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powerpc/mm: Introduce MMU features
[deliverable/linux.git] / arch / powerpc / include / asm / cputable.h
CommitLineData
10b35d99
KG		 1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
10b35d99
KG		 4#define PPC_FEATURE_32 0x80000000
5#define PPC_FEATURE_64 0x40000000
6#define PPC_FEATURE_601_INSTR 0x20000000
7#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
8#define PPC_FEATURE_HAS_FPU 0x08000000
9#define PPC_FEATURE_HAS_MMU 0x04000000
10#define PPC_FEATURE_HAS_4xxMAC 0x02000000
11#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
12#define PPC_FEATURE_HAS_SPE 0x00800000
13#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
14#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
98599013 15#define PPC_FEATURE_NO_TB 0x00100000
a7ddc5e8
PM		 16#define PPC_FEATURE_POWER4 0x00080000
17#define PPC_FEATURE_POWER5 0x00040000
18#define PPC_FEATURE_POWER5_PLUS 0x00020000
19#define PPC_FEATURE_CELL 0x00010000
80f15dc7 20#define PPC_FEATURE_BOOKE 0x00008000
aa5cb021
BH		 21#define PPC_FEATURE_SMT 0x00004000
22#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
03054d51 23#define PPC_FEATURE_ARCH_2_05 0x00001000
b3ebd1d8 24#define PPC_FEATURE_PA6T 0x00000800
974a76f5
PM		 25#define PPC_FEATURE_HAS_DFP 0x00000400
26#define PPC_FEATURE_POWER6_EXT 0x00000200
e952e6c4 27#define PPC_FEATURE_ARCH_2_06 0x00000100
b962ce9d 28#define PPC_FEATURE_HAS_VSX 0x00000080
10b35d99 29
0f473314
NL		 30#define PPC_FEATURE_PSERIES_PERFMON_COMPAT \
31 0x00000040
32
fab5db97
PM		 33#define PPC_FEATURE_TRUE_LE 0x00000002
34#define PPC_FEATURE_PPC_LE 0x00000001
35
10b35d99 36#ifdef __KERNEL__
d1cdcf22
AB		 37
38#include <asm/asm-compat.h>
c5157e58 39#include <asm/feature-fixups.h>
d1cdcf22 40
10b35d99
KG		 41#ifndef __ASSEMBLY__
42
43/* This structure can grow, it's real size is used by head.S code
44 * via the mkdefs mechanism.
45 */
46struct cpu_spec;
10b35d99 47
10b35d99 48typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
f39b7a55 49typedef void (*cpu_restore_t)(void);
10b35d99 50
32a33994 51enum powerpc_oprofile_type {
7a45fb19
AW		 52 PPC_OPROFILE_INVALID = 0,
53 PPC_OPROFILE_RS64 = 1,
54 PPC_OPROFILE_POWER4 = 2,
55 PPC_OPROFILE_G4 = 3,
39aef685 56 PPC_OPROFILE_FSL_EMB = 4,
18f2190d 57 PPC_OPROFILE_CELL = 5,
25fc530e 58 PPC_OPROFILE_PA6T = 6,
32a33994
AB		 59};
60
1bd2e5ae
OJ		 61enum powerpc_pmc_type {
62 PPC_PMC_DEFAULT = 0,
63 PPC_PMC_IBM = 1,
64 PPC_PMC_PA6T = 2,
b950bdd0 65 PPC_PMC_G4 = 3,
1bd2e5ae
OJ		 66};
67
47c0bd1a
BH		 68struct pt_regs;
69
70extern int machine_check_generic(struct pt_regs *regs);
71extern int machine_check_4xx(struct pt_regs *regs);
72extern int machine_check_440A(struct pt_regs *regs);
73extern int machine_check_e500(struct pt_regs *regs);
74extern int machine_check_e200(struct pt_regs *regs);
75
87a72f9e 76/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
10b35d99
KG		 77struct cpu_spec {
78 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
79 unsigned int pvr_mask;
80 unsigned int pvr_value;
81
82 char *cpu_name;
83 unsigned long cpu_features; /* Kernel features */
84 unsigned int cpu_user_features; /* Userland features */
7c03d653 85 unsigned int mmu_features; /* MMU features */
10b35d99
KG		 86
87 /* cache line sizes */
88 unsigned int icache_bsize;
89 unsigned int dcache_bsize;
90
91 /* number of performance monitor counters */
92 unsigned int num_pmcs;
1bd2e5ae 93 enum powerpc_pmc_type pmc_type;
10b35d99
KG		 94
95 /* this is called to initialize various CPU bits like L1 cache,
96 * BHT, SPD, etc... from head.S before branching to identify_machine
97 */
98 cpu_setup_t cpu_setup;
f39b7a55
OJ		 99 /* Used to restore cpu setup on secondary processors and at resume */
100 cpu_restore_t cpu_restore;
10b35d99
KG		 101
102 /* Used by oprofile userspace to select the right counters */
103 char *oprofile_cpu_type;
104
105 /* Processor specific oprofile operations */
32a33994 106 enum powerpc_oprofile_type oprofile_type;
80f15dc7 107
e78dbc80
MN		 108 /* Bit locations inside the mmcra change */
109 unsigned long oprofile_mmcra_sihv;
110 unsigned long oprofile_mmcra_sipr;
111
112 /* Bits to clear during an oprofile exception */
113 unsigned long oprofile_mmcra_clear;
114
80f15dc7
PM		 115 /* Name of processor class, for the ELF AT_PLATFORM entry */
116 char *platform;
47c0bd1a
BH		 117
118 /* Processor specific machine check handling. Return negative
119 * if the error is fatal, 1 if it was fully recovered and 0 to
120 * pass up (not CPU originated) */
121 int (*machine_check)(struct pt_regs *regs);
10b35d99
KG		 122};
123
10b35d99 124extern struct cpu_spec *cur_cpu_spec;
10b35d99 125
42c4aaad
BH		 126extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
127
974a76f5 128extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
0909c8c2
BH		 129extern void do_feature_fixups(unsigned long value, void *fixup_start,
130 void *fixup_end);
9b6b563c 131
9115d134
NL		 132extern const char *powerpc_base_platform;
133
10b35d99
KG		 134#endif /* __ASSEMBLY__ */
135
136/* CPU kernel features */
137
138/* Retain the 32b definitions all use bottom half of word */
4508dc21 139#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000000000000001)
10b35d99
KG		 140#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
141#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
142#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
143#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
144#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
145#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
aba11fc5 146#define CPU_FTR_L2CSR ASM_CONST(0x0000000000000080)
10b35d99 147#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
10b35d99
KG		 148#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
149#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
150#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
151#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
152#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
153#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
10b35d99
KG		 154#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
155#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
3d15910b 156#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
fab5db97
PM		 157#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
158#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
aa42c69c 159#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
4508dc21 160#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
5e14d21e 161#define CPU_FTR_SPE ASM_CONST(0x0000000002000000)
b64f87c1 162#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000)
2d1b2027 163#define CPU_FTR_LWSYNC ASM_CONST(0x0000000008000000)
8309ce72 164#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000010000000)
6d2170be 165#define CPU_FTR_INDEXED_DCR ASM_CONST(0x0000000020000000)
10b35d99 166
3965f8c5
PM		 167/*
168 * Add the 64-bit processor unique features in the top half of the word;
169 * on 32-bit, make the names available but defined to be 0.
170 */
10b35d99 171#ifdef __powerpc64__
3965f8c5 172#define LONG_ASM_CONST(x) ASM_CONST(x)
10b35d99 173#else
3965f8c5 174#define LONG_ASM_CONST(x) 0
10b35d99
KG		 175#endif
176
3965f8c5
PM		 177#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
178#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
179#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
3965f8c5
PM		 180#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
181#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
182#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
183#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
3965f8c5
PM		 184#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
185#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
186#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
187#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
859deea9 188#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
974a76f5 189#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
4c198557 190#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
1189be65 191#define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000)
f66bce5e 192#define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000)
b962ce9d 193#define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000)
37907049 194#define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000)
2a929436 195#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0040000000000000)
4ec577a2 196#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0080000000000000)
3965f8c5 197
10b35d99
KG		 198#ifndef __ASSEMBLY__
199
0470466d
SR		 200#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \
201 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
202 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
10b35d99
KG		 203
204/* We only set the altivec features if the kernel was compiled with altivec
205 * support
206 */
207#ifdef CONFIG_ALTIVEC
208#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
209#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
210#else
211#define CPU_FTR_ALTIVEC_COMP 0
212#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
213#endif
214
b962ce9d
MN		 215/* We only set the VSX features if the kernel was compiled with VSX
216 * support
217 */
218#ifdef CONFIG_VSX
219#define CPU_FTR_VSX_COMP CPU_FTR_VSX
220#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
221#else
222#define CPU_FTR_VSX_COMP 0
223#define PPC_FEATURE_HAS_VSX_COMP 0
224#endif
225
5e14d21e
KG		 226/* We only set the spe features if the kernel was compiled with spe
227 * support
228 */
229#ifdef CONFIG_SPE
230#define CPU_FTR_SPE_COMP CPU_FTR_SPE
231#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
232#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
233#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
234#else
235#define CPU_FTR_SPE_COMP 0
236#define PPC_FEATURE_HAS_SPE_COMP 0
237#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
238#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
239#endif
240
11af1192
SW		 241/* We need to mark all pages as being coherent if we're SMP or we have a
242 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
243 * require it for PCI "streaming/prefetch" to work properly.
10b35d99 244 */
1775dbbc 245#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
11af1192 246 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260)
10b35d99
KG		 247#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
248#else
249#define CPU_FTR_COMMON 0
250#endif
251
252/* The powersave features NAP & DOZE seems to confuse BDI when
253 debugging. So if a BDI is used, disable theses
254 */
255#ifndef CONFIG_BDI_SWITCH
256#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
257#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
258#else
259#define CPU_FTR_MAYBE_CAN_DOZE 0
260#define CPU_FTR_MAYBE_CAN_NAP 0
261#endif
262
263#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
264 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
265 !defined(CONFIG_BOOKE))
266
7c03d653 267#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
4508dc21
DG		 268 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
269#define CPU_FTRS_603 (CPU_FTR_COMMON | \
7c92943c 270 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
fab5db97 271 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 272#define CPU_FTRS_604 (CPU_FTR_COMMON | \
7c03d653 273 CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
4508dc21 274#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
7c92943c 275 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 276 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 277#define CPU_FTRS_740 (CPU_FTR_COMMON | \
7c92943c 278 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 279 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 280 CPU_FTR_PPC_LE)
4508dc21 281#define CPU_FTRS_750 (CPU_FTR_COMMON | \
7c92943c 282 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 283 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 284 CPU_FTR_PPC_LE)
7c03d653 285#define CPU_FTRS_750CL (CPU_FTRS_750)
b6f41cc8
JB		 286#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
287#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
7c03d653 288#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
b6f41cc8 289#define CPU_FTRS_750GX (CPU_FTRS_750FX)
4508dc21 290#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
7c92943c 291 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 292 CPU_FTR_ALTIVEC_COMP | \
fab5db97 293 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 294#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
7c92943c 295 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 296 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
fab5db97 297 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 298#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
7c92943c 299 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 300 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
b64f87c1 301 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 302#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
7c92943c
SR		 303 CPU_FTR_USE_TB | \
304 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 305 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
7c92943c 306 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
b64f87c1 307 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 308#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
b64f87c1 309 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 310 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 311 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
fab5db97 312 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 313#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
b64f87c1 314 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 315 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
7c03d653 316 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 317#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
b64f87c1 318 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 319 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 320 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
7c92943c 321 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
7c03d653 322 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 323#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
7c92943c
SR		 324 CPU_FTR_USE_TB | \
325 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 326 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 327 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 328#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
7c92943c
SR		 329 CPU_FTR_USE_TB | \
330 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 331 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1
BB		 332 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
333 CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 334#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
7c92943c
SR		 335 CPU_FTR_USE_TB | \
336 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 337 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 338 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 339#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
7c92943c
SR		 340 CPU_FTR_USE_TB | \
341 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 342 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 343 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 344#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
3d372548
JY		 345 CPU_FTR_USE_TB | \
346 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 347 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 348 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 349#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
7c92943c 350 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
11af1192 351#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 352 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
4508dc21 353#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 354 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
7c92943c 355 CPU_FTR_COMMON)
4508dc21 356#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 357 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
aa42c69c 358 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
7c03d653 359#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB)
4508dc21 360#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
8309ce72
BH		 361#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
362#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
6d2170be
BH		 363#define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
364 CPU_FTR_INDEXED_DCR)
5e14d21e
KG		 365#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
366 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
8309ce72 367 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE)
fc4033b2 368#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
8309ce72
BH		 369 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
370 CPU_FTR_NOEXECUTE)
fc4033b2 371#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
7c03d653 372 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
8309ce72 373 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
fc4033b2 374#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
7c03d653 375 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
8309ce72 376 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE)
7c92943c 377#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
0b8e2e13
ME		 378
379/* 64-bit CPUs */
2d1b2027 380#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 381 CPU_FTR_IABR | CPU_FTR_PPC_LE)
2d1b2027 382#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 383 CPU_FTR_IABR | \
7c92943c 384 CPU_FTR_MMCRA | CPU_FTR_CTRL)
2d1b2027 385#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 386 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
2a929436 387 CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ)
2d1b2027 388#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 389 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
2a929436
MN		 390 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
391 CPU_FTR_CP_USE_DCBTZ)
2d1b2027 392#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 393 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c
SR		 394 CPU_FTR_MMCRA | CPU_FTR_SMT | \
395 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
e78dbc80 396 CPU_FTR_PURR)
2d1b2027 397#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 398 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
03054d51
AB		 399 CPU_FTR_MMCRA | CPU_FTR_SMT | \
400 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
4c198557 401 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
4ec577a2 402 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD)
2d1b2027 403#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 404 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
e952e6c4
MN		 405 CPU_FTR_MMCRA | CPU_FTR_SMT | \
406 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
407 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
37907049 408 CPU_FTR_DSCR | CPU_FTR_SAO)
2d1b2027 409#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 410 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 411 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
2a929436 412 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | \
4ec577a2
MN		 413 CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
414 CPU_FTR_UNALIGNED_LD_STD)
2d1b2027 415#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 416 CPU_FTR_PPCAS_ARCH_V2 | \
b3ebd1d8 417 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
f66bce5e 418 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
7c03d653 419#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
10b35d99 420
2406f606 421#ifdef __powerpc64__
7c92943c
SR		 422#define CPU_FTRS_POSSIBLE \
423 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
03054d51 424 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
e952e6c4 425 CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
b962ce9d 426 CPU_FTR_1T_SEGMENT | CPU_FTR_VSX)
2406f606 427#else
7c92943c
SR		 428enum {
429 CPU_FTRS_POSSIBLE =
10b35d99
KG		 430#if CLASSIC_PPC
431 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
432 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
433 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
434 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
435 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
436 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
437 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
aa42c69c
KP		 438 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
439 CPU_FTRS_CLASSIC32 |
10b35d99
KG		 440#else
441 CPU_FTRS_GENERIC_32 |
442#endif
10b35d99
KG		 443#ifdef CONFIG_8xx
444 CPU_FTRS_8XX |
445#endif
446#ifdef CONFIG_40x
447 CPU_FTRS_40X |
448#endif
449#ifdef CONFIG_44x
6d2170be 450 CPU_FTRS_44X | CPU_FTRS_440x6 |
10b35d99
KG		 451#endif
452#ifdef CONFIG_E200
453 CPU_FTRS_E200 |
454#endif
455#ifdef CONFIG_E500
3dfa8773 456 CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC |
10b35d99 457#endif
10b35d99 458 0,
7c92943c
SR		 459};
460#endif /* __powerpc64__ */
10b35d99 461
2406f606 462#ifdef __powerpc64__
7c92943c
SR		 463#define CPU_FTRS_ALWAYS \
464 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
03054d51 465 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
e952e6c4 466 CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
2406f606 467#else
7c92943c
SR		 468enum {
469 CPU_FTRS_ALWAYS =
10b35d99
KG		 470#if CLASSIC_PPC
471 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
472 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
473 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
474 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
475 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
476 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
477 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
aa42c69c
KP		 478 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
479 CPU_FTRS_CLASSIC32 &
10b35d99
KG		 480#else
481 CPU_FTRS_GENERIC_32 &
482#endif
10b35d99
KG		 483#ifdef CONFIG_8xx
484 CPU_FTRS_8XX &
485#endif
486#ifdef CONFIG_40x
487 CPU_FTRS_40X &
488#endif
489#ifdef CONFIG_44x
6d2170be 490 CPU_FTRS_44X & CPU_FTRS_440x6 &
10b35d99
KG		 491#endif
492#ifdef CONFIG_E200
493 CPU_FTRS_E200 &
494#endif
495#ifdef CONFIG_E500
3dfa8773 496 CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC &
10b35d99 497#endif
10b35d99
KG		 498 CPU_FTRS_POSSIBLE,
499};
7c92943c 500#endif /* __powerpc64__ */
10b35d99
KG		 501
502static inline int cpu_has_feature(unsigned long feature)
503{
504 return (CPU_FTRS_ALWAYS & feature) ||
505 (CPU_FTRS_POSSIBLE
10b35d99 506 & cur_cpu_spec->cpu_features
10b35d99
KG		 507 & feature);
508}
509
510#endif /* !__ASSEMBLY__ */
511
10b35d99
KG		 512#endif /* __KERNEL__ */
513#endif /* __ASM_POWERPC_CPUTABLE_H */
Linux kernel - Deliverables
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