Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
78b09735 SR |
2 | * Copyright (C) 2004 IBM |
3 | * | |
4 | * Implements the generic device dma API for powerpc. | |
5 | * the pci and vio busses | |
1da177e4 | 6 | */ |
78b09735 SR |
7 | #ifndef _ASM_DMA_MAPPING_H |
8 | #define _ASM_DMA_MAPPING_H | |
33ff910f AB |
9 | #ifdef __KERNEL__ |
10 | ||
11 | #include <linux/types.h> | |
12 | #include <linux/cache.h> | |
13 | /* need struct page definitions */ | |
14 | #include <linux/mm.h> | |
15 | #include <linux/scatterlist.h> | |
3affedc4 | 16 | #include <linux/dma-attrs.h> |
46bab4e4 | 17 | #include <linux/dma-debug.h> |
33ff910f | 18 | #include <asm/io.h> |
ec3cf2ec | 19 | #include <asm/swiotlb.h> |
33ff910f AB |
20 | |
21 | #define DMA_ERROR_CODE (~(dma_addr_t)0x0) | |
22 | ||
ec3cf2ec BB |
23 | /* Some dma direct funcs must be visible for use in other dma_ops */ |
24 | extern void *dma_direct_alloc_coherent(struct device *dev, size_t size, | |
25 | dma_addr_t *dma_handle, gfp_t flag); | |
26 | extern void dma_direct_free_coherent(struct device *dev, size_t size, | |
27 | void *vaddr, dma_addr_t dma_handle); | |
28 | ||
ec3cf2ec | 29 | |
33ff910f AB |
30 | #ifdef CONFIG_NOT_COHERENT_CACHE |
31 | /* | |
32 | * DMA-consistent mapping functions for PowerPCs that don't support | |
33 | * cache snooping. These allocate/free a region of uncached mapped | |
34 | * memory space for use with DMA devices. Alternatively, you could | |
35 | * allocate the space "normally" and use the cache management functions | |
36 | * to ensure it is consistent. | |
37 | */ | |
8b31e49d BH |
38 | struct device; |
39 | extern void *__dma_alloc_coherent(struct device *dev, size_t size, | |
40 | dma_addr_t *handle, gfp_t gfp); | |
33ff910f AB |
41 | extern void __dma_free_coherent(size_t size, void *vaddr); |
42 | extern void __dma_sync(void *vaddr, size_t size, int direction); | |
43 | extern void __dma_sync_page(struct page *page, unsigned long offset, | |
44 | size_t size, int direction); | |
45 | ||
46 | #else /* ! CONFIG_NOT_COHERENT_CACHE */ | |
47 | /* | |
48 | * Cache coherent cores. | |
49 | */ | |
50 | ||
8b31e49d | 51 | #define __dma_alloc_coherent(dev, gfp, size, handle) NULL |
33ff910f AB |
52 | #define __dma_free_coherent(size, addr) ((void)0) |
53 | #define __dma_sync(addr, size, rw) ((void)0) | |
54 | #define __dma_sync_page(pg, off, sz, rw) ((void)0) | |
55 | ||
56 | #endif /* ! CONFIG_NOT_COHERENT_CACHE */ | |
57 | ||
3a4c6f0b MN |
58 | static inline unsigned long device_to_mask(struct device *dev) |
59 | { | |
60 | if (dev->dma_mask && *dev->dma_mask) | |
61 | return *dev->dma_mask; | |
62 | /* Assume devices without mask can take 32 bit addresses */ | |
63 | return 0xfffffffful; | |
64 | } | |
65 | ||
4fc665b8 BB |
66 | /* |
67 | * Available generic sets of operations | |
68 | */ | |
69 | #ifdef CONFIG_PPC64 | |
45223c54 | 70 | extern struct dma_map_ops dma_iommu_ops; |
4fc665b8 | 71 | #endif |
45223c54 | 72 | extern struct dma_map_ops dma_direct_ops; |
4fc665b8 | 73 | |
45223c54 | 74 | static inline struct dma_map_ops *get_dma_ops(struct device *dev) |
33ff910f AB |
75 | { |
76 | /* We don't handle the NULL dev case for ISA for now. We could | |
77 | * do it via an out of line call but it is not needed for now. The | |
78 | * only ISA DMA device we support is the floppy and we have a hack | |
79 | * in the floppy driver directly to get a device for us. | |
80 | */ | |
4ae0ff60 | 81 | if (unlikely(dev == NULL)) |
33ff910f | 82 | return NULL; |
4fc665b8 | 83 | |
33ff910f | 84 | return dev->archdata.dma_ops; |
1f62a162 ME |
85 | } |
86 | ||
45223c54 | 87 | static inline void set_dma_ops(struct device *dev, struct dma_map_ops *ops) |
1f62a162 ME |
88 | { |
89 | dev->archdata.dma_ops = ops; | |
33ff910f AB |
90 | } |
91 | ||
1cebd7a0 BB |
92 | /* |
93 | * get_dma_offset() | |
94 | * | |
95 | * Get the dma offset on configurations where the dma address can be determined | |
96 | * from the physical address by looking at a simple offset. Direct dma and | |
97 | * swiotlb use this function, but it is typically not used by implementations | |
98 | * with an iommu. | |
99 | */ | |
100 | static inline unsigned long get_dma_offset(struct device *dev) | |
101 | { | |
102 | if (dev) | |
103 | return (unsigned long)dev->archdata.dma_data; | |
104 | ||
105 | return PCI_DRAM_OFFSET; | |
106 | } | |
107 | ||
46bab4e4 FT |
108 | /* this will be removed soon */ |
109 | #define flush_write_buffers() | |
110 | ||
111 | #include <asm-generic/dma-mapping-common.h> | |
112 | ||
33ff910f AB |
113 | static inline int dma_supported(struct device *dev, u64 mask) |
114 | { | |
45223c54 | 115 | struct dma_map_ops *dma_ops = get_dma_ops(dev); |
33ff910f AB |
116 | |
117 | if (unlikely(dma_ops == NULL)) | |
118 | return 0; | |
119 | if (dma_ops->dma_supported == NULL) | |
120 | return 1; | |
121 | return dma_ops->dma_supported(dev, mask); | |
122 | } | |
123 | ||
84631f37 ME |
124 | /* We have our own implementation of pci_set_dma_mask() */ |
125 | #define HAVE_ARCH_PCI_SET_DMA_MASK | |
126 | ||
33ff910f AB |
127 | static inline int dma_set_mask(struct device *dev, u64 dma_mask) |
128 | { | |
45223c54 | 129 | struct dma_map_ops *dma_ops = get_dma_ops(dev); |
33ff910f AB |
130 | |
131 | if (unlikely(dma_ops == NULL)) | |
132 | return -EIO; | |
133 | if (dma_ops->set_dma_mask != NULL) | |
134 | return dma_ops->set_dma_mask(dev, dma_mask); | |
135 | if (!dev->dma_mask || !dma_supported(dev, dma_mask)) | |
136 | return -EIO; | |
137 | *dev->dma_mask = dma_mask; | |
138 | return 0; | |
139 | } | |
140 | ||
141 | static inline void *dma_alloc_coherent(struct device *dev, size_t size, | |
142 | dma_addr_t *dma_handle, gfp_t flag) | |
143 | { | |
45223c54 | 144 | struct dma_map_ops *dma_ops = get_dma_ops(dev); |
80d3e8ab | 145 | void *cpu_addr; |
33ff910f AB |
146 | |
147 | BUG_ON(!dma_ops); | |
80d3e8ab FT |
148 | |
149 | cpu_addr = dma_ops->alloc_coherent(dev, size, dma_handle, flag); | |
150 | ||
151 | debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr); | |
152 | ||
153 | return cpu_addr; | |
33ff910f AB |
154 | } |
155 | ||
156 | static inline void dma_free_coherent(struct device *dev, size_t size, | |
157 | void *cpu_addr, dma_addr_t dma_handle) | |
158 | { | |
45223c54 | 159 | struct dma_map_ops *dma_ops = get_dma_ops(dev); |
33ff910f AB |
160 | |
161 | BUG_ON(!dma_ops); | |
80d3e8ab FT |
162 | |
163 | debug_dma_free_coherent(dev, size, cpu_addr, dma_handle); | |
164 | ||
33ff910f AB |
165 | dma_ops->free_coherent(dev, size, cpu_addr, dma_handle); |
166 | } | |
167 | ||
8d8bb39b | 168 | static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) |
78b09735 | 169 | { |
4a9a6bfe FT |
170 | struct dma_map_ops *dma_ops = get_dma_ops(dev); |
171 | ||
172 | if (dma_ops->mapping_error) | |
173 | return dma_ops->mapping_error(dev, dma_addr); | |
174 | ||
78b09735 SR |
175 | #ifdef CONFIG_PPC64 |
176 | return (dma_addr == DMA_ERROR_CODE); | |
177 | #else | |
178 | return 0; | |
179 | #endif | |
180 | } | |
181 | ||
9a937c91 FT |
182 | static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size) |
183 | { | |
762afb73 FT |
184 | #ifdef CONFIG_SWIOTLB |
185 | struct dev_archdata *sd = &dev->archdata; | |
9a937c91 | 186 | |
762afb73 | 187 | if (sd->max_direct_dma_addr && addr + size > sd->max_direct_dma_addr) |
9a937c91 | 188 | return 0; |
762afb73 | 189 | #endif |
9a937c91 FT |
190 | |
191 | if (!dev->dma_mask) | |
192 | return 0; | |
193 | ||
194 | return addr + size <= *dev->dma_mask; | |
195 | } | |
196 | ||
8d4f5339 FT |
197 | static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) |
198 | { | |
1cebd7a0 | 199 | return paddr + get_dma_offset(dev); |
8d4f5339 FT |
200 | } |
201 | ||
202 | static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr) | |
203 | { | |
1cebd7a0 | 204 | return daddr - get_dma_offset(dev); |
8d4f5339 FT |
205 | } |
206 | ||
1da177e4 LT |
207 | #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) |
208 | #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) | |
209 | #ifdef CONFIG_NOT_COHERENT_CACHE | |
f67637ee | 210 | #define dma_is_consistent(d, h) (0) |
1da177e4 | 211 | #else |
f67637ee | 212 | #define dma_is_consistent(d, h) (1) |
1da177e4 LT |
213 | #endif |
214 | ||
215 | static inline int dma_get_cache_alignment(void) | |
216 | { | |
78b09735 SR |
217 | #ifdef CONFIG_PPC64 |
218 | /* no easy way to get cache size on all processors, so return | |
219 | * the maximum possible, to be safe */ | |
1fd73c6b | 220 | return (1 << INTERNODE_CACHE_SHIFT); |
78b09735 | 221 | #else |
1da177e4 LT |
222 | /* |
223 | * Each processor family will define its own L1_CACHE_SHIFT, | |
224 | * L1_CACHE_BYTES wraps to this, so this is always safe. | |
225 | */ | |
226 | return L1_CACHE_BYTES; | |
78b09735 | 227 | #endif |
1da177e4 LT |
228 | } |
229 | ||
d3fa72e4 | 230 | static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size, |
78b09735 | 231 | enum dma_data_direction direction) |
1da177e4 | 232 | { |
78b09735 | 233 | BUG_ON(direction == DMA_NONE); |
1da177e4 LT |
234 | __dma_sync(vaddr, size, (int)direction); |
235 | } | |
236 | ||
88ced031 | 237 | #endif /* __KERNEL__ */ |
78b09735 | 238 | #endif /* _ASM_DMA_MAPPING_H */ |