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powerpc/book3s: Fix CFAR clobbering issue in machine check handler.
[deliverable/linux.git] / arch / powerpc / include / asm / exception-64s.h
CommitLineData
f9ff0f30
SR		 1#ifndef _ASM_POWERPC_EXCEPTION_H
2#define _ASM_POWERPC_EXCEPTION_H
3/*
4 * Extracted from head_64.S
5 *
6 * PowerPC version
7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 *
9 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
10 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
11 * Adapted for Power Macintosh by Paul Mackerras.
12 * Low-level exception handlers and MMU support
13 * rewritten by Paul Mackerras.
14 * Copyright (C) 1996 Paul Mackerras.
15 *
16 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
17 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
18 *
19 * This file contains the low-level support and setup for the
20 * PowerPC-64 platform, including trap and interrupt dispatch.
21 *
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License
24 * as published by the Free Software Foundation; either version
25 * 2 of the License, or (at your option) any later version.
26 */
27/*
28 * The following macros define the code that appears as
29 * the prologue to each of the exception handlers. They
30 * are split into two parts to allow a single kernel binary
31 * to be used for pSeries and iSeries.
32 *
33 * We make as much of the exception code common between native
34 * exception handlers (including pSeries LPAR) and iSeries LPAR
35 * implementations as possible.
36 */
37
38#define EX_R9 0
39#define EX_R10 8
40#define EX_R11 16
41#define EX_R12 24
42#define EX_R13 32
43#define EX_SRR0 40
44#define EX_DAR 48
45#define EX_DSISR 56
46#define EX_CCR 60
47#define EX_R3 64
48#define EX_LR 72
48404f2e 49#define EX_CFAR 80
a09688cd 50#define EX_PPR 88 /* SMT thread status register (priority) */
bc2e6c6a 51#define EX_CTR 96
f9ff0f30 52
4700dfaf 53#ifdef CONFIG_RELOCATABLE
1707dd16 54#define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \
4700dfaf
MN		 55 ld r12,PACAKBASE(r13); /* get high part of &label */ \
56 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \
57 LOAD_HANDLER(r12,label); \
bc2e6c6a 58 mtctr r12; \
4700dfaf
MN		 59 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \
60 li r10,MSR_RI; \
61 mtmsrd r10,1; /* Set RI (EE=0) */ \
bc2e6c6a 62 bctr;
4700dfaf
MN		 63#else
64/* If not relocatable, we can jump directly -- and save messing with LR */
1707dd16 65#define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \
4700dfaf
MN		 66 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \
67 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \
68 li r10,MSR_RI; \
69 mtmsrd r10,1; /* Set RI (EE=0) */ \
70 b label;
71#endif
1707dd16
PM		 72#define EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \
73 __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \
4700dfaf
MN		 74
75/*
76 * As EXCEPTION_PROLOG_PSERIES(), except we've already got relocation on
77 * so no need to rfid. Save lr in case we're CONFIG_RELOCATABLE, in which
78 * case EXCEPTION_RELON_PROLOG_PSERIES_1 will be using lr.
79 */
80#define EXCEPTION_RELON_PROLOG_PSERIES(area, label, h, extra, vec) \
1707dd16 81 EXCEPTION_PROLOG_0(area); \
4700dfaf
MN		 82 EXCEPTION_PROLOG_1(area, extra, vec); \
83 EXCEPTION_RELON_PROLOG_PSERIES_1(label, h)
84
f9ff0f30
SR		 85/*
86 * We're short on space and time in the exception prolog, so we can't
87 * use the normal SET_REG_IMMEDIATE macro. Normally we just need the
88 * low halfword of the address, but for Kdump we need the whole low
89 * word.
90 */
f9ff0f30 91#define LOAD_HANDLER(reg, label) \
61e2390e
MN		 92 /* Handlers must be within 64K of kbase, which must be 64k aligned */ \
93 ori reg,reg,(label)-_stext; /* virt addr of handler ... */
f9ff0f30 94
a5d4f3ad
BH		 95/* Exception register prefixes */
96#define EXC_HV H
97#define EXC_STD
98
4700dfaf
MN		 99#if defined(CONFIG_RELOCATABLE)
100/*
bc2e6c6a
MN		 101 * If we support interrupts with relocation on AND we're a relocatable kernel,
102 * we need to use CTR to get to the 2nd level handler. So, save/restore it
103 * when required.
4700dfaf 104 */
bc2e6c6a
MN		 105#define SAVE_CTR(reg, area) mfctr reg ; std reg,area+EX_CTR(r13)
106#define GET_CTR(reg, area) ld reg,area+EX_CTR(r13)
107#define RESTORE_CTR(reg, area) ld reg,area+EX_CTR(r13) ; mtctr reg
4700dfaf 108#else
bc2e6c6a
MN		 109/* ...else CTR is unused and in register. */
110#define SAVE_CTR(reg, area)
111#define GET_CTR(reg, area) mfctr reg
112#define RESTORE_CTR(reg, area)
4700dfaf
MN		 113#endif
114
13e7a8e8
HM		 115/*
116 * PPR save/restore macros used in exceptions_64s.S
117 * Used for P7 or later processors
118 */
119#define SAVE_PPR(area, ra, rb) \
120BEGIN_FTR_SECTION_NESTED(940) \
121 ld ra,PACACURRENT(r13); \
122 ld rb,area+EX_PPR(r13); /* Read PPR from paca */ \
123 std rb,TASKTHREADPPR(ra); \
124END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940)
125
126#define RESTORE_PPR_PACA(area, ra) \
127BEGIN_FTR_SECTION_NESTED(941) \
128 ld ra,area+EX_PPR(r13); \
129 mtspr SPRN_PPR,ra; \
130END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941)
131
132/*
133 * Increase the priority on systems where PPR save/restore is not
134 * implemented/ supported.
135 */
136#define HMT_MEDIUM_PPR_DISCARD \
137BEGIN_FTR_SECTION_NESTED(942) \
138 HMT_MEDIUM; \
139END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,0,942) /*non P7*/
140
141/*
1707dd16 142 * Get an SPR into a register if the CPU has the given feature
13e7a8e8 143 */
1707dd16 144#define OPT_GET_SPR(ra, spr, ftr) \
13e7a8e8 145BEGIN_FTR_SECTION_NESTED(943) \
1707dd16
PM		 146 mfspr ra,spr; \
147END_FTR_SECTION_NESTED(ftr,ftr,943)
13e7a8e8 148
d410ae21
MS		 149/*
150 * Set an SPR from a register if the CPU has the given feature
151 */
152#define OPT_SET_SPR(ra, spr, ftr) \
153BEGIN_FTR_SECTION_NESTED(943) \
154 mtspr spr,ra; \
155END_FTR_SECTION_NESTED(ftr,ftr,943)
156
1707dd16
PM		 157/*
158 * Save a register to the PACA if the CPU has the given feature
159 */
160#define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \
161BEGIN_FTR_SECTION_NESTED(943) \
162 std ra,offset(r13); \
163END_FTR_SECTION_NESTED(ftr,ftr,943)
164
165#define EXCEPTION_PROLOG_0(area) \
2dd60d79 166 GET_PACA(r13); \
44e9309f 167 std r9,area+EX_R9(r13); /* save r9 */ \
1707dd16
PM		 168 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); \
169 HMT_MEDIUM; \
44e9309f 170 std r10,area+EX_R10(r13); /* save r10 - r12 */ \
1707dd16
PM		 171 OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR)
172
173#define __EXCEPTION_PROLOG_1(area, extra, vec) \
174 OPT_SAVE_REG_TO_PACA(area+EX_PPR, r9, CPU_FTR_HAS_PPR); \
175 OPT_SAVE_REG_TO_PACA(area+EX_CFAR, r10, CPU_FTR_CFAR); \
bc2e6c6a 176 SAVE_CTR(r10, area); \
b01c8b54
PM		 177 mfcr r9; \
178 extra(vec); \
179 std r11,area+EX_R11(r13); \
180 std r12,area+EX_R12(r13); \
181 GET_SCRATCH0(r10); \
182 std r10,area+EX_R13(r13)
183#define EXCEPTION_PROLOG_1(area, extra, vec) \
184 __EXCEPTION_PROLOG_1(area, extra, vec)
7180e3e6 185
a5d4f3ad 186#define __EXCEPTION_PROLOG_PSERIES_1(label, h) \
1f6a93e4
PM		 187 ld r12,PACAKBASE(r13); /* get high part of &label */ \
188 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \
a5d4f3ad 189 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \
f9ff0f30 190 LOAD_HANDLER(r12,label) \
a5d4f3ad
BH		 191 mtspr SPRN_##h##SRR0,r12; \
192 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \
193 mtspr SPRN_##h##SRR1,r10; \
194 h##rfid; \
f9ff0f30 195 b . /* prevent speculative execution */
b01c8b54 196#define EXCEPTION_PROLOG_PSERIES_1(label, h) \
a5d4f3ad 197 __EXCEPTION_PROLOG_PSERIES_1(label, h)
f9ff0f30 198
b01c8b54 199#define EXCEPTION_PROLOG_PSERIES(area, label, h, extra, vec) \
1707dd16 200 EXCEPTION_PROLOG_0(area); \
b01c8b54 201 EXCEPTION_PROLOG_1(area, extra, vec); \
a5d4f3ad 202 EXCEPTION_PROLOG_PSERIES_1(label, h);
c5a8c0c9 203
b01c8b54 204#define __KVMTEST(n) \
3c42bf8a 205 lbz r10,HSTATE_IN_GUEST(r13); \
b01c8b54
PM		 206 cmpwi r10,0; \
207 bne do_kvm_##n
208
dd96b2c2
AK		 209#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
210/*
211 * If hv is possible, interrupts come into to the hv version
212 * of the kvmppc_interrupt code, which then jumps to the PR handler,
213 * kvmppc_interrupt_pr, if the guest is a PR guest.
214 */
215#define kvmppc_interrupt kvmppc_interrupt_hv
216#else
217#define kvmppc_interrupt kvmppc_interrupt_pr
218#endif
219
b01c8b54
PM		 220#define __KVM_HANDLER(area, h, n) \
221do_kvm_##n: \
0acb9111
PM		 222 BEGIN_FTR_SECTION_NESTED(947) \
223 ld r10,area+EX_CFAR(r13); \
224 std r10,HSTATE_CFAR(r13); \
225 END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947); \
4b8473c9
PM		 226 BEGIN_FTR_SECTION_NESTED(948) \
227 ld r10,area+EX_PPR(r13); \
228 std r10,HSTATE_PPR(r13); \
229 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \
b01c8b54 230 ld r10,area+EX_R10(r13); \
0acb9111 231 stw r9,HSTATE_SCRATCH1(r13); \
b01c8b54 232 ld r9,area+EX_R9(r13); \
0acb9111 233 std r12,HSTATE_SCRATCH0(r13); \
b01c8b54
PM		 234 li r12,n; \
235 b kvmppc_interrupt
236
237#define __KVM_HANDLER_SKIP(area, h, n) \
238do_kvm_##n: \
239 cmpwi r10,KVM_GUEST_MODE_SKIP; \
240 ld r10,area+EX_R10(r13); \
241 beq 89f; \
3c42bf8a 242 stw r9,HSTATE_SCRATCH1(r13); \
4b8473c9
PM		 243 BEGIN_FTR_SECTION_NESTED(948) \
244 ld r9,area+EX_PPR(r13); \
245 std r9,HSTATE_PPR(r13); \
246 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \
b01c8b54 247 ld r9,area+EX_R9(r13); \
3c42bf8a 248 std r12,HSTATE_SCRATCH0(r13); \
b01c8b54
PM		 249 li r12,n; \
250 b kvmppc_interrupt; \
25189: mtocrf 0x80,r9; \
252 ld r9,area+EX_R9(r13); \
253 b kvmppc_skip_##h##interrupt
254
255#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
256#define KVMTEST(n) __KVMTEST(n)
257#define KVM_HANDLER(area, h, n) __KVM_HANDLER(area, h, n)
258#define KVM_HANDLER_SKIP(area, h, n) __KVM_HANDLER_SKIP(area, h, n)
259
260#else
261#define KVMTEST(n)
262#define KVM_HANDLER(area, h, n)
263#define KVM_HANDLER_SKIP(area, h, n)
264#endif
265
7aa79938 266#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
de56a948
PM		 267#define KVMTEST_PR(n) __KVMTEST(n)
268#define KVM_HANDLER_PR(area, h, n) __KVM_HANDLER(area, h, n)
269#define KVM_HANDLER_PR_SKIP(area, h, n) __KVM_HANDLER_SKIP(area, h, n)
270
271#else
272#define KVMTEST_PR(n)
273#define KVM_HANDLER_PR(area, h, n)
274#define KVM_HANDLER_PR_SKIP(area, h, n)
275#endif
276
b01c8b54
PM		 277#define NOTEST(n)
278
f9ff0f30
SR		 279/*
280 * The common exception prolog is used for all except a few exceptions
281 * such as a segment miss on a kernel address. We have to be prepared
282 * to take another exception from the point where we first touch the
283 * kernel stack onwards.
284 *
285 * On entry r13 points to the paca, r9-r13 are saved in the paca,
286 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
287 * SRR1, and relocation is on.
288 */
289#define EXCEPTION_PROLOG_COMMON(n, area) \
290 andi. r10,r12,MSR_PR; /* See if coming from user */ \
291 mr r10,r1; /* Save r1 */ \
292 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
293 beq- 1f; \
294 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
90ff5d68 2951: cmpdi cr1,r1,-INT_FRAME_SIZE; /* check if r1 is in userspace */ \
1977b502
PM		 296 blt+ cr1,3f; /* abort if it is */ \
297 li r1,(n); /* will be reloaded later */ \
f9ff0f30 298 sth r1,PACA_TRAP_SAVE(r13); \
1977b502
PM		 299 std r3,area+EX_R3(r13); \
300 addi r3,r13,area; /* r3 -> where regs are saved*/ \
bc2e6c6a 301 RESTORE_CTR(r1, area); \
f9ff0f30
SR		 302 b bad_stack; \
3033: std r9,_CCR(r1); /* save CR in stackframe */ \
304 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
305 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
306 std r10,0(r1); /* make stack chain pointer */ \
307 std r0,GPR0(r1); /* save r0 in stackframe */ \
308 std r10,GPR1(r1); /* save r1 in stackframe */ \
5d75b264 309 beq 4f; /* if from kernel mode */ \
f9ff0f30 310 ACCOUNT_CPU_USER_ENTRY(r9, r10); \
44e9309f 311 SAVE_PPR(area, r9, r10); \
b14a7253
MS		 3124: EXCEPTION_PROLOG_COMMON_2(area) \
313 EXCEPTION_PROLOG_COMMON_3(n) \
314 ACCOUNT_STOLEN_TIME
315
316/* Save original regs values from save area to stack frame. */
317#define EXCEPTION_PROLOG_COMMON_2(area) \
f9ff0f30
SR		 318 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
319 ld r10,area+EX_R10(r13); \
320 std r9,GPR9(r1); \
321 std r10,GPR10(r1); \
322 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
323 ld r10,area+EX_R12(r13); \
324 ld r11,area+EX_R13(r13); \
325 std r9,GPR11(r1); \
326 std r10,GPR12(r1); \
327 std r11,GPR13(r1); \
48404f2e
PM		 328 BEGIN_FTR_SECTION_NESTED(66); \
329 ld r10,area+EX_CFAR(r13); \
330 std r10,ORIG_GPR3(r1); \
331 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \
b14a7253
MS		 332 GET_CTR(r10, area); \
333 std r10,_CTR(r1);
334
335#define EXCEPTION_PROLOG_COMMON_3(n) \
336 std r2,GPR2(r1); /* save r2 in stackframe */ \
337 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
338 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
bc2e6c6a 339 mflr r9; /* Get LR, later save to stack */ \
f9ff0f30 340 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
f9ff0f30 341 std r9,_LINK(r1); \
f9ff0f30
SR		 342 lbz r10,PACASOFTIRQEN(r13); \
343 mfspr r11,SPRN_XER; /* save XER in stackframe */ \
344 std r10,SOFTE(r1); \
345 std r11,_XER(r1); \
346 li r9,(n)+1; \
347 std r9,_TRAP(r1); /* set trap number */ \
348 li r10,0; \
349 ld r11,exception_marker@toc(r2); \
350 std r10,RESULT(r1); /* clear regs->result */ \
b14a7253 351 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
f9ff0f30
SR		 352
353/*
354 * Exception vectors.
355 */
b3e6b5df
BH		 356#define STD_EXCEPTION_PSERIES(loc, vec, label) \
357 . = loc; \
f9ff0f30
SR		 358 .globl label##_pSeries; \
359label##_pSeries: \
44e9309f 360 HMT_MEDIUM_PPR_DISCARD; \
673b189a 361 SET_SCRATCH0(r13); /* save r13 */ \
b01c8b54 362 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common, \
de56a948 363 EXC_STD, KVMTEST_PR, vec)
f9ff0f30 364
1707dd16
PM		 365/* Version of above for when we have to branch out-of-line */
366#define STD_EXCEPTION_PSERIES_OOL(vec, label) \
367 .globl label##_pSeries; \
368label##_pSeries: \
369 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_PR, vec); \
370 EXCEPTION_PROLOG_PSERIES_1(label##_common, EXC_STD)
371
b3e6b5df
BH		 372#define STD_EXCEPTION_HV(loc, vec, label) \
373 . = loc; \
374 .globl label##_hv; \
375label##_hv: \
44e9309f 376 HMT_MEDIUM_PPR_DISCARD; \
b01c8b54
PM		 377 SET_SCRATCH0(r13); /* save r13 */ \
378 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common, \
379 EXC_HV, KVMTEST, vec)
f9ff0f30 380
1707dd16
PM		 381/* Version of above for when we have to branch out-of-line */
382#define STD_EXCEPTION_HV_OOL(vec, label) \
383 .globl label##_hv; \
384label##_hv: \
385 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST, vec); \
386 EXCEPTION_PROLOG_PSERIES_1(label##_common, EXC_HV)
387
4700dfaf
MN		 388#define STD_RELON_EXCEPTION_PSERIES(loc, vec, label) \
389 . = loc; \
390 .globl label##_relon_pSeries; \
391label##_relon_pSeries: \
44e9309f 392 HMT_MEDIUM_PPR_DISCARD; \
4700dfaf
MN		 393 /* No guest interrupts come through here */ \
394 SET_SCRATCH0(r13); /* save r13 */ \
395 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label##_common, \
c9f69518 396 EXC_STD, NOTEST, vec)
4700dfaf 397
1707dd16
PM		 398#define STD_RELON_EXCEPTION_PSERIES_OOL(vec, label) \
399 .globl label##_relon_pSeries; \
400label##_relon_pSeries: \
c9f69518 401 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, vec); \
1707dd16
PM		 402 EXCEPTION_RELON_PROLOG_PSERIES_1(label##_common, EXC_STD)
403
4700dfaf
MN		 404#define STD_RELON_EXCEPTION_HV(loc, vec, label) \
405 . = loc; \
406 .globl label##_relon_hv; \
407label##_relon_hv: \
44e9309f 408 HMT_MEDIUM_PPR_DISCARD; \
4700dfaf
MN		 409 /* No guest interrupts come through here */ \
410 SET_SCRATCH0(r13); /* save r13 */ \
411 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label##_common, \
c9f69518 412 EXC_HV, NOTEST, vec)
4700dfaf 413
1707dd16
PM		 414#define STD_RELON_EXCEPTION_HV_OOL(vec, label) \
415 .globl label##_relon_hv; \
416label##_relon_hv: \
c9f69518 417 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, vec); \
1707dd16
PM		 418 EXCEPTION_RELON_PROLOG_PSERIES_1(label##_common, EXC_HV)
419
7230c564
BH		 420/* This associate vector numbers with bits in paca->irq_happened */
421#define SOFTEN_VALUE_0x500 PACA_IRQ_EE
422#define SOFTEN_VALUE_0x502 PACA_IRQ_EE
423#define SOFTEN_VALUE_0x900 PACA_IRQ_DEC
424#define SOFTEN_VALUE_0x982 PACA_IRQ_DEC
1dbdafec 425#define SOFTEN_VALUE_0xa00 PACA_IRQ_DBELL
655bb3f4
IM		 426#define SOFTEN_VALUE_0xe80 PACA_IRQ_DBELL
427#define SOFTEN_VALUE_0xe82 PACA_IRQ_DBELL
7230c564
BH		 428
429#define __SOFTEN_TEST(h, vec) \
f9ff0f30 430 lbz r10,PACASOFTIRQEN(r13); \
f9ff0f30 431 cmpwi r10,0; \
7230c564 432 li r10,SOFTEN_VALUE_##vec; \
b01c8b54 433 beq masked_##h##interrupt
7230c564 434#define _SOFTEN_TEST(h, vec) __SOFTEN_TEST(h, vec)
b01c8b54 435
de56a948
PM		 436#define SOFTEN_TEST_PR(vec) \
437 KVMTEST_PR(vec); \
7230c564 438 _SOFTEN_TEST(EXC_STD, vec)
b01c8b54
PM		 439
440#define SOFTEN_TEST_HV(vec) \
441 KVMTEST(vec); \
7230c564 442 _SOFTEN_TEST(EXC_HV, vec)
b01c8b54 443
9e368f29
PM		 444#define SOFTEN_TEST_HV_201(vec) \
445 KVMTEST(vec); \
7230c564 446 _SOFTEN_TEST(EXC_STD, vec)
9e368f29 447
4700dfaf
MN		 448#define SOFTEN_NOTEST_PR(vec) _SOFTEN_TEST(EXC_STD, vec)
449#define SOFTEN_NOTEST_HV(vec) _SOFTEN_TEST(EXC_HV, vec)
450
b01c8b54 451#define __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) \
b01c8b54 452 SET_SCRATCH0(r13); /* save r13 */ \
1707dd16
PM		 453 EXCEPTION_PROLOG_0(PACA_EXGEN); \
454 __EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec); \
b01c8b54 455 EXCEPTION_PROLOG_PSERIES_1(label##_common, h);
1707dd16 456
b01c8b54
PM		 457#define _MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) \
458 __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra)
b3e6b5df
BH		 459
460#define MASKABLE_EXCEPTION_PSERIES(loc, vec, label) \
461 . = loc; \
462 .globl label##_pSeries; \
463label##_pSeries: \
a485c709 464 HMT_MEDIUM_PPR_DISCARD; \
b01c8b54 465 _MASKABLE_EXCEPTION_PSERIES(vec, label, \
de56a948 466 EXC_STD, SOFTEN_TEST_PR)
b3e6b5df
BH		 467
468#define MASKABLE_EXCEPTION_HV(loc, vec, label) \
469 . = loc; \
470 .globl label##_hv; \
471label##_hv: \
b01c8b54
PM		 472 _MASKABLE_EXCEPTION_PSERIES(vec, label, \
473 EXC_HV, SOFTEN_TEST_HV)
f9ff0f30 474
1707dd16
PM		 475#define MASKABLE_EXCEPTION_HV_OOL(vec, label) \
476 .globl label##_hv; \
477label##_hv: \
478 EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec); \
479 EXCEPTION_PROLOG_PSERIES_1(label##_common, EXC_HV);
480
4700dfaf 481#define __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \
44e9309f 482 HMT_MEDIUM_PPR_DISCARD; \
4700dfaf 483 SET_SCRATCH0(r13); /* save r13 */ \
1707dd16 484 EXCEPTION_PROLOG_0(PACA_EXGEN); \
4700dfaf
MN		 485 __EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec); \
486 EXCEPTION_RELON_PROLOG_PSERIES_1(label##_common, h);
487#define _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \
488 __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra)
489
490#define MASKABLE_RELON_EXCEPTION_PSERIES(loc, vec, label) \
491 . = loc; \
492 .globl label##_relon_pSeries; \
493label##_relon_pSeries: \
494 _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \
495 EXC_STD, SOFTEN_NOTEST_PR)
496
497#define MASKABLE_RELON_EXCEPTION_HV(loc, vec, label) \
498 . = loc; \
499 .globl label##_relon_hv; \
500label##_relon_hv: \
501 _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \
502 EXC_HV, SOFTEN_NOTEST_HV)
503
1707dd16
PM		 504#define MASKABLE_RELON_EXCEPTION_HV_OOL(vec, label) \
505 .globl label##_relon_hv; \
506label##_relon_hv: \
507 EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_NOTEST_HV, vec); \
508 EXCEPTION_PROLOG_PSERIES_1(label##_common, EXC_HV);
509
1b701179
BH		 510/*
511 * Our exception common code can be passed various "additions"
512 * to specify the behaviour of interrupts, whether to kick the
513 * runlatch, etc...
514 */
515
516/* Exception addition: Hard disable interrupts */
de021bb7 517#define DISABLE_INTS RECONCILE_IRQ_STATE(r10,r11)
f9ff0f30 518
fe1952fc
BH		 519#define ADD_NVGPRS \
520 bl .save_nvgprs
521
522#define RUNLATCH_ON \
523BEGIN_FTR_SECTION \
9778b696 524 CURRENT_THREAD_INFO(r3, r1); \
fe1952fc
BH		 525 ld r4,TI_LOCAL_FLAGS(r3); \
526 andi. r0,r4,_TLF_RUNLATCH; \
527 beql ppc64_runlatch_on_trampoline; \
528END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
529
530#define EXCEPTION_COMMON(trap, label, hdlr, ret, additions) \
531 .align 7; \
532 .globl label##_common; \
533label##_common: \
534 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
535 additions; \
536 addi r3,r1,STACK_FRAME_OVERHEAD; \
537 bl hdlr; \
538 b ret
539
540#define STD_EXCEPTION_COMMON(trap, label, hdlr) \
541 EXCEPTION_COMMON(trap, label, hdlr, ret_from_except, \
542 ADD_NVGPRS;DISABLE_INTS)
f9ff0f30
SR		 543
544/*
545 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur
7450f6f0
BH		 546 * in the idle task and therefore need the special idle handling
547 * (finish nap and runlatch)
f9ff0f30 548 */
fe1952fc
BH		 549#define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr) \
550 EXCEPTION_COMMON(trap, label, hdlr, ret_from_except_lite, \
0e37739b 551 FINISH_NAP;DISABLE_INTS;RUNLATCH_ON)
f9ff0f30
SR		 552
553/*
554 * When the idle code in power4_idle puts the CPU into NAP mode,
555 * it has to do so in a loop, and relies on the external interrupt
556 * and decrementer interrupt entry code to get it out of the loop.
557 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
558 * to signal that it is in the loop and needs help to get out.
559 */
560#ifdef CONFIG_PPC_970_NAP
561#define FINISH_NAP \
562BEGIN_FTR_SECTION \
9778b696 563 CURRENT_THREAD_INFO(r11, r1); \
f9ff0f30
SR		 564 ld r9,TI_LOCAL_FLAGS(r11); \
565 andi. r10,r9,_TLF_NAPPING; \
566 bnel power4_fixup_nap; \
567END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
568#else
569#define FINISH_NAP
570#endif
571
572#endif /* _ASM_POWERPC_EXCEPTION_H */
Linux kernel - Deliverables
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