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f9ff0f30 SR |
1 | #ifndef _ASM_POWERPC_EXCEPTION_H |
2 | #define _ASM_POWERPC_EXCEPTION_H | |
3 | /* | |
4 | * Extracted from head_64.S | |
5 | * | |
6 | * PowerPC version | |
7 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
8 | * | |
9 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP | |
10 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> | |
11 | * Adapted for Power Macintosh by Paul Mackerras. | |
12 | * Low-level exception handlers and MMU support | |
13 | * rewritten by Paul Mackerras. | |
14 | * Copyright (C) 1996 Paul Mackerras. | |
15 | * | |
16 | * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and | |
17 | * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com | |
18 | * | |
19 | * This file contains the low-level support and setup for the | |
20 | * PowerPC-64 platform, including trap and interrupt dispatch. | |
21 | * | |
22 | * This program is free software; you can redistribute it and/or | |
23 | * modify it under the terms of the GNU General Public License | |
24 | * as published by the Free Software Foundation; either version | |
25 | * 2 of the License, or (at your option) any later version. | |
26 | */ | |
27 | /* | |
28 | * The following macros define the code that appears as | |
29 | * the prologue to each of the exception handlers. They | |
30 | * are split into two parts to allow a single kernel binary | |
31 | * to be used for pSeries and iSeries. | |
32 | * | |
33 | * We make as much of the exception code common between native | |
34 | * exception handlers (including pSeries LPAR) and iSeries LPAR | |
35 | * implementations as possible. | |
36 | */ | |
37 | ||
38 | #define EX_R9 0 | |
39 | #define EX_R10 8 | |
40 | #define EX_R11 16 | |
41 | #define EX_R12 24 | |
42 | #define EX_R13 32 | |
43 | #define EX_SRR0 40 | |
44 | #define EX_DAR 48 | |
45 | #define EX_DSISR 56 | |
46 | #define EX_CCR 60 | |
47 | #define EX_R3 64 | |
48 | #define EX_LR 72 | |
48404f2e | 49 | #define EX_CFAR 80 |
a09688cd | 50 | #define EX_PPR 88 /* SMT thread status register (priority) */ |
bc2e6c6a | 51 | #define EX_CTR 96 |
f9ff0f30 | 52 | |
4700dfaf | 53 | #ifdef CONFIG_RELOCATABLE |
1707dd16 | 54 | #define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ |
4700dfaf MN |
55 | ld r12,PACAKBASE(r13); /* get high part of &label */ \ |
56 | mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ | |
57 | LOAD_HANDLER(r12,label); \ | |
bc2e6c6a | 58 | mtctr r12; \ |
4700dfaf MN |
59 | mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ |
60 | li r10,MSR_RI; \ | |
61 | mtmsrd r10,1; /* Set RI (EE=0) */ \ | |
bc2e6c6a | 62 | bctr; |
4700dfaf MN |
63 | #else |
64 | /* If not relocatable, we can jump directly -- and save messing with LR */ | |
1707dd16 | 65 | #define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ |
4700dfaf MN |
66 | mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ |
67 | mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ | |
68 | li r10,MSR_RI; \ | |
69 | mtmsrd r10,1; /* Set RI (EE=0) */ \ | |
70 | b label; | |
71 | #endif | |
1707dd16 PM |
72 | #define EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ |
73 | __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ | |
4700dfaf MN |
74 | |
75 | /* | |
76 | * As EXCEPTION_PROLOG_PSERIES(), except we've already got relocation on | |
77 | * so no need to rfid. Save lr in case we're CONFIG_RELOCATABLE, in which | |
78 | * case EXCEPTION_RELON_PROLOG_PSERIES_1 will be using lr. | |
79 | */ | |
80 | #define EXCEPTION_RELON_PROLOG_PSERIES(area, label, h, extra, vec) \ | |
1707dd16 | 81 | EXCEPTION_PROLOG_0(area); \ |
4700dfaf MN |
82 | EXCEPTION_PROLOG_1(area, extra, vec); \ |
83 | EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) | |
84 | ||
f9ff0f30 SR |
85 | /* |
86 | * We're short on space and time in the exception prolog, so we can't | |
87 | * use the normal SET_REG_IMMEDIATE macro. Normally we just need the | |
88 | * low halfword of the address, but for Kdump we need the whole low | |
89 | * word. | |
90 | */ | |
f9ff0f30 | 91 | #define LOAD_HANDLER(reg, label) \ |
61e2390e MN |
92 | /* Handlers must be within 64K of kbase, which must be 64k aligned */ \ |
93 | ori reg,reg,(label)-_stext; /* virt addr of handler ... */ | |
f9ff0f30 | 94 | |
a5d4f3ad BH |
95 | /* Exception register prefixes */ |
96 | #define EXC_HV H | |
97 | #define EXC_STD | |
98 | ||
4700dfaf MN |
99 | #if defined(CONFIG_RELOCATABLE) |
100 | /* | |
bc2e6c6a MN |
101 | * If we support interrupts with relocation on AND we're a relocatable kernel, |
102 | * we need to use CTR to get to the 2nd level handler. So, save/restore it | |
103 | * when required. | |
4700dfaf | 104 | */ |
bc2e6c6a MN |
105 | #define SAVE_CTR(reg, area) mfctr reg ; std reg,area+EX_CTR(r13) |
106 | #define GET_CTR(reg, area) ld reg,area+EX_CTR(r13) | |
107 | #define RESTORE_CTR(reg, area) ld reg,area+EX_CTR(r13) ; mtctr reg | |
4700dfaf | 108 | #else |
bc2e6c6a MN |
109 | /* ...else CTR is unused and in register. */ |
110 | #define SAVE_CTR(reg, area) | |
111 | #define GET_CTR(reg, area) mfctr reg | |
112 | #define RESTORE_CTR(reg, area) | |
4700dfaf MN |
113 | #endif |
114 | ||
13e7a8e8 HM |
115 | /* |
116 | * PPR save/restore macros used in exceptions_64s.S | |
117 | * Used for P7 or later processors | |
118 | */ | |
119 | #define SAVE_PPR(area, ra, rb) \ | |
120 | BEGIN_FTR_SECTION_NESTED(940) \ | |
121 | ld ra,PACACURRENT(r13); \ | |
122 | ld rb,area+EX_PPR(r13); /* Read PPR from paca */ \ | |
123 | std rb,TASKTHREADPPR(ra); \ | |
124 | END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940) | |
125 | ||
126 | #define RESTORE_PPR_PACA(area, ra) \ | |
127 | BEGIN_FTR_SECTION_NESTED(941) \ | |
128 | ld ra,area+EX_PPR(r13); \ | |
129 | mtspr SPRN_PPR,ra; \ | |
130 | END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941) | |
131 | ||
13e7a8e8 | 132 | /* |
1707dd16 | 133 | * Get an SPR into a register if the CPU has the given feature |
13e7a8e8 | 134 | */ |
1707dd16 | 135 | #define OPT_GET_SPR(ra, spr, ftr) \ |
13e7a8e8 | 136 | BEGIN_FTR_SECTION_NESTED(943) \ |
1707dd16 PM |
137 | mfspr ra,spr; \ |
138 | END_FTR_SECTION_NESTED(ftr,ftr,943) | |
13e7a8e8 | 139 | |
d410ae21 MS |
140 | /* |
141 | * Set an SPR from a register if the CPU has the given feature | |
142 | */ | |
143 | #define OPT_SET_SPR(ra, spr, ftr) \ | |
144 | BEGIN_FTR_SECTION_NESTED(943) \ | |
145 | mtspr spr,ra; \ | |
146 | END_FTR_SECTION_NESTED(ftr,ftr,943) | |
147 | ||
1707dd16 PM |
148 | /* |
149 | * Save a register to the PACA if the CPU has the given feature | |
150 | */ | |
151 | #define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \ | |
152 | BEGIN_FTR_SECTION_NESTED(943) \ | |
153 | std ra,offset(r13); \ | |
154 | END_FTR_SECTION_NESTED(ftr,ftr,943) | |
155 | ||
156 | #define EXCEPTION_PROLOG_0(area) \ | |
2dd60d79 | 157 | GET_PACA(r13); \ |
44e9309f | 158 | std r9,area+EX_R9(r13); /* save r9 */ \ |
1707dd16 PM |
159 | OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); \ |
160 | HMT_MEDIUM; \ | |
44e9309f | 161 | std r10,area+EX_R10(r13); /* save r10 - r12 */ \ |
1707dd16 PM |
162 | OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR) |
163 | ||
164 | #define __EXCEPTION_PROLOG_1(area, extra, vec) \ | |
165 | OPT_SAVE_REG_TO_PACA(area+EX_PPR, r9, CPU_FTR_HAS_PPR); \ | |
166 | OPT_SAVE_REG_TO_PACA(area+EX_CFAR, r10, CPU_FTR_CFAR); \ | |
bc2e6c6a | 167 | SAVE_CTR(r10, area); \ |
b01c8b54 PM |
168 | mfcr r9; \ |
169 | extra(vec); \ | |
170 | std r11,area+EX_R11(r13); \ | |
171 | std r12,area+EX_R12(r13); \ | |
172 | GET_SCRATCH0(r10); \ | |
173 | std r10,area+EX_R13(r13) | |
174 | #define EXCEPTION_PROLOG_1(area, extra, vec) \ | |
175 | __EXCEPTION_PROLOG_1(area, extra, vec) | |
7180e3e6 | 176 | |
a5d4f3ad | 177 | #define __EXCEPTION_PROLOG_PSERIES_1(label, h) \ |
1f6a93e4 PM |
178 | ld r12,PACAKBASE(r13); /* get high part of &label */ \ |
179 | ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ | |
a5d4f3ad | 180 | mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ |
f9ff0f30 | 181 | LOAD_HANDLER(r12,label) \ |
a5d4f3ad BH |
182 | mtspr SPRN_##h##SRR0,r12; \ |
183 | mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ | |
184 | mtspr SPRN_##h##SRR1,r10; \ | |
185 | h##rfid; \ | |
f9ff0f30 | 186 | b . /* prevent speculative execution */ |
b01c8b54 | 187 | #define EXCEPTION_PROLOG_PSERIES_1(label, h) \ |
a5d4f3ad | 188 | __EXCEPTION_PROLOG_PSERIES_1(label, h) |
f9ff0f30 | 189 | |
b01c8b54 | 190 | #define EXCEPTION_PROLOG_PSERIES(area, label, h, extra, vec) \ |
1707dd16 | 191 | EXCEPTION_PROLOG_0(area); \ |
b01c8b54 | 192 | EXCEPTION_PROLOG_1(area, extra, vec); \ |
a5d4f3ad | 193 | EXCEPTION_PROLOG_PSERIES_1(label, h); |
c5a8c0c9 | 194 | |
b01c8b54 | 195 | #define __KVMTEST(n) \ |
3c42bf8a | 196 | lbz r10,HSTATE_IN_GUEST(r13); \ |
b01c8b54 PM |
197 | cmpwi r10,0; \ |
198 | bne do_kvm_##n | |
199 | ||
dd96b2c2 AK |
200 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
201 | /* | |
202 | * If hv is possible, interrupts come into to the hv version | |
203 | * of the kvmppc_interrupt code, which then jumps to the PR handler, | |
204 | * kvmppc_interrupt_pr, if the guest is a PR guest. | |
205 | */ | |
206 | #define kvmppc_interrupt kvmppc_interrupt_hv | |
207 | #else | |
208 | #define kvmppc_interrupt kvmppc_interrupt_pr | |
209 | #endif | |
210 | ||
b01c8b54 PM |
211 | #define __KVM_HANDLER(area, h, n) \ |
212 | do_kvm_##n: \ | |
0acb9111 PM |
213 | BEGIN_FTR_SECTION_NESTED(947) \ |
214 | ld r10,area+EX_CFAR(r13); \ | |
215 | std r10,HSTATE_CFAR(r13); \ | |
216 | END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947); \ | |
4b8473c9 PM |
217 | BEGIN_FTR_SECTION_NESTED(948) \ |
218 | ld r10,area+EX_PPR(r13); \ | |
219 | std r10,HSTATE_PPR(r13); \ | |
220 | END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \ | |
b01c8b54 | 221 | ld r10,area+EX_R10(r13); \ |
0acb9111 | 222 | stw r9,HSTATE_SCRATCH1(r13); \ |
b01c8b54 | 223 | ld r9,area+EX_R9(r13); \ |
0acb9111 | 224 | std r12,HSTATE_SCRATCH0(r13); \ |
b01c8b54 PM |
225 | li r12,n; \ |
226 | b kvmppc_interrupt | |
227 | ||
228 | #define __KVM_HANDLER_SKIP(area, h, n) \ | |
229 | do_kvm_##n: \ | |
230 | cmpwi r10,KVM_GUEST_MODE_SKIP; \ | |
231 | ld r10,area+EX_R10(r13); \ | |
232 | beq 89f; \ | |
3c42bf8a | 233 | stw r9,HSTATE_SCRATCH1(r13); \ |
4b8473c9 PM |
234 | BEGIN_FTR_SECTION_NESTED(948) \ |
235 | ld r9,area+EX_PPR(r13); \ | |
236 | std r9,HSTATE_PPR(r13); \ | |
237 | END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \ | |
b01c8b54 | 238 | ld r9,area+EX_R9(r13); \ |
3c42bf8a | 239 | std r12,HSTATE_SCRATCH0(r13); \ |
b01c8b54 PM |
240 | li r12,n; \ |
241 | b kvmppc_interrupt; \ | |
242 | 89: mtocrf 0x80,r9; \ | |
243 | ld r9,area+EX_R9(r13); \ | |
244 | b kvmppc_skip_##h##interrupt | |
245 | ||
246 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER | |
247 | #define KVMTEST(n) __KVMTEST(n) | |
248 | #define KVM_HANDLER(area, h, n) __KVM_HANDLER(area, h, n) | |
249 | #define KVM_HANDLER_SKIP(area, h, n) __KVM_HANDLER_SKIP(area, h, n) | |
250 | ||
251 | #else | |
252 | #define KVMTEST(n) | |
253 | #define KVM_HANDLER(area, h, n) | |
254 | #define KVM_HANDLER_SKIP(area, h, n) | |
255 | #endif | |
256 | ||
257 | #define NOTEST(n) | |
258 | ||
f9ff0f30 SR |
259 | /* |
260 | * The common exception prolog is used for all except a few exceptions | |
261 | * such as a segment miss on a kernel address. We have to be prepared | |
262 | * to take another exception from the point where we first touch the | |
263 | * kernel stack onwards. | |
264 | * | |
265 | * On entry r13 points to the paca, r9-r13 are saved in the paca, | |
266 | * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and | |
267 | * SRR1, and relocation is on. | |
268 | */ | |
269 | #define EXCEPTION_PROLOG_COMMON(n, area) \ | |
270 | andi. r10,r12,MSR_PR; /* See if coming from user */ \ | |
271 | mr r10,r1; /* Save r1 */ \ | |
272 | subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ | |
273 | beq- 1f; \ | |
274 | ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ | |
90ff5d68 | 275 | 1: cmpdi cr1,r1,-INT_FRAME_SIZE; /* check if r1 is in userspace */ \ |
1977b502 PM |
276 | blt+ cr1,3f; /* abort if it is */ \ |
277 | li r1,(n); /* will be reloaded later */ \ | |
f9ff0f30 | 278 | sth r1,PACA_TRAP_SAVE(r13); \ |
1977b502 PM |
279 | std r3,area+EX_R3(r13); \ |
280 | addi r3,r13,area; /* r3 -> where regs are saved*/ \ | |
bc2e6c6a | 281 | RESTORE_CTR(r1, area); \ |
f9ff0f30 SR |
282 | b bad_stack; \ |
283 | 3: std r9,_CCR(r1); /* save CR in stackframe */ \ | |
284 | std r11,_NIP(r1); /* save SRR0 in stackframe */ \ | |
285 | std r12,_MSR(r1); /* save SRR1 in stackframe */ \ | |
286 | std r10,0(r1); /* make stack chain pointer */ \ | |
287 | std r0,GPR0(r1); /* save r0 in stackframe */ \ | |
288 | std r10,GPR1(r1); /* save r1 in stackframe */ \ | |
5d75b264 | 289 | beq 4f; /* if from kernel mode */ \ |
c223c903 | 290 | ACCOUNT_CPU_USER_ENTRY(r13, r9, r10); \ |
44e9309f | 291 | SAVE_PPR(area, r9, r10); \ |
b14a7253 MS |
292 | 4: EXCEPTION_PROLOG_COMMON_2(area) \ |
293 | EXCEPTION_PROLOG_COMMON_3(n) \ | |
294 | ACCOUNT_STOLEN_TIME | |
295 | ||
296 | /* Save original regs values from save area to stack frame. */ | |
297 | #define EXCEPTION_PROLOG_COMMON_2(area) \ | |
f9ff0f30 SR |
298 | ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ |
299 | ld r10,area+EX_R10(r13); \ | |
300 | std r9,GPR9(r1); \ | |
301 | std r10,GPR10(r1); \ | |
302 | ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ | |
303 | ld r10,area+EX_R12(r13); \ | |
304 | ld r11,area+EX_R13(r13); \ | |
305 | std r9,GPR11(r1); \ | |
306 | std r10,GPR12(r1); \ | |
307 | std r11,GPR13(r1); \ | |
48404f2e PM |
308 | BEGIN_FTR_SECTION_NESTED(66); \ |
309 | ld r10,area+EX_CFAR(r13); \ | |
310 | std r10,ORIG_GPR3(r1); \ | |
311 | END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \ | |
b14a7253 MS |
312 | GET_CTR(r10, area); \ |
313 | std r10,_CTR(r1); | |
314 | ||
315 | #define EXCEPTION_PROLOG_COMMON_3(n) \ | |
316 | std r2,GPR2(r1); /* save r2 in stackframe */ \ | |
317 | SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ | |
318 | SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ | |
bc2e6c6a | 319 | mflr r9; /* Get LR, later save to stack */ \ |
f9ff0f30 | 320 | ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ |
f9ff0f30 | 321 | std r9,_LINK(r1); \ |
f9ff0f30 SR |
322 | lbz r10,PACASOFTIRQEN(r13); \ |
323 | mfspr r11,SPRN_XER; /* save XER in stackframe */ \ | |
324 | std r10,SOFTE(r1); \ | |
325 | std r11,_XER(r1); \ | |
326 | li r9,(n)+1; \ | |
327 | std r9,_TRAP(r1); /* set trap number */ \ | |
328 | li r10,0; \ | |
329 | ld r11,exception_marker@toc(r2); \ | |
330 | std r10,RESULT(r1); /* clear regs->result */ \ | |
b14a7253 | 331 | std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ |
f9ff0f30 SR |
332 | |
333 | /* | |
334 | * Exception vectors. | |
335 | */ | |
2613265c ME |
336 | #define STD_EXCEPTION_PSERIES(vec, label) \ |
337 | . = vec; \ | |
f9ff0f30 SR |
338 | .globl label##_pSeries; \ |
339 | label##_pSeries: \ | |
673b189a | 340 | SET_SCRATCH0(r13); /* save r13 */ \ |
b01c8b54 | 341 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common, \ |
31a40e2b | 342 | EXC_STD, KVMTEST, vec) |
f9ff0f30 | 343 | |
1707dd16 PM |
344 | /* Version of above for when we have to branch out-of-line */ |
345 | #define STD_EXCEPTION_PSERIES_OOL(vec, label) \ | |
346 | .globl label##_pSeries; \ | |
347 | label##_pSeries: \ | |
31a40e2b | 348 | EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST, vec); \ |
1707dd16 PM |
349 | EXCEPTION_PROLOG_PSERIES_1(label##_common, EXC_STD) |
350 | ||
b3e6b5df BH |
351 | #define STD_EXCEPTION_HV(loc, vec, label) \ |
352 | . = loc; \ | |
353 | .globl label##_hv; \ | |
354 | label##_hv: \ | |
b01c8b54 PM |
355 | SET_SCRATCH0(r13); /* save r13 */ \ |
356 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common, \ | |
357 | EXC_HV, KVMTEST, vec) | |
f9ff0f30 | 358 | |
1707dd16 PM |
359 | /* Version of above for when we have to branch out-of-line */ |
360 | #define STD_EXCEPTION_HV_OOL(vec, label) \ | |
361 | .globl label##_hv; \ | |
362 | label##_hv: \ | |
363 | EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST, vec); \ | |
364 | EXCEPTION_PROLOG_PSERIES_1(label##_common, EXC_HV) | |
365 | ||
4700dfaf MN |
366 | #define STD_RELON_EXCEPTION_PSERIES(loc, vec, label) \ |
367 | . = loc; \ | |
368 | .globl label##_relon_pSeries; \ | |
369 | label##_relon_pSeries: \ | |
4700dfaf MN |
370 | /* No guest interrupts come through here */ \ |
371 | SET_SCRATCH0(r13); /* save r13 */ \ | |
372 | EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label##_common, \ | |
c9f69518 | 373 | EXC_STD, NOTEST, vec) |
4700dfaf | 374 | |
1707dd16 PM |
375 | #define STD_RELON_EXCEPTION_PSERIES_OOL(vec, label) \ |
376 | .globl label##_relon_pSeries; \ | |
377 | label##_relon_pSeries: \ | |
c9f69518 | 378 | EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, vec); \ |
1707dd16 PM |
379 | EXCEPTION_RELON_PROLOG_PSERIES_1(label##_common, EXC_STD) |
380 | ||
4700dfaf MN |
381 | #define STD_RELON_EXCEPTION_HV(loc, vec, label) \ |
382 | . = loc; \ | |
383 | .globl label##_relon_hv; \ | |
384 | label##_relon_hv: \ | |
4700dfaf MN |
385 | /* No guest interrupts come through here */ \ |
386 | SET_SCRATCH0(r13); /* save r13 */ \ | |
387 | EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label##_common, \ | |
c9f69518 | 388 | EXC_HV, NOTEST, vec) |
4700dfaf | 389 | |
1707dd16 PM |
390 | #define STD_RELON_EXCEPTION_HV_OOL(vec, label) \ |
391 | .globl label##_relon_hv; \ | |
392 | label##_relon_hv: \ | |
c9f69518 | 393 | EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, vec); \ |
1707dd16 PM |
394 | EXCEPTION_RELON_PROLOG_PSERIES_1(label##_common, EXC_HV) |
395 | ||
7230c564 BH |
396 | /* This associate vector numbers with bits in paca->irq_happened */ |
397 | #define SOFTEN_VALUE_0x500 PACA_IRQ_EE | |
398 | #define SOFTEN_VALUE_0x502 PACA_IRQ_EE | |
399 | #define SOFTEN_VALUE_0x900 PACA_IRQ_DEC | |
400 | #define SOFTEN_VALUE_0x982 PACA_IRQ_DEC | |
1dbdafec | 401 | #define SOFTEN_VALUE_0xa00 PACA_IRQ_DBELL |
655bb3f4 IM |
402 | #define SOFTEN_VALUE_0xe80 PACA_IRQ_DBELL |
403 | #define SOFTEN_VALUE_0xe82 PACA_IRQ_DBELL | |
0869b6fd MS |
404 | #define SOFTEN_VALUE_0xe60 PACA_IRQ_HMI |
405 | #define SOFTEN_VALUE_0xe62 PACA_IRQ_HMI | |
9baaef0a BH |
406 | #define SOFTEN_VALUE_0xea0 PACA_IRQ_EE |
407 | #define SOFTEN_VALUE_0xea2 PACA_IRQ_EE | |
7230c564 BH |
408 | |
409 | #define __SOFTEN_TEST(h, vec) \ | |
f9ff0f30 | 410 | lbz r10,PACASOFTIRQEN(r13); \ |
f9ff0f30 | 411 | cmpwi r10,0; \ |
7230c564 | 412 | li r10,SOFTEN_VALUE_##vec; \ |
b01c8b54 | 413 | beq masked_##h##interrupt |
7230c564 | 414 | #define _SOFTEN_TEST(h, vec) __SOFTEN_TEST(h, vec) |
b01c8b54 | 415 | |
de56a948 | 416 | #define SOFTEN_TEST_PR(vec) \ |
31a40e2b | 417 | KVMTEST(vec); \ |
7230c564 | 418 | _SOFTEN_TEST(EXC_STD, vec) |
b01c8b54 PM |
419 | |
420 | #define SOFTEN_TEST_HV(vec) \ | |
421 | KVMTEST(vec); \ | |
7230c564 | 422 | _SOFTEN_TEST(EXC_HV, vec) |
b01c8b54 | 423 | |
4700dfaf MN |
424 | #define SOFTEN_NOTEST_PR(vec) _SOFTEN_TEST(EXC_STD, vec) |
425 | #define SOFTEN_NOTEST_HV(vec) _SOFTEN_TEST(EXC_HV, vec) | |
426 | ||
b01c8b54 | 427 | #define __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) \ |
b01c8b54 | 428 | SET_SCRATCH0(r13); /* save r13 */ \ |
1707dd16 PM |
429 | EXCEPTION_PROLOG_0(PACA_EXGEN); \ |
430 | __EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec); \ | |
b01c8b54 | 431 | EXCEPTION_PROLOG_PSERIES_1(label##_common, h); |
1707dd16 | 432 | |
b01c8b54 PM |
433 | #define _MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) \ |
434 | __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) | |
b3e6b5df BH |
435 | |
436 | #define MASKABLE_EXCEPTION_PSERIES(loc, vec, label) \ | |
437 | . = loc; \ | |
438 | .globl label##_pSeries; \ | |
439 | label##_pSeries: \ | |
b01c8b54 | 440 | _MASKABLE_EXCEPTION_PSERIES(vec, label, \ |
de56a948 | 441 | EXC_STD, SOFTEN_TEST_PR) |
b3e6b5df BH |
442 | |
443 | #define MASKABLE_EXCEPTION_HV(loc, vec, label) \ | |
444 | . = loc; \ | |
445 | .globl label##_hv; \ | |
446 | label##_hv: \ | |
b01c8b54 PM |
447 | _MASKABLE_EXCEPTION_PSERIES(vec, label, \ |
448 | EXC_HV, SOFTEN_TEST_HV) | |
f9ff0f30 | 449 | |
1707dd16 PM |
450 | #define MASKABLE_EXCEPTION_HV_OOL(vec, label) \ |
451 | .globl label##_hv; \ | |
452 | label##_hv: \ | |
453 | EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec); \ | |
454 | EXCEPTION_PROLOG_PSERIES_1(label##_common, EXC_HV); | |
455 | ||
4700dfaf | 456 | #define __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \ |
4700dfaf | 457 | SET_SCRATCH0(r13); /* save r13 */ \ |
1707dd16 | 458 | EXCEPTION_PROLOG_0(PACA_EXGEN); \ |
4700dfaf MN |
459 | __EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec); \ |
460 | EXCEPTION_RELON_PROLOG_PSERIES_1(label##_common, h); | |
461 | #define _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \ | |
462 | __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) | |
463 | ||
464 | #define MASKABLE_RELON_EXCEPTION_PSERIES(loc, vec, label) \ | |
465 | . = loc; \ | |
466 | .globl label##_relon_pSeries; \ | |
467 | label##_relon_pSeries: \ | |
468 | _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \ | |
469 | EXC_STD, SOFTEN_NOTEST_PR) | |
470 | ||
471 | #define MASKABLE_RELON_EXCEPTION_HV(loc, vec, label) \ | |
472 | . = loc; \ | |
473 | .globl label##_relon_hv; \ | |
474 | label##_relon_hv: \ | |
475 | _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \ | |
476 | EXC_HV, SOFTEN_NOTEST_HV) | |
477 | ||
1707dd16 PM |
478 | #define MASKABLE_RELON_EXCEPTION_HV_OOL(vec, label) \ |
479 | .globl label##_relon_hv; \ | |
480 | label##_relon_hv: \ | |
481 | EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_NOTEST_HV, vec); \ | |
482 | EXCEPTION_PROLOG_PSERIES_1(label##_common, EXC_HV); | |
483 | ||
1b701179 BH |
484 | /* |
485 | * Our exception common code can be passed various "additions" | |
486 | * to specify the behaviour of interrupts, whether to kick the | |
487 | * runlatch, etc... | |
488 | */ | |
489 | ||
9daf112b ME |
490 | /* |
491 | * This addition reconciles our actual IRQ state with the various software | |
492 | * flags that track it. This may call C code. | |
493 | */ | |
494 | #define ADD_RECONCILE RECONCILE_IRQ_STATE(r10,r11) | |
f9ff0f30 | 495 | |
fe1952fc | 496 | #define ADD_NVGPRS \ |
b1576fec | 497 | bl save_nvgprs |
fe1952fc BH |
498 | |
499 | #define RUNLATCH_ON \ | |
500 | BEGIN_FTR_SECTION \ | |
9778b696 | 501 | CURRENT_THREAD_INFO(r3, r1); \ |
fe1952fc BH |
502 | ld r4,TI_LOCAL_FLAGS(r3); \ |
503 | andi. r0,r4,_TLF_RUNLATCH; \ | |
504 | beql ppc64_runlatch_on_trampoline; \ | |
505 | END_FTR_SECTION_IFSET(CPU_FTR_CTRL) | |
506 | ||
507 | #define EXCEPTION_COMMON(trap, label, hdlr, ret, additions) \ | |
508 | .align 7; \ | |
509 | .globl label##_common; \ | |
510 | label##_common: \ | |
511 | EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ | |
a1d711c5 | 512 | /* Volatile regs are potentially clobbered here */ \ |
fe1952fc BH |
513 | additions; \ |
514 | addi r3,r1,STACK_FRAME_OVERHEAD; \ | |
515 | bl hdlr; \ | |
516 | b ret | |
517 | ||
518 | #define STD_EXCEPTION_COMMON(trap, label, hdlr) \ | |
519 | EXCEPTION_COMMON(trap, label, hdlr, ret_from_except, \ | |
9daf112b | 520 | ADD_NVGPRS;ADD_RECONCILE) |
f9ff0f30 SR |
521 | |
522 | /* | |
523 | * Like STD_EXCEPTION_COMMON, but for exceptions that can occur | |
7450f6f0 BH |
524 | * in the idle task and therefore need the special idle handling |
525 | * (finish nap and runlatch) | |
f9ff0f30 | 526 | */ |
fe1952fc BH |
527 | #define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr) \ |
528 | EXCEPTION_COMMON(trap, label, hdlr, ret_from_except_lite, \ | |
9daf112b | 529 | FINISH_NAP;ADD_RECONCILE;RUNLATCH_ON) |
f9ff0f30 SR |
530 | |
531 | /* | |
532 | * When the idle code in power4_idle puts the CPU into NAP mode, | |
533 | * it has to do so in a loop, and relies on the external interrupt | |
534 | * and decrementer interrupt entry code to get it out of the loop. | |
535 | * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags | |
536 | * to signal that it is in the loop and needs help to get out. | |
537 | */ | |
538 | #ifdef CONFIG_PPC_970_NAP | |
539 | #define FINISH_NAP \ | |
540 | BEGIN_FTR_SECTION \ | |
9778b696 | 541 | CURRENT_THREAD_INFO(r11, r1); \ |
f9ff0f30 SR |
542 | ld r9,TI_LOCAL_FLAGS(r11); \ |
543 | andi. r10,r9,_TLF_NAPPING; \ | |
544 | bnel power4_fixup_nap; \ | |
545 | END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) | |
546 | #else | |
547 | #define FINISH_NAP | |
548 | #endif | |
549 | ||
550 | #endif /* _ASM_POWERPC_EXCEPTION_H */ |