[deliverable/linux.git] / arch / powerpc / include / asm / fsl_guts.h

/**
 * Freecale 85xx and 86xx Global Utilties register set
 *
 * Authors: Jeff Brown
 *          Timur Tabi <timur@freescale.com>
 *
 * Copyright 2004,2007,2012 Freescale Semiconductor, Inc
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#ifndef __ASM_POWERPC_FSL_GUTS_H__
#define __ASM_POWERPC_FSL_GUTS_H__
#ifdef __KERNEL__

/**
 * Global Utility Registers.
 *
 * Not all registers defined in this structure are available on all chips, so
 * you are expected to know whether a given register actually exists on your
 * chip before you access it.
 *
 * Also, some registers are similar on different chips but have slightly
 * different names.  In these cases, one name is chosen to avoid extraneous
 * #ifdefs.
 */
struct ccsr_guts {
	__be32	porpllsr;	/* 0x.0000 - POR PLL Ratio Status Register */
	__be32	porbmsr;	/* 0x.0004 - POR Boot Mode Status Register */
	__be32	porimpscr;	/* 0x.0008 - POR I/O Impedance Status and Control Register */
	__be32	pordevsr;	/* 0x.000c - POR I/O Device Status Register */
	__be32	pordbgmsr;	/* 0x.0010 - POR Debug Mode Status Register */
	__be32	pordevsr2;	/* 0x.0014 - POR device status register 2 */
	u8	res018[0x20 - 0x18];
	__be32	porcir;		/* 0x.0020 - POR Configuration Information Register */
	u8	res024[0x30 - 0x24];
	__be32	gpiocr;		/* 0x.0030 - GPIO Control Register */
	u8	res034[0x40 - 0x34];
	__be32	gpoutdr;	/* 0x.0040 - General-Purpose Output Data Register */
	u8	res044[0x50 - 0x44];
	__be32	gpindr;		/* 0x.0050 - General-Purpose Input Data Register */
	u8	res054[0x60 - 0x54];
	__be32	pmuxcr;		/* 0x.0060 - Alternate Function Signal Multiplex Control */
        __be32  pmuxcr2;	/* 0x.0064 - Alternate function signal multiplex control 2 */
        __be32  dmuxcr;		/* 0x.0068 - DMA Mux Control Register */
        u8	res06c[0x70 - 0x6c];
	__be32	devdisr;	/* 0x.0070 - Device Disable Control */
#define CCSR_GUTS_DEVDISR_TB1	0x00001000
#define CCSR_GUTS_DEVDISR_TB0	0x00004000
	__be32	devdisr2;	/* 0x.0074 - Device Disable Control 2 */
	u8	res078[0x7c - 0x78];
	__be32  pmjcr;		/* 0x.007c - 4 Power Management Jog Control Register */
	__be32	powmgtcsr;	/* 0x.0080 - Power Management Status and Control Register */
	__be32  pmrccr;		/* 0x.0084 - Power Management Reset Counter Configuration Register */
	__be32  pmpdccr;	/* 0x.0088 - Power Management Power Down Counter Configuration Register */
	__be32  pmcdr;		/* 0x.008c - 4Power management clock disable register */
	__be32	mcpsumr;	/* 0x.0090 - Machine Check Summary Register */
	__be32	rstrscr;	/* 0x.0094 - Reset Request Status and Control Register */
	__be32  ectrstcr;	/* 0x.0098 - Exception reset control register */
	__be32  autorstsr;	/* 0x.009c - Automatic reset status register */
	__be32	pvr;		/* 0x.00a0 - Processor Version Register */
	__be32	svr;		/* 0x.00a4 - System Version Register */
	u8	res0a8[0xb0 - 0xa8];
	__be32	rstcr;		/* 0x.00b0 - Reset Control Register */
	u8	res0b4[0xc0 - 0xb4];
	__be32  iovselsr;	/* 0x.00c0 - I/O voltage select status register
					     Called 'elbcvselcr' on 86xx SOCs */
	u8	res0c4[0x224 - 0xc4];
	__be32  iodelay1;	/* 0x.0224 - IO delay control register 1 */
	__be32  iodelay2;	/* 0x.0228 - IO delay control register 2 */
	u8	res22c[0x800 - 0x22c];
	__be32	clkdvdr;	/* 0x.0800 - Clock Divide Register */
	u8	res804[0x900 - 0x804];
	__be32	ircr;		/* 0x.0900 - Infrared Control Register */
	u8	res904[0x908 - 0x904];
	__be32	dmacr;		/* 0x.0908 - DMA Control Register */
	u8	res90c[0x914 - 0x90c];
	__be32	elbccr;		/* 0x.0914 - eLBC Control Register */
	u8	res918[0xb20 - 0x918];
	__be32	ddr1clkdr;	/* 0x.0b20 - DDR1 Clock Disable Register */
	__be32	ddr2clkdr;	/* 0x.0b24 - DDR2 Clock Disable Register */
	__be32	ddrclkdr;	/* 0x.0b28 - DDR Clock Disable Register */
	u8	resb2c[0xe00 - 0xb2c];
	__be32	clkocr;		/* 0x.0e00 - Clock Out Select Register */
	u8	rese04[0xe10 - 0xe04];
	__be32	ddrdllcr;	/* 0x.0e10 - DDR DLL Control Register */
	u8	rese14[0xe20 - 0xe14];
	__be32	lbcdllcr;	/* 0x.0e20 - LBC DLL Control Register */
	__be32  cpfor;		/* 0x.0e24 - L2 charge pump fuse override register */
	u8	rese28[0xf04 - 0xe28];
	__be32	srds1cr0;	/* 0x.0f04 - SerDes1 Control Register 0 */
	__be32	srds1cr1;	/* 0x.0f08 - SerDes1 Control Register 0 */
	u8	resf0c[0xf2c - 0xf0c];
	__be32  itcr;		/* 0x.0f2c - Internal transaction control register */
	u8	resf30[0xf40 - 0xf30];
	__be32	srds2cr0;	/* 0x.0f40 - SerDes2 Control Register 0 */
	__be32	srds2cr1;	/* 0x.0f44 - SerDes2 Control Register 0 */
} __attribute__ ((packed));


/* Alternate function signal multiplex control */
#define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))

#ifdef CONFIG_PPC_86xx

#define CCSR_GUTS_DMACR_DEV_SSI	0	/* DMA controller/channel set to SSI */
#define CCSR_GUTS_DMACR_DEV_IR	1	/* DMA controller/channel set to IR */

/*
 * Set the DMACR register in the GUTS
 *
 * The DMACR register determines the source of initiated transfers for each
 * channel on each DMA controller.  Rather than have a bunch of repetitive
 * macros for the bit patterns, we just have a function that calculates
 * them.
 *
 * guts: Pointer to GUTS structure
 * co: The DMA controller (0 or 1)
 * ch: The channel on the DMA controller (0, 1, 2, or 3)
 * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx)
 */
static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
	unsigned int co, unsigned int ch, unsigned int device)
{
	unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));

	clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift);
}

#define CCSR_GUTS_PMUXCR_LDPSEL		0x00010000
#define CCSR_GUTS_PMUXCR_SSI1_MASK	0x0000C000	/* Bitmask for SSI1 */
#define CCSR_GUTS_PMUXCR_SSI1_LA	0x00000000	/* Latched address */
#define CCSR_GUTS_PMUXCR_SSI1_HI	0x00004000	/* High impedance */
#define CCSR_GUTS_PMUXCR_SSI1_SSI	0x00008000	/* Used for SSI1 */
#define CCSR_GUTS_PMUXCR_SSI2_MASK	0x00003000	/* Bitmask for SSI2 */
#define CCSR_GUTS_PMUXCR_SSI2_LA	0x00000000	/* Latched address */
#define CCSR_GUTS_PMUXCR_SSI2_HI	0x00001000	/* High impedance */
#define CCSR_GUTS_PMUXCR_SSI2_SSI	0x00002000	/* Used for SSI2 */
#define CCSR_GUTS_PMUXCR_LA_22_25_LA	0x00000000	/* Latched Address */
#define CCSR_GUTS_PMUXCR_LA_22_25_HI	0x00000400	/* High impedance */
#define CCSR_GUTS_PMUXCR_DBGDRV		0x00000200	/* Signals not driven */
#define CCSR_GUTS_PMUXCR_DMA2_0		0x00000008
#define CCSR_GUTS_PMUXCR_DMA2_3		0x00000004
#define CCSR_GUTS_PMUXCR_DMA1_0		0x00000002
#define CCSR_GUTS_PMUXCR_DMA1_3		0x00000001

/*
 * Set the DMA external control bits in the GUTS
 *
 * The DMA external control bits in the PMUXCR are only meaningful for
 * channels 0 and 3.  Any other channels are ignored.
 *
 * guts: Pointer to GUTS structure
 * co: The DMA controller (0 or 1)
 * ch: The channel on the DMA controller (0, 1, 2, or 3)
 * value: the new value for the bit (0 or 1)
 */
static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
	unsigned int co, unsigned int ch, unsigned int value)
{
	if ((ch == 0) || (ch == 3)) {
		unsigned int shift = 2 * (co + 1) - (ch & 1) - 1;

		clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift);
	}
}

#define CCSR_GUTS_CLKDVDR_PXCKEN	0x80000000
#define CCSR_GUTS_CLKDVDR_SSICKEN	0x20000000
#define CCSR_GUTS_CLKDVDR_PXCKINV	0x10000000
#define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT 25
#define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK	0x06000000
#define CCSR_GUTS_CLKDVDR_PXCKDLY(x) \
	(((x) & 3) << CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT)
#define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT	16
#define CCSR_GUTS_CLKDVDR_PXCLK_MASK	0x001F0000
#define CCSR_GUTS_CLKDVDR_PXCLK(x) (((x) & 31) << CCSR_GUTS_CLKDVDR_PXCLK_SHIFT)
#define CCSR_GUTS_CLKDVDR_SSICLK_MASK	0x000000FF
#define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK)

#endif

#endif
#endif
Commit	Line	Data
82925e76	1	/**
6e6f6622	2	* Freecale 85xx and 86xx Global Utilties register set
6b543404	3	*
82925e76 TT	4	* Authors: Jeff Brown
82925e76 TT	5	* Timur Tabi <timur@freescale.com>
6b543404	6	*
c141b38f	7	* Copyright 2004,2007,2012 Freescale Semiconductor, Inc
6b543404 JL	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms of the GNU General Public License as published by the
	11	* Free Software Foundation; either version 2 of the License, or (at your
	12	* option) any later version.
6b543404 JL	13	*/
6b543404 JL	14
6e6f6622 TT	15	#ifndef __ASM_POWERPC_FSL_GUTS_H__
6e6f6622 TT	16	#define __ASM_POWERPC_FSL_GUTS_H__
6b543404 JL	17	#ifdef __KERNEL__
6b543404 JL	18
6e6f6622 TT	19	/**
	20	* Global Utility Registers.
	21	*
	22	* Not all registers defined in this structure are available on all chips, so
	23	* you are expected to know whether a given register actually exists on your
	24	* chip before you access it.
	25	*
	26	* Also, some registers are similar on different chips but have slightly
	27	* different names. In these cases, one name is chosen to avoid extraneous
	28	* #ifdefs.
	29	*/
9cb6abcb	30	struct ccsr_guts {
82925e76 TT	31	__be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
	32	__be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
	33	__be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */
	34	__be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
	35	__be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
6e6f6622 TT	36	__be32 pordevsr2; /* 0x.0014 - POR device status register 2 */
6e6f6622 TT	37	u8 res018[0x20 - 0x18];
82925e76	38	__be32 porcir; /* 0x.0020 - POR Configuration Information Register */
6e6f6622	39	u8 res024[0x30 - 0x24];
82925e76	40	__be32 gpiocr; /* 0x.0030 - GPIO Control Register */
6e6f6622	41	u8 res034[0x40 - 0x34];
82925e76	42	__be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */
6e6f6622	43	u8 res044[0x50 - 0x44];
82925e76	44	__be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */
6e6f6622	45	u8 res054[0x60 - 0x54];
82925e76	46	__be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */
6e6f6622 TT	47	__be32 pmuxcr2; /* 0x.0064 - Alternate function signal multiplex control 2 */
	48	__be32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
	49	u8 res06c[0x70 - 0x6c];
82925e76	50	__be32 devdisr; /* 0x.0070 - Device Disable Control */
bf345263 ZC	51	#define CCSR_GUTS_DEVDISR_TB1 0x00001000
bf345263 ZC	52	#define CCSR_GUTS_DEVDISR_TB0 0x00004000
090fe850	53	__be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
6e6f6622 TT	54	u8 res078[0x7c - 0x78];
6e6f6622 TT	55	__be32 pmjcr; /* 0x.007c - 4 Power Management Jog Control Register */
82925e76	56	__be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */
6e6f6622 TT	57	__be32 pmrccr; /* 0x.0084 - Power Management Reset Counter Configuration Register */
	58	__be32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter Configuration Register */
	59	__be32 pmcdr; /* 0x.008c - 4Power management clock disable register */
82925e76 TT	60	__be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
82925e76 TT	61	__be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */
6e6f6622 TT	62	__be32 ectrstcr; /* 0x.0098 - Exception reset control register */
6e6f6622 TT	63	__be32 autorstsr; /* 0x.009c - Automatic reset status register */
82925e76 TT	64	__be32 pvr; /* 0x.00a0 - Processor Version Register */
82925e76 TT	65	__be32 svr; /* 0x.00a4 - System Version Register */
6e6f6622	66	u8 res0a8[0xb0 - 0xa8];
82925e76	67	__be32 rstcr; /* 0x.00b0 - Reset Control Register */
6e6f6622	68	u8 res0b4[0xc0 - 0xb4];
9cb6abcb TT	69	__be32 iovselsr; /* 0x.00c0 - I/O voltage select status register
9cb6abcb TT	70	Called 'elbcvselcr' on 86xx SOCs */
6e6f6622 TT	71	u8 res0c4[0x224 - 0xc4];
	72	__be32 iodelay1; /* 0x.0224 - IO delay control register 1 */
	73	__be32 iodelay2; /* 0x.0228 - IO delay control register 2 */
	74	u8 res22c[0x800 - 0x22c];
090fe850	75	__be32 clkdvdr; /* 0x.0800 - Clock Divide Register */
6e6f6622	76	u8 res804[0x900 - 0x804];
090fe850	77	__be32 ircr; /* 0x.0900 - Infrared Control Register */
6e6f6622	78	u8 res904[0x908 - 0x904];
090fe850	79	__be32 dmacr; /* 0x.0908 - DMA Control Register */
6e6f6622	80	u8 res90c[0x914 - 0x90c];
090fe850	81	__be32 elbccr; /* 0x.0914 - eLBC Control Register */
6e6f6622	82	u8 res918[0xb20 - 0x918];
090fe850 TT	83	__be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
	84	__be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
	85	__be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
6e6f6622	86	u8 resb2c[0xe00 - 0xb2c];
82925e76	87	__be32 clkocr; /* 0x.0e00 - Clock Out Select Register */
6e6f6622	88	u8 rese04[0xe10 - 0xe04];
090fe850	89	__be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
6e6f6622	90	u8 rese14[0xe20 - 0xe14];
090fe850	91	__be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
6e6f6622 TT	92	__be32 cpfor; /* 0x.0e24 - L2 charge pump fuse override register */
6e6f6622 TT	93	u8 rese28[0xf04 - 0xe28];
82925e76 TT	94	__be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
82925e76 TT	95	__be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
6e6f6622 TT	96	u8 resf0c[0xf2c - 0xf0c];
	97	__be32 itcr; /* 0x.0f2c - Internal transaction control register */
	98	u8 resf30[0xf40 - 0xf30];
	99	__be32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
	100	__be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
090fe850 TT	101	} __attribute__ ((packed));
090fe850 TT	102
c141b38f ZF	103
	104	/* Alternate function signal multiplex control */
	105	#define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))
	106
6e6f6622 TT	107	#ifdef CONFIG_PPC_86xx
6e6f6622 TT	108
090fe850 TT	109	#define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA controller/channel set to SSI */
	110	#define CCSR_GUTS_DMACR_DEV_IR 1 /* DMA controller/channel set to IR */
	111
	112	/*
	113	* Set the DMACR register in the GUTS
	114	*
	115	* The DMACR register determines the source of initiated transfers for each
	116	* channel on each DMA controller. Rather than have a bunch of repetitive
	117	* macros for the bit patterns, we just have a function that calculates
	118	* them.
	119	*
	120	* guts: Pointer to GUTS structure
c5eeb559	121	* co: The DMA controller (0 or 1)
090fe850 TT	122	* ch: The channel on the DMA controller (0, 1, 2, or 3)
	123	* device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx)
	124	*/
9cb6abcb	125	static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
090fe850 TT	126	unsigned int co, unsigned int ch, unsigned int device)
090fe850 TT	127	{
c5eeb559	128	unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
090fe850 TT	129
	130	clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift);
	131	}
	132
	133	#define CCSR_GUTS_PMUXCR_LDPSEL 0x00010000
	134	#define CCSR_GUTS_PMUXCR_SSI1_MASK 0x0000C000 /* Bitmask for SSI1 */
	135	#define CCSR_GUTS_PMUXCR_SSI1_LA 0x00000000 /* Latched address */
	136	#define CCSR_GUTS_PMUXCR_SSI1_HI 0x00004000 /* High impedance */
	137	#define CCSR_GUTS_PMUXCR_SSI1_SSI 0x00008000 /* Used for SSI1 */
	138	#define CCSR_GUTS_PMUXCR_SSI2_MASK 0x00003000 /* Bitmask for SSI2 */
	139	#define CCSR_GUTS_PMUXCR_SSI2_LA 0x00000000 /* Latched address */
	140	#define CCSR_GUTS_PMUXCR_SSI2_HI 0x00001000 /* High impedance */
	141	#define CCSR_GUTS_PMUXCR_SSI2_SSI 0x00002000 /* Used for SSI2 */
	142	#define CCSR_GUTS_PMUXCR_LA_22_25_LA 0x00000000 /* Latched Address */
	143	#define CCSR_GUTS_PMUXCR_LA_22_25_HI 0x00000400 /* High impedance */
	144	#define CCSR_GUTS_PMUXCR_DBGDRV 0x00000200 /* Signals not driven */
	145	#define CCSR_GUTS_PMUXCR_DMA2_0 0x00000008
	146	#define CCSR_GUTS_PMUXCR_DMA2_3 0x00000004
	147	#define CCSR_GUTS_PMUXCR_DMA1_0 0x00000002
	148	#define CCSR_GUTS_PMUXCR_DMA1_3 0x00000001
	149
c5eeb559 TT	150	/*
	151	* Set the DMA external control bits in the GUTS
	152	*
	153	* The DMA external control bits in the PMUXCR are only meaningful for
	154	* channels 0 and 3. Any other channels are ignored.
	155	*
	156	* guts: Pointer to GUTS structure
	157	* co: The DMA controller (0 or 1)
	158	* ch: The channel on the DMA controller (0, 1, 2, or 3)
	159	* value: the new value for the bit (0 or 1)
	160	*/
9cb6abcb	161	static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
c5eeb559 TT	162	unsigned int co, unsigned int ch, unsigned int value)
	163	{
	164	if ((ch == 0) \|\| (ch == 3)) {
	165	unsigned int shift = 2 * (co + 1) - (ch & 1) - 1;
	166
	167	clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift);
	168	}
	169	}
	170
090fe850 TT	171	#define CCSR_GUTS_CLKDVDR_PXCKEN 0x80000000
	172	#define CCSR_GUTS_CLKDVDR_SSICKEN 0x20000000
	173	#define CCSR_GUTS_CLKDVDR_PXCKINV 0x10000000
	174	#define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT 25
	175	#define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK 0x06000000
	176	#define CCSR_GUTS_CLKDVDR_PXCKDLY(x) \
	177	(((x) & 3) << CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT)
	178	#define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT 16
	179	#define CCSR_GUTS_CLKDVDR_PXCLK_MASK 0x001F0000
	180	#define CCSR_GUTS_CLKDVDR_PXCLK(x) (((x) & 31) << CCSR_GUTS_CLKDVDR_PXCLK_SHIFT)
	181	#define CCSR_GUTS_CLKDVDR_SSICLK_MASK 0x000000FF
	182	#define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK)
6b543404	183
6e6f6622 TT	184	#endif
	185
	186	#endif
	187	#endif