[deliverable/linux.git] / arch / powerpc / include / asm / futex.h

#ifndef _ASM_POWERPC_FUTEX_H
#define _ASM_POWERPC_FUTEX_H

#ifdef __KERNEL__

#include <linux/futex.h>
#include <linux/uaccess.h>
#include <asm/errno.h>
#include <asm/synch.h>
#include <asm/asm-compat.h>

#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
  __asm__ __volatile ( \
	PPC_ATOMIC_ENTRY_BARRIER \
"1:	lwarx	%0,0,%2\n" \
	insn \
	PPC405_ERR77(0, %2) \
"2:	stwcx.	%1,0,%2\n" \
	"bne-	1b\n" \
	PPC_ATOMIC_EXIT_BARRIER \
	"li	%1,0\n" \
"3:	.section .fixup,\"ax\"\n" \
"4:	li	%1,%3\n" \
	"b	3b\n" \
	".previous\n" \
	".section __ex_table,\"a\"\n" \
	".align 3\n" \
	PPC_LONG "1b,4b,2b,4b\n" \
	".previous" \
	: "=&r" (oldval), "=&r" (ret) \
	: "b" (uaddr), "i" (-EFAULT), "r" (oparg) \
	: "cr0", "memory")

static inline int futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
{
	int op = (encoded_op >> 28) & 7;
	int cmp = (encoded_op >> 24) & 15;
	int oparg = (encoded_op << 8) >> 20;
	int cmparg = (encoded_op << 20) >> 20;
	int oldval = 0, ret;
	if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
		oparg = 1 << oparg;

	if (! access_ok (VERIFY_WRITE, uaddr, sizeof(u32)))
		return -EFAULT;

	pagefault_disable();

	switch (op) {
	case FUTEX_OP_SET:
		__futex_atomic_op("mr %1,%4\n", ret, oldval, uaddr, oparg);
		break;
	case FUTEX_OP_ADD:
		__futex_atomic_op("add %1,%0,%4\n", ret, oldval, uaddr, oparg);
		break;
	case FUTEX_OP_OR:
		__futex_atomic_op("or %1,%0,%4\n", ret, oldval, uaddr, oparg);
		break;
	case FUTEX_OP_ANDN:
		__futex_atomic_op("andc %1,%0,%4\n", ret, oldval, uaddr, oparg);
		break;
	case FUTEX_OP_XOR:
		__futex_atomic_op("xor %1,%0,%4\n", ret, oldval, uaddr, oparg);
		break;
	default:
		ret = -ENOSYS;
	}

	pagefault_enable();

	if (!ret) {
		switch (cmp) {
		case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
		case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
		case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
		case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
		case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
		case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
		default: ret = -ENOSYS;
		}
	}
	return ret;
}

static inline int
futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
			      u32 oldval, u32 newval)
{
	int ret = 0;
	u32 prev;

	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
		return -EFAULT;

        __asm__ __volatile__ (
        PPC_ATOMIC_ENTRY_BARRIER
"1:     lwarx   %1,0,%3         # futex_atomic_cmpxchg_inatomic\n\
        cmpw    0,%1,%4\n\
        bne-    3f\n"
        PPC405_ERR77(0,%3)
"2:     stwcx.  %5,0,%3\n\
        bne-    1b\n"
        PPC_ATOMIC_EXIT_BARRIER
"3:	.section .fixup,\"ax\"\n\
4:	li	%0,%6\n\
	b	3b\n\
	.previous\n\
	.section __ex_table,\"a\"\n\
	.align 3\n\
	" PPC_LONG "1b,4b,2b,4b\n\
	.previous" \
        : "+r" (ret), "=&r" (prev), "+m" (*uaddr)
        : "r" (uaddr), "r" (oldval), "r" (newval), "i" (-EFAULT)
        : "cc", "memory");

	*uval = prev;
        return ret;
}

#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_FUTEX_H */
Commit	Line	Data
2ff2ae7a DG	1	#ifndef _ASM_POWERPC_FUTEX_H
2ff2ae7a DG	2	#define _ASM_POWERPC_FUTEX_H
4732efbe JJ	3
	4	#ifdef __KERNEL__
	5
	6	#include <linux/futex.h>
730f412c	7	#include <linux/uaccess.h>
4732efbe	8	#include <asm/errno.h>
feaf7cf1	9	#include <asm/synch.h>
3ddfbcf1	10	#include <asm/asm-compat.h>
4732efbe JJ	11
4732efbe JJ	12	#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
2ff2ae7a	13	__asm__ __volatile ( \
b97021f8	14	PPC_ATOMIC_ENTRY_BARRIER \
2ff2ae7a DG	15	"1: lwarx %0,0,%2\n" \
2ff2ae7a DG	16	insn \
3ddfbcf1	17	PPC405_ERR77(0, %2) \
2ff2ae7a DG	18	"2: stwcx. %1,0,%2\n" \
2ff2ae7a DG	19	"bne- 1b\n" \
b97021f8	20	PPC_ATOMIC_EXIT_BARRIER \
2ff2ae7a DG	21	"li %1,0\n" \
	22	"3: .section .fixup,\"ax\"\n" \
	23	"4: li %1,%3\n" \
	24	"b 3b\n" \
	25	".previous\n" \
	26	".section __ex_table,\"a\"\n" \
	27	".align 3\n" \
3ddfbcf1	28	PPC_LONG "1b,4b,2b,4b\n" \
2ff2ae7a DG	29	".previous" \
2ff2ae7a DG	30	: "=&r" (oldval), "=&r" (ret) \
306a8288	31	: "b" (uaddr), "i" (-EFAULT), "r" (oparg) \
4732efbe JJ	32	: "cr0", "memory")
4732efbe JJ	33
8d7718aa	34	static inline int futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
4732efbe JJ	35	{
	36	int op = (encoded_op >> 28) & 7;
	37	int cmp = (encoded_op >> 24) & 15;
	38	int oparg = (encoded_op << 8) >> 20;
	39	int cmparg = (encoded_op << 20) >> 20;
	40	int oldval = 0, ret;
	41	if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
	42	oparg = 1 << oparg;
	43
8d7718aa	44	if (! access_ok (VERIFY_WRITE, uaddr, sizeof(u32)))
4732efbe JJ	45	return -EFAULT;
4732efbe JJ	46
a866374a	47	pagefault_disable();
4732efbe JJ	48
	49	switch (op) {
	50	case FUTEX_OP_SET:
306a8288	51	__futex_atomic_op("mr %1,%4\n", ret, oldval, uaddr, oparg);
4732efbe JJ	52	break;
4732efbe JJ	53	case FUTEX_OP_ADD:
306a8288	54	__futex_atomic_op("add %1,%0,%4\n", ret, oldval, uaddr, oparg);
4732efbe JJ	55	break;
4732efbe JJ	56	case FUTEX_OP_OR:
306a8288	57	__futex_atomic_op("or %1,%0,%4\n", ret, oldval, uaddr, oparg);
4732efbe JJ	58	break;
4732efbe JJ	59	case FUTEX_OP_ANDN:
306a8288	60	__futex_atomic_op("andc %1,%0,%4\n", ret, oldval, uaddr, oparg);
4732efbe JJ	61	break;
4732efbe JJ	62	case FUTEX_OP_XOR:
306a8288	63	__futex_atomic_op("xor %1,%0,%4\n", ret, oldval, uaddr, oparg);
4732efbe JJ	64	break;
	65	default:
	66	ret = -ENOSYS;
	67	}
	68
a866374a	69	pagefault_enable();
4732efbe JJ	70
	71	if (!ret) {
	72	switch (cmp) {
	73	case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
	74	case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
	75	case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
	76	case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
	77	case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
	78	case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
	79	default: ret = -ENOSYS;
	80	}
	81	}
	82	return ret;
	83	}
	84
e9056f13	85	static inline int
8d7718aa ML	86	futex_atomic_cmpxchg_inatomic(u32 uval, u32 __user uaddr,
8d7718aa ML	87	u32 oldval, u32 newval)
e9056f13	88	{
8d7718aa ML	89	int ret = 0;
8d7718aa ML	90	u32 prev;
69588298	91
8d7718aa	92	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
69588298 DW	93	return -EFAULT;
	94
	95	__asm__ __volatile__ (
b97021f8	96	PPC_ATOMIC_ENTRY_BARRIER
37a9d912 ML	97	"1: lwarx %1,0,%3 # futex_atomic_cmpxchg_inatomic\n\
37a9d912 ML	98	cmpw 0,%1,%4\n\
69588298	99	bne- 3f\n"
37a9d912 ML	100	PPC405_ERR77(0,%3)
37a9d912 ML	101	"2: stwcx. %5,0,%3\n\
69588298	102	bne- 1b\n"
b97021f8	103	PPC_ATOMIC_EXIT_BARRIER
69588298	104	"3: .section .fixup,\"ax\"\n\
37a9d912	105	4: li %0,%6\n\
69588298 DW	106	b 3b\n\
	107	.previous\n\
	108	.section __ex_table,\"a\"\n\
	109	.align 3\n\
	110	" PPC_LONG "1b,4b,2b,4b\n\
	111	.previous" \
37a9d912	112	: "+r" (ret), "=&r" (prev), "+m" (*uaddr)
69588298 DW	113	: "r" (uaddr), "r" (oldval), "r" (newval), "i" (-EFAULT)
	114	: "cc", "memory");
	115
37a9d912 ML	116	*uval = prev;
37a9d912 ML	117	return ret;
e9056f13 IM	118	}
e9056f13 IM	119
2ff2ae7a DG	120	#endif /* __KERNEL__ */
2ff2ae7a DG	121	#endif /* _ASM_POWERPC_FUTEX_H */