[deliverable/linux.git] / arch / powerpc / include / asm / kvm_book3s_64.h

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2, as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 *
 * Copyright SUSE Linux Products GmbH 2010
 *
 * Authors: Alexander Graf <agraf@suse.de>
 */

#ifndef __ASM_KVM_BOOK3S_64_H__
#define __ASM_KVM_BOOK3S_64_H__

#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
static inline struct kvmppc_book3s_shadow_vcpu *svcpu_get(struct kvm_vcpu *vcpu)
{
	preempt_disable();
	return &get_paca()->shadow_vcpu;
}

static inline void svcpu_put(struct kvmppc_book3s_shadow_vcpu *svcpu)
{
	preempt_enable();
}
#endif

#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
#define KVM_DEFAULT_HPT_ORDER	24	/* 16MB HPT by default */
#endif

#define VRMA_VSID	0x1ffffffUL	/* 1TB VSID reserved for VRMA */

/*
 * We use a lock bit in HPTE dword 0 to synchronize updates and
 * accesses to each HPTE, and another bit to indicate non-present
 * HPTEs.
 */
#define HPTE_V_HVLOCK	0x40UL
#define HPTE_V_ABSENT	0x20UL

/*
 * We use this bit in the guest_rpte field of the revmap entry
 * to indicate a modified HPTE.
 */
#define HPTE_GR_MODIFIED	(1ul << 62)

/* These bits are reserved in the guest view of the HPTE */
#define HPTE_GR_RESERVED	HPTE_GR_MODIFIED

static inline long try_lock_hpte(__be64 *hpte, unsigned long bits)
{
	unsigned long tmp, old;
	__be64 be_lockbit, be_bits;

	/*
	 * We load/store in native endian, but the HTAB is in big endian. If
	 * we byte swap all data we apply on the PTE we're implicitly correct
	 * again.
	 */
	be_lockbit = cpu_to_be64(HPTE_V_HVLOCK);
	be_bits = cpu_to_be64(bits);

	asm volatile("	ldarx	%0,0,%2\n"
		     "	and.	%1,%0,%3\n"
		     "	bne	2f\n"
		     "	or	%0,%0,%4\n"
		     "  stdcx.	%0,0,%2\n"
		     "	beq+	2f\n"
		     "	mr	%1,%3\n"
		     "2:	isync"
		     : "=&r" (tmp), "=&r" (old)
		     : "r" (hpte), "r" (be_bits), "r" (be_lockbit)
		     : "cc", "memory");
	return old == 0;
}

static inline void unlock_hpte(__be64 *hpte, unsigned long hpte_v)
{
	hpte_v &= ~HPTE_V_HVLOCK;
	asm volatile(PPC_RELEASE_BARRIER "" : : : "memory");
	hpte[0] = cpu_to_be64(hpte_v);
}

/* Without barrier */
static inline void __unlock_hpte(__be64 *hpte, unsigned long hpte_v)
{
	hpte_v &= ~HPTE_V_HVLOCK;
	hpte[0] = cpu_to_be64(hpte_v);
}

static inline int __hpte_actual_psize(unsigned int lp, int psize)
{
	int i, shift;
	unsigned int mask;

	/* start from 1 ignoring MMU_PAGE_4K */
	for (i = 1; i < MMU_PAGE_COUNT; i++) {

		/* invalid penc */
		if (mmu_psize_defs[psize].penc[i] == -1)
			continue;
		/*
		 * encoding bits per actual page size
		 *        PTE LP     actual page size
		 *    rrrr rrrz		>=8KB
		 *    rrrr rrzz		>=16KB
		 *    rrrr rzzz		>=32KB
		 *    rrrr zzzz		>=64KB
		 * .......
		 */
		shift = mmu_psize_defs[i].shift - LP_SHIFT;
		if (shift > LP_BITS)
			shift = LP_BITS;
		mask = (1 << shift) - 1;
		if ((lp & mask) == mmu_psize_defs[psize].penc[i])
			return i;
	}
	return -1;
}

static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
					     unsigned long pte_index)
{
	int b_psize = MMU_PAGE_4K, a_psize = MMU_PAGE_4K;
	unsigned int penc;
	unsigned long rb = 0, va_low, sllp;
	unsigned int lp = (r >> LP_SHIFT) & ((1 << LP_BITS) - 1);

	if (v & HPTE_V_LARGE) {
		for (b_psize = 0; b_psize < MMU_PAGE_COUNT; b_psize++) {

			/* valid entries have a shift value */
			if (!mmu_psize_defs[b_psize].shift)
				continue;

			a_psize = __hpte_actual_psize(lp, b_psize);
			if (a_psize != -1)
				break;
		}
	}
	/*
	 * Ignore the top 14 bits of va
	 * v have top two bits covering segment size, hence move
	 * by 16 bits, Also clear the lower HPTE_V_AVPN_SHIFT (7) bits.
	 * AVA field in v also have the lower 23 bits ignored.
	 * For base page size 4K we need 14 .. 65 bits (so need to
	 * collect extra 11 bits)
	 * For others we need 14..14+i
	 */
	/* This covers 14..54 bits of va*/
	rb = (v & ~0x7fUL) << 16;		/* AVA field */

	rb |= (v >> HPTE_V_SSIZE_SHIFT) << 8;	/*  B field */
	/*
	 * AVA in v had cleared lower 23 bits. We need to derive
	 * that from pteg index
	 */
	va_low = pte_index >> 3;
	if (v & HPTE_V_SECONDARY)
		va_low = ~va_low;
	/*
	 * get the vpn bits from va_low using reverse of hashing.
	 * In v we have va with 23 bits dropped and then left shifted
	 * HPTE_V_AVPN_SHIFT (7) bits. Now to find vsid we need
	 * right shift it with (SID_SHIFT - (23 - 7))
	 */
	if (!(v & HPTE_V_1TB_SEG))
		va_low ^= v >> (SID_SHIFT - 16);
	else
		va_low ^= v >> (SID_SHIFT_1T - 16);
	va_low &= 0x7ff;

	switch (b_psize) {
	case MMU_PAGE_4K:
		sllp = ((mmu_psize_defs[a_psize].sllp & SLB_VSID_L) >> 6) |
			((mmu_psize_defs[a_psize].sllp & SLB_VSID_LP) >> 4);
		rb |= sllp << 5;	/*  AP field */
		rb |= (va_low & 0x7ff) << 12;	/* remaining 11 bits of AVA */
		break;
	default:
	{
		int aval_shift;
		/*
		 * remaining bits of AVA/LP fields
		 * Also contain the rr bits of LP
		 */
		rb |= (va_low << mmu_psize_defs[b_psize].shift) & 0x7ff000;
		/*
		 * Now clear not needed LP bits based on actual psize
		 */
		rb &= ~((1ul << mmu_psize_defs[a_psize].shift) - 1);
		/*
		 * AVAL field 58..77 - base_page_shift bits of va
		 * we have space for 58..64 bits, Missing bits should
		 * be zero filled. +1 is to take care of L bit shift
		 */
		aval_shift = 64 - (77 - mmu_psize_defs[b_psize].shift) + 1;
		rb |= ((va_low << aval_shift) & 0xfe);

		rb |= 1;		/* L field */
		penc = mmu_psize_defs[b_psize].penc[a_psize];
		rb |= penc << 12;	/* LP field */
		break;
	}
	}
	rb |= (v >> 54) & 0x300;		/* B field */
	return rb;
}

static inline unsigned long __hpte_page_size(unsigned long h, unsigned long l,
					     bool is_base_size)
{

	int size, a_psize;
	/* Look at the 8 bit LP value */
	unsigned int lp = (l >> LP_SHIFT) & ((1 << LP_BITS) - 1);

	/* only handle 4k, 64k and 16M pages for now */
	if (!(h & HPTE_V_LARGE))
		return 1ul << 12;
	else {
		for (size = 0; size < MMU_PAGE_COUNT; size++) {
			/* valid entries have a shift value */
			if (!mmu_psize_defs[size].shift)
				continue;

			a_psize = __hpte_actual_psize(lp, size);
			if (a_psize != -1) {
				if (is_base_size)
					return 1ul << mmu_psize_defs[size].shift;
				return 1ul << mmu_psize_defs[a_psize].shift;
			}
		}

	}
	return 0;
}

static inline unsigned long hpte_page_size(unsigned long h, unsigned long l)
{
	return __hpte_page_size(h, l, 0);
}

static inline unsigned long hpte_base_page_size(unsigned long h, unsigned long l)
{
	return __hpte_page_size(h, l, 1);
}

static inline unsigned long hpte_rpn(unsigned long ptel, unsigned long psize)
{
	return ((ptel & HPTE_R_RPN) & ~(psize - 1)) >> PAGE_SHIFT;
}

static inline int hpte_is_writable(unsigned long ptel)
{
	unsigned long pp = ptel & (HPTE_R_PP0 | HPTE_R_PP);

	return pp != PP_RXRX && pp != PP_RXXX;
}

static inline unsigned long hpte_make_readonly(unsigned long ptel)
{
	if ((ptel & HPTE_R_PP0) || (ptel & HPTE_R_PP) == PP_RWXX)
		ptel = (ptel & ~HPTE_R_PP) | PP_RXXX;
	else
		ptel |= PP_RXRX;
	return ptel;
}

static inline int hpte_cache_flags_ok(unsigned long ptel, unsigned long io_type)
{
	unsigned int wimg = ptel & HPTE_R_WIMG;

	/* Handle SAO */
	if (wimg == (HPTE_R_W | HPTE_R_I | HPTE_R_M) &&
	    cpu_has_feature(CPU_FTR_ARCH_206))
		wimg = HPTE_R_M;

	if (!io_type)
		return wimg == HPTE_R_M;

	return (wimg & (HPTE_R_W | HPTE_R_I)) == io_type;
}

/*
 * If it's present and writable, atomically set dirty and referenced bits and
 * return the PTE, otherwise return 0.
 */
static inline pte_t kvmppc_read_update_linux_pte(pte_t *ptep, int writing)
{
	pte_t old_pte, new_pte = __pte(0);

	while (1) {
		/*
		 * Make sure we don't reload from ptep
		 */
		old_pte = READ_ONCE(*ptep);
		/*
		 * wait until _PAGE_BUSY is clear then set it atomically
		 */
		if (unlikely(pte_val(old_pte) & _PAGE_BUSY)) {
			cpu_relax();
			continue;
		}
		/* If pte is not present return None */
		if (unlikely(!(pte_val(old_pte) & _PAGE_PRESENT)))
			return __pte(0);

		new_pte = pte_mkyoung(old_pte);
		if (writing && pte_write(old_pte))
			new_pte = pte_mkdirty(new_pte);

		if (pte_val(old_pte) == __cmpxchg_u64((unsigned long *)ptep,
						      pte_val(old_pte),
						      pte_val(new_pte))) {
			break;
		}
	}
	return new_pte;
}


/* Return HPTE cache control bits corresponding to Linux pte bits */
static inline unsigned long hpte_cache_bits(unsigned long pte_val)
{
#if _PAGE_NO_CACHE == HPTE_R_I && _PAGE_WRITETHRU == HPTE_R_W
	return pte_val & (HPTE_R_W | HPTE_R_I);
#else
	return ((pte_val & _PAGE_NO_CACHE) ? HPTE_R_I : 0) +
		((pte_val & _PAGE_WRITETHRU) ? HPTE_R_W : 0);
#endif
}

static inline bool hpte_read_permission(unsigned long pp, unsigned long key)
{
	if (key)
		return PP_RWRX <= pp && pp <= PP_RXRX;
	return true;
}

static inline bool hpte_write_permission(unsigned long pp, unsigned long key)
{
	if (key)
		return pp == PP_RWRW;
	return pp <= PP_RWRW;
}

static inline int hpte_get_skey_perm(unsigned long hpte_r, unsigned long amr)
{
	unsigned long skey;

	skey = ((hpte_r & HPTE_R_KEY_HI) >> 57) |
		((hpte_r & HPTE_R_KEY_LO) >> 9);
	return (amr >> (62 - 2 * skey)) & 3;
}

static inline void lock_rmap(unsigned long *rmap)
{
	do {
		while (test_bit(KVMPPC_RMAP_LOCK_BIT, rmap))
			cpu_relax();
	} while (test_and_set_bit_lock(KVMPPC_RMAP_LOCK_BIT, rmap));
}

static inline void unlock_rmap(unsigned long *rmap)
{
	__clear_bit_unlock(KVMPPC_RMAP_LOCK_BIT, rmap);
}

static inline bool slot_is_aligned(struct kvm_memory_slot *memslot,
				   unsigned long pagesize)
{
	unsigned long mask = (pagesize >> PAGE_SHIFT) - 1;

	if (pagesize <= PAGE_SIZE)
		return true;
	return !(memslot->base_gfn & mask) && !(memslot->npages & mask);
}

/*
 * This works for 4k, 64k and 16M pages on POWER7,
 * and 4k and 16M pages on PPC970.
 */
static inline unsigned long slb_pgsize_encoding(unsigned long psize)
{
	unsigned long senc = 0;

	if (psize > 0x1000) {
		senc = SLB_VSID_L;
		if (psize == 0x10000)
			senc |= SLB_VSID_LP_01;
	}
	return senc;
}

static inline int is_vrma_hpte(unsigned long hpte_v)
{
	return (hpte_v & ~0xffffffUL) ==
		(HPTE_V_1TB_SEG | (VRMA_VSID << (40 - 16)));
}

#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
/*
 * Note modification of an HPTE; set the HPTE modified bit
 * if anyone is interested.
 */
static inline void note_hpte_modification(struct kvm *kvm,
					  struct revmap_entry *rev)
{
	if (atomic_read(&kvm->arch.hpte_mod_interest))
		rev->guest_rpte |= HPTE_GR_MODIFIED;
}

/*
 * Like kvm_memslots(), but for use in real mode when we can't do
 * any RCU stuff (since the secondary threads are offline from the
 * kernel's point of view), and we can't print anything.
 * Thus we use rcu_dereference_raw() rather than rcu_dereference_check().
 */
static inline struct kvm_memslots *kvm_memslots_raw(struct kvm *kvm)
{
	return rcu_dereference_raw_notrace(kvm->memslots[0]);
}

extern void kvmppc_mmu_debugfs_init(struct kvm *kvm);

extern void kvmhv_rm_send_ipi(int cpu);

#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */

#endif /* __ASM_KVM_BOOK3S_64_H__ */
Commit	Line	Data
3ae07890 AG	1	/*
	2	* This program is free software; you can redistribute it and/or modify
	3	* it under the terms of the GNU General Public License, version 2, as
	4	* published by the Free Software Foundation.
	5	*
	6	* This program is distributed in the hope that it will be useful,
	7	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	8	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	9	* GNU General Public License for more details.
	10	*
	11	* You should have received a copy of the GNU General Public License
	12	* along with this program; if not, write to the Free Software
	13	* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
	14	*
	15	* Copyright SUSE Linux Products GmbH 2010
	16	*
	17	* Authors: Alexander Graf <agraf@suse.de>
	18	*/
	19
	20	#ifndef __ASM_KVM_BOOK3S_64_H__
	21	#define __ASM_KVM_BOOK3S_64_H__
	22
7aa79938	23	#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
468a12c2	24	static inline struct kvmppc_book3s_shadow_vcpu svcpu_get(struct kvm_vcpu vcpu)
3ae07890	25	{
468a12c2	26	preempt_disable();
3ae07890 AG	27	return &get_paca()->shadow_vcpu;
3ae07890 AG	28	}
468a12c2 AG	29
	30	static inline void svcpu_put(struct kvmppc_book3s_shadow_vcpu *svcpu)
	31	{
	32	preempt_enable();
	33	}
de56a948	34	#endif
3ae07890	35
9975f5e3	36	#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
32fad281	37	#define KVM_DEFAULT_HPT_ORDER 24 /* 16MB HPT by default */
8936dda4 PM	38	#endif
8936dda4 PM	39
697d3899 PM	40	#define VRMA_VSID 0x1ffffffUL /* 1TB VSID reserved for VRMA */
697d3899 PM	41
075295dd PM	42	/*
	43	* We use a lock bit in HPTE dword 0 to synchronize updates and
	44	* accesses to each HPTE, and another bit to indicate non-present
	45	* HPTEs.
	46	*/
	47	#define HPTE_V_HVLOCK 0x40UL
697d3899	48	#define HPTE_V_ABSENT 0x20UL
075295dd	49
44e5f6be PM	50	/*
	51	* We use this bit in the guest_rpte field of the revmap entry
	52	* to indicate a modified HPTE.
	53	*/
	54	#define HPTE_GR_MODIFIED (1ul << 62)
	55
	56	/* These bits are reserved in the guest view of the HPTE */
	57	#define HPTE_GR_RESERVED HPTE_GR_MODIFIED
	58
6f22bd32	59	static inline long try_lock_hpte(__be64 *hpte, unsigned long bits)
075295dd PM	60	{
075295dd PM	61	unsigned long tmp, old;
6f22bd32 AG	62	__be64 be_lockbit, be_bits;
	63
	64	/*
	65	* We load/store in native endian, but the HTAB is in big endian. If
	66	* we byte swap all data we apply on the PTE we're implicitly correct
	67	* again.
	68	*/
	69	be_lockbit = cpu_to_be64(HPTE_V_HVLOCK);
	70	be_bits = cpu_to_be64(bits);
075295dd PM	71
	72	asm volatile(" ldarx %0,0,%2\n"
	73	" and. %1,%0,%3\n"
	74	" bne 2f\n"
6f22bd32	75	" or %0,%0,%4\n"
075295dd PM	76	" stdcx. %0,0,%2\n"
075295dd PM	77	" beq+ 2f\n"
8b5869ad	78	" mr %1,%3\n"
075295dd PM	79	"2: isync"
075295dd PM	80	: "=&r" (tmp), "=&r" (old)
6f22bd32	81	: "r" (hpte), "r" (be_bits), "r" (be_lockbit)
075295dd PM	82	: "cc", "memory");
	83	return old == 0;
	84	}
	85
a4bd6eb0 AK	86	static inline void unlock_hpte(__be64 *hpte, unsigned long hpte_v)
	87	{
	88	hpte_v &= ~HPTE_V_HVLOCK;
	89	asm volatile(PPC_RELEASE_BARRIER "" : : : "memory");
	90	hpte[0] = cpu_to_be64(hpte_v);
	91	}
	92
	93	/* Without barrier */
	94	static inline void __unlock_hpte(__be64 *hpte, unsigned long hpte_v)
	95	{
	96	hpte_v &= ~HPTE_V_HVLOCK;
	97	hpte[0] = cpu_to_be64(hpte_v);
	98	}
	99
1f365bb0 AK	100	static inline int __hpte_actual_psize(unsigned int lp, int psize)
	101	{
	102	int i, shift;
	103	unsigned int mask;
	104
	105	/* start from 1 ignoring MMU_PAGE_4K */
	106	for (i = 1; i < MMU_PAGE_COUNT; i++) {
	107
	108	/* invalid penc */
	109	if (mmu_psize_defs[psize].penc[i] == -1)
	110	continue;
	111	/*
	112	* encoding bits per actual page size
	113	* PTE LP actual page size
	114	* rrrr rrrz >=8KB
	115	* rrrr rrzz >=16KB
	116	* rrrr rzzz >=32KB
	117	* rrrr zzzz >=64KB
	118	* .......
	119	*/
	120	shift = mmu_psize_defs[i].shift - LP_SHIFT;
	121	if (shift > LP_BITS)
	122	shift = LP_BITS;
	123	mask = (1 << shift) - 1;
	124	if ((lp & mask) == mmu_psize_defs[psize].penc[i])
	125	return i;
	126	}
	127	return -1;
	128	}
	129
36cc66d6 AS	130	static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
	131	unsigned long pte_index)
	132	{
f6bf3a66	133	int b_psize = MMU_PAGE_4K, a_psize = MMU_PAGE_4K;
1f365bb0 AK	134	unsigned int penc;
	135	unsigned long rb = 0, va_low, sllp;
	136	unsigned int lp = (r >> LP_SHIFT) & ((1 << LP_BITS) - 1);
	137
f6bf3a66	138	if (v & HPTE_V_LARGE) {
1f365bb0 AK	139	for (b_psize = 0; b_psize < MMU_PAGE_COUNT; b_psize++) {
	140
	141	/* valid entries have a shift value */
	142	if (!mmu_psize_defs[b_psize].shift)
	143	continue;
36cc66d6	144
1f365bb0 AK	145	a_psize = __hpte_actual_psize(lp, b_psize);
	146	if (a_psize != -1)
	147	break;
	148	}
	149	}
	150	/*
	151	* Ignore the top 14 bits of va
	152	* v have top two bits covering segment size, hence move
	153	* by 16 bits, Also clear the lower HPTE_V_AVPN_SHIFT (7) bits.
	154	* AVA field in v also have the lower 23 bits ignored.
	155	* For base page size 4K we need 14 .. 65 bits (so need to
	156	* collect extra 11 bits)
	157	* For others we need 14..14+i
	158	*/
	159	/* This covers 14..54 bits of va*/
36cc66d6	160	rb = (v & ~0x7fUL) << 16; /* AVA field */
63fff5c1	161
d506735b	162	rb \|= (v >> HPTE_V_SSIZE_SHIFT) << 8; /* B field */
1f365bb0 AK	163	/*
	164	* AVA in v had cleared lower 23 bits. We need to derive
	165	* that from pteg index
	166	*/
36cc66d6 AS	167	va_low = pte_index >> 3;
	168	if (v & HPTE_V_SECONDARY)
	169	va_low = ~va_low;
1f365bb0 AK	170	/*
	171	* get the vpn bits from va_low using reverse of hashing.
	172	* In v we have va with 23 bits dropped and then left shifted
	173	* HPTE_V_AVPN_SHIFT (7) bits. Now to find vsid we need
	174	* right shift it with (SID_SHIFT - (23 - 7))
	175	*/
36cc66d6	176	if (!(v & HPTE_V_1TB_SEG))
1f365bb0	177	va_low ^= v >> (SID_SHIFT - 16);
36cc66d6	178	else
1f365bb0	179	va_low ^= v >> (SID_SHIFT_1T - 16);
36cc66d6	180	va_low &= 0x7ff;
1f365bb0 AK	181
	182	switch (b_psize) {
	183	case MMU_PAGE_4K:
	184	sllp = ((mmu_psize_defs[a_psize].sllp & SLB_VSID_L) >> 6) \|
	185	((mmu_psize_defs[a_psize].sllp & SLB_VSID_LP) >> 4);
	186	rb \|= sllp << 5; /* AP field */
	187	rb \|= (va_low & 0x7ff) << 12; /* remaining 11 bits of AVA */
	188	break;
	189	default:
	190	{
	191	int aval_shift;
	192	/*
63fff5c1	193	* remaining bits of AVA/LP fields
1f365bb0 AK	194	* Also contain the rr bits of LP
1f365bb0 AK	195	*/
63fff5c1	196	rb \|= (va_low << mmu_psize_defs[b_psize].shift) & 0x7ff000;
1f365bb0 AK	197	/*
	198	* Now clear not needed LP bits based on actual psize
	199	*/
	200	rb &= ~((1ul << mmu_psize_defs[a_psize].shift) - 1);
	201	/*
	202	* AVAL field 58..77 - base_page_shift bits of va
	203	* we have space for 58..64 bits, Missing bits should
	204	* be zero filled. +1 is to take care of L bit shift
	205	*/
	206	aval_shift = 64 - (77 - mmu_psize_defs[b_psize].shift) + 1;
	207	rb \|= ((va_low << aval_shift) & 0xfe);
	208
	209	rb \|= 1; /* L field */
	210	penc = mmu_psize_defs[b_psize].penc[a_psize];
	211	rb \|= penc << 12; /* LP field */
	212	break;
	213	}
36cc66d6 AS	214	}
	215	rb \|= (v >> 54) & 0x300; /* B field */
	216	return rb;
	217	}
	218
341acbb3 AK	219	static inline unsigned long __hpte_page_size(unsigned long h, unsigned long l,
341acbb3 AK	220	bool is_base_size)
c77162de	221	{
341acbb3	222
1f365bb0 AK	223	int size, a_psize;
	224	/* Look at the 8 bit LP value */
	225	unsigned int lp = (l >> LP_SHIFT) & ((1 << LP_BITS) - 1);
	226
c77162de PM	227	/* only handle 4k, 64k and 16M pages for now */
c77162de PM	228	if (!(h & HPTE_V_LARGE))
1f365bb0 AK	229	return 1ul << 12;
	230	else {
	231	for (size = 0; size < MMU_PAGE_COUNT; size++) {
	232	/* valid entries have a shift value */
	233	if (!mmu_psize_defs[size].shift)
	234	continue;
	235
	236	a_psize = __hpte_actual_psize(lp, size);
341acbb3 AK	237	if (a_psize != -1) {
	238	if (is_base_size)
	239	return 1ul << mmu_psize_defs[size].shift;
1f365bb0	240	return 1ul << mmu_psize_defs[a_psize].shift;
341acbb3	241	}
1f365bb0 AK	242	}
	243
	244	}
	245	return 0;
c77162de PM	246	}
c77162de PM	247
341acbb3 AK	248	static inline unsigned long hpte_page_size(unsigned long h, unsigned long l)
	249	{
	250	return __hpte_page_size(h, l, 0);
	251	}
	252
	253	static inline unsigned long hpte_base_page_size(unsigned long h, unsigned long l)
	254	{
	255	return __hpte_page_size(h, l, 1);
	256	}
	257
06ce2c63 PM	258	static inline unsigned long hpte_rpn(unsigned long ptel, unsigned long psize)
	259	{
	260	return ((ptel & HPTE_R_RPN) & ~(psize - 1)) >> PAGE_SHIFT;
	261	}
	262
4cf302bc PM	263	static inline int hpte_is_writable(unsigned long ptel)
	264	{
	265	unsigned long pp = ptel & (HPTE_R_PP0 \| HPTE_R_PP);
	266
	267	return pp != PP_RXRX && pp != PP_RXXX;
	268	}
	269
	270	static inline unsigned long hpte_make_readonly(unsigned long ptel)
	271	{
	272	if ((ptel & HPTE_R_PP0) \|\| (ptel & HPTE_R_PP) == PP_RWXX)
	273	ptel = (ptel & ~HPTE_R_PP) \| PP_RXXX;
	274	else
	275	ptel \|= PP_RXRX;
	276	return ptel;
	277	}
	278
9d0ef5ea PM	279	static inline int hpte_cache_flags_ok(unsigned long ptel, unsigned long io_type)
	280	{
	281	unsigned int wimg = ptel & HPTE_R_WIMG;
	282
	283	/* Handle SAO */
	284	if (wimg == (HPTE_R_W \| HPTE_R_I \| HPTE_R_M) &&
	285	cpu_has_feature(CPU_FTR_ARCH_206))
	286	wimg = HPTE_R_M;
	287
	288	if (!io_type)
	289	return wimg == HPTE_R_M;
	290
	291	return (wimg & (HPTE_R_W \| HPTE_R_I)) == io_type;
	292	}
	293
342d3db7	294	/*
db7cb5b9	295	* If it's present and writable, atomically set dirty and referenced bits and
7d6e7f7f	296	* return the PTE, otherwise return 0.
342d3db7	297	*/
7d6e7f7f	298	static inline pte_t kvmppc_read_update_linux_pte(pte_t *ptep, int writing)
342d3db7	299	{
db7cb5b9 AK	300	pte_t old_pte, new_pte = __pte(0);
	301
	302	while (1) {
5e1d44ae AK	303	/*
	304	* Make sure we don't reload from ptep
	305	*/
	306	old_pte = READ_ONCE(*ptep);
db7cb5b9 AK	307	/*
	308	* wait until _PAGE_BUSY is clear then set it atomically
	309	*/
4f9c53c8	310	if (unlikely(pte_val(old_pte) & _PAGE_BUSY)) {
db7cb5b9 AK	311	cpu_relax();
	312	continue;
	313	}
db7cb5b9	314	/* If pte is not present return None */
4f9c53c8	315	if (unlikely(!(pte_val(old_pte) & _PAGE_PRESENT)))
db7cb5b9	316	return __pte(0);
342d3db7	317
db7cb5b9 AK	318	new_pte = pte_mkyoung(old_pte);
	319	if (writing && pte_write(old_pte))
	320	new_pte = pte_mkdirty(new_pte);
342d3db7	321
4f9c53c8 ME	322	if (pte_val(old_pte) == __cmpxchg_u64((unsigned long *)ptep,
	323	pte_val(old_pte),
	324	pte_val(new_pte))) {
db7cb5b9	325	break;
4f9c53c8	326	}
db7cb5b9 AK	327	}
db7cb5b9 AK	328	return new_pte;
342d3db7 PM	329	}
342d3db7 PM	330
db7cb5b9	331
9d0ef5ea PM	332	/* Return HPTE cache control bits corresponding to Linux pte bits */
	333	static inline unsigned long hpte_cache_bits(unsigned long pte_val)
	334	{
	335	#if _PAGE_NO_CACHE == HPTE_R_I && _PAGE_WRITETHRU == HPTE_R_W
	336	return pte_val & (HPTE_R_W \| HPTE_R_I);
	337	#else
	338	return ((pte_val & _PAGE_NO_CACHE) ? HPTE_R_I : 0) +
	339	((pte_val & _PAGE_WRITETHRU) ? HPTE_R_W : 0);
	340	#endif
	341	}
	342
697d3899 PM	343	static inline bool hpte_read_permission(unsigned long pp, unsigned long key)
	344	{
	345	if (key)
	346	return PP_RWRX <= pp && pp <= PP_RXRX;
acdb6685	347	return true;
697d3899 PM	348	}
	349
	350	static inline bool hpte_write_permission(unsigned long pp, unsigned long key)
	351	{
	352	if (key)
	353	return pp == PP_RWRW;
	354	return pp <= PP_RWRW;
	355	}
	356
	357	static inline int hpte_get_skey_perm(unsigned long hpte_r, unsigned long amr)
	358	{
	359	unsigned long skey;
	360
	361	skey = ((hpte_r & HPTE_R_KEY_HI) >> 57) \|
	362	((hpte_r & HPTE_R_KEY_LO) >> 9);
	363	return (amr >> (62 - 2 * skey)) & 3;
	364	}
	365
06ce2c63 PM	366	static inline void lock_rmap(unsigned long *rmap)
	367	{
	368	do {
	369	while (test_bit(KVMPPC_RMAP_LOCK_BIT, rmap))
	370	cpu_relax();
	371	} while (test_and_set_bit_lock(KVMPPC_RMAP_LOCK_BIT, rmap));
	372	}
	373
	374	static inline void unlock_rmap(unsigned long *rmap)
	375	{
	376	__clear_bit_unlock(KVMPPC_RMAP_LOCK_BIT, rmap);
	377	}
	378
da9d1d7f PM	379	static inline bool slot_is_aligned(struct kvm_memory_slot *memslot,
	380	unsigned long pagesize)
	381	{
	382	unsigned long mask = (pagesize >> PAGE_SHIFT) - 1;
	383
	384	if (pagesize <= PAGE_SIZE)
acdb6685	385	return true;
da9d1d7f PM	386	return !(memslot->base_gfn & mask) && !(memslot->npages & mask);
	387	}
	388
a2932923 PM	389	/*
	390	* This works for 4k, 64k and 16M pages on POWER7,
	391	* and 4k and 16M pages on PPC970.
	392	*/
	393	static inline unsigned long slb_pgsize_encoding(unsigned long psize)
	394	{
	395	unsigned long senc = 0;
	396
	397	if (psize > 0x1000) {
	398	senc = SLB_VSID_L;
	399	if (psize == 0x10000)
	400	senc \|= SLB_VSID_LP_01;
	401	}
	402	return senc;
	403	}
	404
	405	static inline int is_vrma_hpte(unsigned long hpte_v)
	406	{
	407	return (hpte_v & ~0xffffffUL) ==
	408	(HPTE_V_1TB_SEG \| (VRMA_VSID << (40 - 16)));
	409	}
	410
9975f5e3	411	#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
a1b4a0f6 PM	412	/*
	413	* Note modification of an HPTE; set the HPTE modified bit
	414	* if anyone is interested.
	415	*/
	416	static inline void note_hpte_modification(struct kvm *kvm,
	417	struct revmap_entry *rev)
	418	{
	419	if (atomic_read(&kvm->arch.hpte_mod_interest))
	420	rev->guest_rpte \|= HPTE_GR_MODIFIED;
	421	}
797f9c07 PM	422
	423	/*
	424	* Like kvm_memslots(), but for use in real mode when we can't do
	425	* any RCU stuff (since the secondary threads are offline from the
	426	* kernel's point of view), and we can't print anything.
	427	* Thus we use rcu_dereference_raw() rather than rcu_dereference_check().
	428	*/
	429	static inline struct kvm_memslots kvm_memslots_raw(struct kvm kvm)
	430	{
f481b069	431	return rcu_dereference_raw_notrace(kvm->memslots[0]);
797f9c07 PM	432	}
797f9c07 PM	433
e23a808b PM	434	extern void kvmppc_mmu_debugfs_init(struct kvm *kvm);
e23a808b PM	435
eddb60fb PM	436	extern void kvmhv_rm_send_ipi(int cpu);
eddb60fb PM	437
9975f5e3	438	#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
a1b4a0f6	439
3ae07890	440	#endif /* __ASM_KVM_BOOK3S_64_H__ */