[deliverable/linux.git] / arch / powerpc / include / asm / kvm_book3s_64.h

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2, as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 *
 * Copyright SUSE Linux Products GmbH 2010
 *
 * Authors: Alexander Graf <agraf@suse.de>
 */

#ifndef __ASM_KVM_BOOK3S_64_H__
#define __ASM_KVM_BOOK3S_64_H__

#ifdef CONFIG_KVM_BOOK3S_PR
static inline struct kvmppc_book3s_shadow_vcpu *svcpu_get(struct kvm_vcpu *vcpu)
{
	preempt_disable();
	return &get_paca()->shadow_vcpu;
}

static inline void svcpu_put(struct kvmppc_book3s_shadow_vcpu *svcpu)
{
	preempt_enable();
}
#endif

#define SPAPR_TCE_SHIFT		12

#ifdef CONFIG_KVM_BOOK3S_64_HV
/* For now use fixed-size 16MB page table */
#define HPT_ORDER	24
#define HPT_NPTEG	(1ul << (HPT_ORDER - 7))	/* 128B per pteg */
#define HPT_NPTE	(HPT_NPTEG << 3)		/* 8 PTEs per PTEG */
#define HPT_HASH_MASK	(HPT_NPTEG - 1)
#endif

#define VRMA_VSID	0x1ffffffUL	/* 1TB VSID reserved for VRMA */

/*
 * We use a lock bit in HPTE dword 0 to synchronize updates and
 * accesses to each HPTE, and another bit to indicate non-present
 * HPTEs.
 */
#define HPTE_V_HVLOCK	0x40UL
#define HPTE_V_ABSENT	0x20UL

static inline long try_lock_hpte(unsigned long *hpte, unsigned long bits)
{
	unsigned long tmp, old;

	asm volatile("	ldarx	%0,0,%2\n"
		     "	and.	%1,%0,%3\n"
		     "	bne	2f\n"
		     "	ori	%0,%0,%4\n"
		     "  stdcx.	%0,0,%2\n"
		     "	beq+	2f\n"
		     "	li	%1,%3\n"
		     "2:	isync"
		     : "=&r" (tmp), "=&r" (old)
		     : "r" (hpte), "r" (bits), "i" (HPTE_V_HVLOCK)
		     : "cc", "memory");
	return old == 0;
}

static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
					     unsigned long pte_index)
{
	unsigned long rb, va_low;

	rb = (v & ~0x7fUL) << 16;		/* AVA field */
	va_low = pte_index >> 3;
	if (v & HPTE_V_SECONDARY)
		va_low = ~va_low;
	/* xor vsid from AVA */
	if (!(v & HPTE_V_1TB_SEG))
		va_low ^= v >> 12;
	else
		va_low ^= v >> 24;
	va_low &= 0x7ff;
	if (v & HPTE_V_LARGE) {
		rb |= 1;			/* L field */
		if (cpu_has_feature(CPU_FTR_ARCH_206) &&
		    (r & 0xff000)) {
			/* non-16MB large page, must be 64k */
			/* (masks depend on page size) */
			rb |= 0x1000;		/* page encoding in LP field */
			rb |= (va_low & 0x7f) << 16; /* 7b of VA in AVA/LP field */
			rb |= (va_low & 0xfe);	/* AVAL field (P7 doesn't seem to care) */
		}
	} else {
		/* 4kB page */
		rb |= (va_low & 0x7ff) << 12;	/* remaining 11b of VA */
	}
	rb |= (v >> 54) & 0x300;		/* B field */
	return rb;
}

static inline unsigned long hpte_page_size(unsigned long h, unsigned long l)
{
	/* only handle 4k, 64k and 16M pages for now */
	if (!(h & HPTE_V_LARGE))
		return 1ul << 12;		/* 4k page */
	if ((l & 0xf000) == 0x1000 && cpu_has_feature(CPU_FTR_ARCH_206))
		return 1ul << 16;		/* 64k page */
	if ((l & 0xff000) == 0)
		return 1ul << 24;		/* 16M page */
	return 0;				/* error */
}

static inline unsigned long hpte_rpn(unsigned long ptel, unsigned long psize)
{
	return ((ptel & HPTE_R_RPN) & ~(psize - 1)) >> PAGE_SHIFT;
}

static inline int hpte_cache_flags_ok(unsigned long ptel, unsigned long io_type)
{
	unsigned int wimg = ptel & HPTE_R_WIMG;

	/* Handle SAO */
	if (wimg == (HPTE_R_W | HPTE_R_I | HPTE_R_M) &&
	    cpu_has_feature(CPU_FTR_ARCH_206))
		wimg = HPTE_R_M;

	if (!io_type)
		return wimg == HPTE_R_M;

	return (wimg & (HPTE_R_W | HPTE_R_I)) == io_type;
}

/*
 * Lock and read a linux PTE.  If it's present and writable, atomically
 * set dirty and referenced bits and return the PTE, otherwise return 0.
 */
static inline pte_t kvmppc_read_update_linux_pte(pte_t *p)
{
	pte_t pte, tmp;

	/* wait until _PAGE_BUSY is clear then set it atomically */
	__asm__ __volatile__ (
		"1:	ldarx	%0,0,%3\n"
		"	andi.	%1,%0,%4\n"
		"	bne-	1b\n"
		"	ori	%1,%0,%4\n"
		"	stdcx.	%1,0,%3\n"
		"	bne-	1b"
		: "=&r" (pte), "=&r" (tmp), "=m" (*p)
		: "r" (p), "i" (_PAGE_BUSY)
		: "cc");

	if (pte_present(pte)) {
		pte = pte_mkyoung(pte);
		if (pte_write(pte))
			pte = pte_mkdirty(pte);
	}

	*p = pte;	/* clears _PAGE_BUSY */

	return pte;
}

/* Return HPTE cache control bits corresponding to Linux pte bits */
static inline unsigned long hpte_cache_bits(unsigned long pte_val)
{
#if _PAGE_NO_CACHE == HPTE_R_I && _PAGE_WRITETHRU == HPTE_R_W
	return pte_val & (HPTE_R_W | HPTE_R_I);
#else
	return ((pte_val & _PAGE_NO_CACHE) ? HPTE_R_I : 0) +
		((pte_val & _PAGE_WRITETHRU) ? HPTE_R_W : 0);
#endif
}

static inline bool hpte_read_permission(unsigned long pp, unsigned long key)
{
	if (key)
		return PP_RWRX <= pp && pp <= PP_RXRX;
	return 1;
}

static inline bool hpte_write_permission(unsigned long pp, unsigned long key)
{
	if (key)
		return pp == PP_RWRW;
	return pp <= PP_RWRW;
}

static inline int hpte_get_skey_perm(unsigned long hpte_r, unsigned long amr)
{
	unsigned long skey;

	skey = ((hpte_r & HPTE_R_KEY_HI) >> 57) |
		((hpte_r & HPTE_R_KEY_LO) >> 9);
	return (amr >> (62 - 2 * skey)) & 3;
}

static inline void lock_rmap(unsigned long *rmap)
{
	do {
		while (test_bit(KVMPPC_RMAP_LOCK_BIT, rmap))
			cpu_relax();
	} while (test_and_set_bit_lock(KVMPPC_RMAP_LOCK_BIT, rmap));
}

static inline void unlock_rmap(unsigned long *rmap)
{
	__clear_bit_unlock(KVMPPC_RMAP_LOCK_BIT, rmap);
}

static inline bool slot_is_aligned(struct kvm_memory_slot *memslot,
				   unsigned long pagesize)
{
	unsigned long mask = (pagesize >> PAGE_SHIFT) - 1;

	if (pagesize <= PAGE_SIZE)
		return 1;
	return !(memslot->base_gfn & mask) && !(memslot->npages & mask);
}

#endif /* __ASM_KVM_BOOK3S_64_H__ */
Commit	Line	Data
3ae07890 AG	1	/*
	2	* This program is free software; you can redistribute it and/or modify
	3	* it under the terms of the GNU General Public License, version 2, as
	4	* published by the Free Software Foundation.
	5	*
	6	* This program is distributed in the hope that it will be useful,
	7	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	8	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	9	* GNU General Public License for more details.
	10	*
	11	* You should have received a copy of the GNU General Public License
	12	* along with this program; if not, write to the Free Software
	13	* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
	14	*
	15	* Copyright SUSE Linux Products GmbH 2010
	16	*
	17	* Authors: Alexander Graf <agraf@suse.de>
	18	*/
	19
	20	#ifndef __ASM_KVM_BOOK3S_64_H__
	21	#define __ASM_KVM_BOOK3S_64_H__
	22
de56a948	23	#ifdef CONFIG_KVM_BOOK3S_PR
468a12c2	24	static inline struct kvmppc_book3s_shadow_vcpu svcpu_get(struct kvm_vcpu vcpu)
3ae07890	25	{
468a12c2	26	preempt_disable();
3ae07890 AG	27	return &get_paca()->shadow_vcpu;
3ae07890 AG	28	}
468a12c2 AG	29
	30	static inline void svcpu_put(struct kvmppc_book3s_shadow_vcpu *svcpu)
	31	{
	32	preempt_enable();
	33	}
de56a948	34	#endif
3ae07890	35
54738c09 DG	36	#define SPAPR_TCE_SHIFT 12
54738c09 DG	37
8936dda4 PM	38	#ifdef CONFIG_KVM_BOOK3S_64_HV
	39	/* For now use fixed-size 16MB page table */
	40	#define HPT_ORDER 24
	41	#define HPT_NPTEG (1ul << (HPT_ORDER - 7)) /* 128B per pteg */
	42	#define HPT_NPTE (HPT_NPTEG << 3) /* 8 PTEs per PTEG */
	43	#define HPT_HASH_MASK (HPT_NPTEG - 1)
	44	#endif
	45
697d3899 PM	46	#define VRMA_VSID 0x1ffffffUL /* 1TB VSID reserved for VRMA */
697d3899 PM	47
075295dd PM	48	/*
	49	* We use a lock bit in HPTE dword 0 to synchronize updates and
	50	* accesses to each HPTE, and another bit to indicate non-present
	51	* HPTEs.
	52	*/
	53	#define HPTE_V_HVLOCK 0x40UL
697d3899	54	#define HPTE_V_ABSENT 0x20UL
075295dd PM	55
	56	static inline long try_lock_hpte(unsigned long *hpte, unsigned long bits)
	57	{
	58	unsigned long tmp, old;
	59
	60	asm volatile(" ldarx %0,0,%2\n"
	61	" and. %1,%0,%3\n"
	62	" bne 2f\n"
	63	" ori %0,%0,%4\n"
	64	" stdcx. %0,0,%2\n"
	65	" beq+ 2f\n"
	66	" li %1,%3\n"
	67	"2: isync"
	68	: "=&r" (tmp), "=&r" (old)
	69	: "r" (hpte), "r" (bits), "i" (HPTE_V_HVLOCK)
	70	: "cc", "memory");
	71	return old == 0;
	72	}
	73
36cc66d6 AS	74	static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
	75	unsigned long pte_index)
	76	{
	77	unsigned long rb, va_low;
	78
	79	rb = (v & ~0x7fUL) << 16; /* AVA field */
	80	va_low = pte_index >> 3;
	81	if (v & HPTE_V_SECONDARY)
	82	va_low = ~va_low;
	83	/* xor vsid from AVA */
	84	if (!(v & HPTE_V_1TB_SEG))
	85	va_low ^= v >> 12;
	86	else
	87	va_low ^= v >> 24;
	88	va_low &= 0x7ff;
	89	if (v & HPTE_V_LARGE) {
	90	rb \|= 1; /* L field */
	91	if (cpu_has_feature(CPU_FTR_ARCH_206) &&
	92	(r & 0xff000)) {
	93	/* non-16MB large page, must be 64k */
	94	/* (masks depend on page size) */
	95	rb \|= 0x1000; /* page encoding in LP field */
	96	rb \|= (va_low & 0x7f) << 16; /* 7b of VA in AVA/LP field */
	97	rb \|= (va_low & 0xfe); /* AVAL field (P7 doesn't seem to care) */
	98	}
	99	} else {
	100	/* 4kB page */
	101	rb \|= (va_low & 0x7ff) << 12; /* remaining 11b of VA */
	102	}
	103	rb \|= (v >> 54) & 0x300; /* B field */
	104	return rb;
	105	}
	106
c77162de PM	107	static inline unsigned long hpte_page_size(unsigned long h, unsigned long l)
	108	{
	109	/* only handle 4k, 64k and 16M pages for now */
	110	if (!(h & HPTE_V_LARGE))
	111	return 1ul << 12; /* 4k page */
	112	if ((l & 0xf000) == 0x1000 && cpu_has_feature(CPU_FTR_ARCH_206))
	113	return 1ul << 16; /* 64k page */
	114	if ((l & 0xff000) == 0)
	115	return 1ul << 24; /* 16M page */
	116	return 0; /* error */
	117	}
	118
06ce2c63 PM	119	static inline unsigned long hpte_rpn(unsigned long ptel, unsigned long psize)
	120	{
	121	return ((ptel & HPTE_R_RPN) & ~(psize - 1)) >> PAGE_SHIFT;
	122	}
	123
9d0ef5ea PM	124	static inline int hpte_cache_flags_ok(unsigned long ptel, unsigned long io_type)
	125	{
	126	unsigned int wimg = ptel & HPTE_R_WIMG;
	127
	128	/* Handle SAO */
	129	if (wimg == (HPTE_R_W \| HPTE_R_I \| HPTE_R_M) &&
	130	cpu_has_feature(CPU_FTR_ARCH_206))
	131	wimg = HPTE_R_M;
	132
	133	if (!io_type)
	134	return wimg == HPTE_R_M;
	135
	136	return (wimg & (HPTE_R_W \| HPTE_R_I)) == io_type;
	137	}
	138
342d3db7 PM	139	/*
	140	* Lock and read a linux PTE. If it's present and writable, atomically
	141	* set dirty and referenced bits and return the PTE, otherwise return 0.
	142	*/
	143	static inline pte_t kvmppc_read_update_linux_pte(pte_t *p)
	144	{
	145	pte_t pte, tmp;
	146
	147	/* wait until _PAGE_BUSY is clear then set it atomically */
	148	__asm__ __volatile__ (
	149	"1: ldarx %0,0,%3\n"
	150	" andi. %1,%0,%4\n"
	151	" bne- 1b\n"
	152	" ori %1,%0,%4\n"
	153	" stdcx. %1,0,%3\n"
	154	" bne- 1b"
	155	: "=&r" (pte), "=&r" (tmp), "=m" (*p)
	156	: "r" (p), "i" (_PAGE_BUSY)
	157	: "cc");
	158
	159	if (pte_present(pte)) {
	160	pte = pte_mkyoung(pte);
	161	if (pte_write(pte))
	162	pte = pte_mkdirty(pte);
	163	}
	164
	165	p = pte; / clears _PAGE_BUSY */
	166
	167	return pte;
	168	}
	169
9d0ef5ea PM	170	/* Return HPTE cache control bits corresponding to Linux pte bits */
	171	static inline unsigned long hpte_cache_bits(unsigned long pte_val)
	172	{
	173	#if _PAGE_NO_CACHE == HPTE_R_I && _PAGE_WRITETHRU == HPTE_R_W
	174	return pte_val & (HPTE_R_W \| HPTE_R_I);
	175	#else
	176	return ((pte_val & _PAGE_NO_CACHE) ? HPTE_R_I : 0) +
	177	((pte_val & _PAGE_WRITETHRU) ? HPTE_R_W : 0);
	178	#endif
	179	}
	180
697d3899 PM	181	static inline bool hpte_read_permission(unsigned long pp, unsigned long key)
	182	{
	183	if (key)
	184	return PP_RWRX <= pp && pp <= PP_RXRX;
	185	return 1;
	186	}
	187
	188	static inline bool hpte_write_permission(unsigned long pp, unsigned long key)
	189	{
	190	if (key)
	191	return pp == PP_RWRW;
	192	return pp <= PP_RWRW;
	193	}
	194
	195	static inline int hpte_get_skey_perm(unsigned long hpte_r, unsigned long amr)
	196	{
	197	unsigned long skey;
	198
	199	skey = ((hpte_r & HPTE_R_KEY_HI) >> 57) \|
	200	((hpte_r & HPTE_R_KEY_LO) >> 9);
	201	return (amr >> (62 - 2 * skey)) & 3;
	202	}
	203
06ce2c63 PM	204	static inline void lock_rmap(unsigned long *rmap)
	205	{
	206	do {
	207	while (test_bit(KVMPPC_RMAP_LOCK_BIT, rmap))
	208	cpu_relax();
	209	} while (test_and_set_bit_lock(KVMPPC_RMAP_LOCK_BIT, rmap));
	210	}
	211
	212	static inline void unlock_rmap(unsigned long *rmap)
	213	{
	214	__clear_bit_unlock(KVMPPC_RMAP_LOCK_BIT, rmap);
	215	}
	216
da9d1d7f PM	217	static inline bool slot_is_aligned(struct kvm_memory_slot *memslot,
	218	unsigned long pagesize)
	219	{
	220	unsigned long mask = (pagesize >> PAGE_SHIFT) - 1;
	221
	222	if (pagesize <= PAGE_SIZE)
	223	return 1;
	224	return !(memslot->base_gfn & mask) && !(memslot->npages & mask);
	225	}
	226
3ae07890	227	#endif /* __ASM_KVM_BOOK3S_64_H__ */