projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * lppaca.h | |
| 3 | * Copyright (C) 2001 Mike Corrigan IBM Corporation | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify | |
| 6 | * it under the terms of the GNU General Public License as published by | |
| 7 | * the Free Software Foundation; either version 2 of the License, or | |
| 8 | * (at your option) any later version. | |
| 9 | * | |
| 10 | * This program is distributed in the hope that it will be useful, | |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | * GNU General Public License for more details. | |
| 14 | * | |
| 15 | * You should have received a copy of the GNU General Public License | |
| 16 | * along with this program; if not, write to the Free Software | |
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 18 | */ | |
| 8882a4da DG |
19 | #ifndef _ASM_POWERPC_LPPACA_H |
| 20 | #define _ASM_POWERPC_LPPACA_H | |
| 88ced031 | 21 | #ifdef __KERNEL__ |
| 1da177e4 | 22 | |
| 94491685 BH |
23 | /* These definitions relate to hypervisors that only exist when using |
| 24 | * a server type processor | |
| 25 | */ | |
| 26 | #ifdef CONFIG_PPC_BOOK3S | |
| 27 | ||
| 1da177e4 LT |
28 | //============================================================================= |
| 29 | // | |
| 30 | // This control block contains the data that is shared between the | |
| 31 | // hypervisor (PLIC) and the OS. | |
| 32 | // | |
| 33 | // | |
| 34 | //---------------------------------------------------------------------------- | |
| 2f6093c8 | 35 | #include <linux/cache.h> |
| 1da177e4 | 36 | #include <asm/types.h> |
| 2f6093c8 | 37 | #include <asm/mmu.h> |
| 1da177e4 | 38 | |
| 3356bb9f DG |
39 | /* The Hypervisor barfs if the lppaca crosses a page boundary. A 1k |
| 40 | * alignment is sufficient to prevent this */ | |
| c6b3feaf | 41 | struct lppaca { |
| 1da177e4 LT |
42 | //============================================================================= |
| 43 | // CACHE_LINE_1 0x0000 - 0x007F Contains read-only data | |
| 44 | // NOTE: The xDynXyz fields are fields that will be dynamically changed by | |
| 45 | // PLIC when preparing to bring a processor online or when dispatching a | |
| 46 | // virtual processor! | |
| 47 | //============================================================================= | |
| 48 | u32 desc; // Eye catcher 0xD397D781 x00-x03 | |
| 49 | u16 size; // Size of this struct x04-x05 | |
| 50 | u16 reserved1; // Reserved x06-x07 | |
| 51 | u16 reserved2:14; // Reserved x08-x09 | |
| 52 | u8 shared_proc:1; // Shared processor indicator ... | |
| 53 | u8 secondary_thread:1; // Secondary thread indicator ... | |
| 54 | volatile u8 dyn_proc_status:8; // Dynamic Status of this proc x0A-x0A | |
| 55 | u8 secondary_thread_count; // Secondary thread count x0B-x0B | |
| 56 | volatile u16 dyn_hv_phys_proc_index;// Dynamic HV Physical Proc Index0C-x0D | |
| 57 | volatile u16 dyn_hv_log_proc_index;// Dynamic HV Logical Proc Indexx0E-x0F | |
| 58 | u32 decr_val; // Value for Decr programming x10-x13 | |
| 59 | u32 pmc_val; // Value for PMC regs x14-x17 | |
| 60 | volatile u32 dyn_hw_node_id; // Dynamic Hardware Node id x18-x1B | |
| 61 | volatile u32 dyn_hw_proc_id; // Dynamic Hardware Proc Id x1C-x1F | |
| 62 | volatile u32 dyn_pir; // Dynamic ProcIdReg value x20-x23 | |
| 63 | u32 dsei_data; // DSEI data x24-x27 | |
| 64 | u64 sprg3; // SPRG3 value x28-x2F | |
| 65 | u8 reserved3[80]; // Reserved x30-x7F | |
| 66 | ||
| 67 | //============================================================================= | |
| 68 | // CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data | |
| 69 | //============================================================================= | |
| 70 | // This Dword contains a byte for each type of interrupt that can occur. | |
| 71 | // The IPI is a count while the others are just a binary 1 or 0. | |
| 72 | union { | |
| 73 | u64 any_int; | |
| 74 | struct { | |
| 75 | u16 reserved; // Reserved - cleared by #mpasmbl | |
| 76 | u8 xirr_int; // Indicates xXirrValue is valid or Immed IO | |
| 77 | u8 ipi_cnt; // IPI Count | |
| 78 | u8 decr_int; // DECR interrupt occurred | |
| 79 | u8 pdc_int; // PDC interrupt occurred | |
| 80 | u8 quantum_int; // Interrupt quantum reached | |
| 81 | u8 old_plic_deferred_ext_int; // Old PLIC has a deferred XIRR pending | |
| 82 | } fields; | |
| 83 | } int_dword; | |
| 84 | ||
| 85 | // Whenever any fields in this Dword are set then PLIC will defer the | |
| 86 | // processing of external interrupts. Note that PLIC will store the | |
| 87 | // XIRR directly into the xXirrValue field so that another XIRR will | |
| 88 | // not be presented until this one clears. The layout of the low | |
| 89 | // 4-bytes of this Dword is upto SLIC - PLIC just checks whether the | |
| 90 | // entire Dword is zero or not. A non-zero value in the low order | |
| 91 | // 2-bytes will result in SLIC being granted the highest thread | |
| 92 | // priority upon return. A 0 will return to SLIC as medium priority. | |
| 93 | u64 plic_defer_ints_area; // Entire Dword | |
| 94 | ||
| 95 | // Used to pass the real SRR0/1 from PLIC to SLIC as well as to | |
| 96 | // pass the target SRR0/1 from SLIC to PLIC on a SetAsrAndRfid. | |
| 97 | u64 saved_srr0; // Saved SRR0 x10-x17 | |
| 98 | u64 saved_srr1; // Saved SRR1 x18-x1F | |
| 99 | ||
| 100 | // Used to pass parms from the OS to PLIC for SetAsrAndRfid | |
| 101 | u64 saved_gpr3; // Saved GPR3 x20-x27 | |
| 102 | u64 saved_gpr4; // Saved GPR4 x28-x2F | |
| 103 | u64 saved_gpr5; // Saved GPR5 x30-x37 | |
| 104 | ||
| 098e8957 | 105 | u8 dtl_enable_mask; // Dispatch Trace Log mask x38-x38 |
| d8c391a5 | 106 | u8 donate_dedicated_cpu; // Donate dedicated CPU cycles x39-x39 |
| 1da177e4 LT |
107 | u8 fpregs_in_use; // FP regs in use x3A-x3A |
| 108 | u8 pmcregs_in_use; // PMC regs in use x3B-x3B | |
| 109 | volatile u32 saved_decr; // Saved Decr Value x3C-x3F | |
| 110 | volatile u64 emulated_time_base;// Emulated TB for this thread x40-x47 | |
| 111 | volatile u64 cur_plic_latency; // Unaccounted PLIC latency x48-x4F | |
| 112 | u64 tot_plic_latency; // Accumulated PLIC latency x50-x57 | |
| 113 | u64 wait_state_cycles; // Wait cycles for this proc x58-x5F | |
| 114 | u64 end_of_quantum; // TB at end of quantum x60-x67 | |
| 115 | u64 pdc_saved_sprg1; // Saved SPRG1 for PMC int x68-x6F | |
| 116 | u64 pdc_saved_srr0; // Saved SRR0 for PMC int x70-x77 | |
| 117 | volatile u32 virtual_decr; // Virtual DECR for shared procsx78-x7B | |
| 118 | u16 slb_count; // # of SLBs to maintain x7C-x7D | |
| 119 | u8 idle; // Indicate OS is idle x7E | |
| 233ccd0d | 120 | u8 vmxregs_in_use; // VMX registers in use x7F |
| 1da177e4 LT |
121 | |
| 122 | ||
| 123 | //============================================================================= | |
| 5cf13911 | 124 | // CACHE_LINE_3 0x0100 - 0x017F: This line is shared with other processors |
| 1da177e4 LT |
125 | //============================================================================= |
| 126 | // This is the yield_count. An "odd" value (low bit on) means that | |
| 127 | // the processor is yielded (either because of an OS yield or a PLIC | |
| 128 | // preempt). An even value implies that the processor is currently | |
| 129 | // executing. | |
| 130 | // NOTE: This value will ALWAYS be zero for dedicated processors and | |
| 131 | // will NEVER be zero for shared processors (ie, initialized to a 1). | |
| 132 | volatile u32 yield_count; // PLIC increments each dispatchx00-x03 | |
| 0559f0a7 | 133 | volatile u32 dispersion_count; // dispatch changed phys cpu x04-x07 |
| ffa5abbd BK |
134 | volatile u64 cmo_faults; // CMO page fault count x08-x0F |
| 135 | volatile u64 cmo_fault_time; // CMO page fault time x10-x17 | |
| 136 | u8 reserved7[104]; // Reserved x18-x7F | |
| 1da177e4 LT |
137 | |
| 138 | //============================================================================= | |
| 5cf13911 | 139 | // CACHE_LINE_4-5 0x0180 - 0x027F Contains PMC interrupt data |
| 1da177e4 | 140 | //============================================================================= |
| 40322783 | 141 | u32 page_ins; // CMO Hint - # page ins by OS x00-x03 |
| 098e8957 JK |
142 | u8 reserved8[148]; // Reserved x04-x97 |
| 143 | volatile u64 dtl_idx; // Dispatch Trace Log head idx x98-x9F | |
| 144 | u8 reserved9[96]; // Reserved xA0-xFF | |
| c6b3feaf | 145 | } __attribute__((__aligned__(0x400))); |
| 1da177e4 | 146 | |
| 3356bb9f DG |
147 | extern struct lppaca lppaca[]; |
| 148 | ||
| 2f6093c8 MN |
149 | /* |
| 150 | * SLB shadow buffer structure as defined in the PAPR. The save_area | |
| 151 | * contains adjacent ESID and VSID pairs for each shadowed SLB. The | |
| 152 | * ESID is stored in the lower 64bits, then the VSID. | |
| 153 | */ | |
| 154 | struct slb_shadow { | |
| 155 | u32 persistent; // Number of persistent SLBs x00-x03 | |
| 156 | u32 buffer_length; // Total shadow buffer length x04-x07 | |
| 157 | u64 reserved; // Alignment x08-x0f | |
| 158 | struct { | |
| 159 | u64 esid; | |
| 160 | u64 vsid; | |
| 161 | } save_area[SLB_NUM_BOLTED]; // x10-x40 | |
| 162 | } ____cacheline_aligned; | |
| 163 | ||
| 164 | extern struct slb_shadow slb_shadow[]; | |
| 165 | ||
| 94491685 | 166 | #endif /* CONFIG_PPC_BOOK3S */ |
| 88ced031 | 167 | #endif /* __KERNEL__ */ |
| 8882a4da | 168 | #endif /* _ASM_POWERPC_LPPACA_H */ |