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31202345 DG |
1 | #ifndef _ASM_POWERPC_MMU_8XX_H_ |
2 | #define _ASM_POWERPC_MMU_8XX_H_ | |
3 | /* | |
4 | * PPC8xx support | |
5 | */ | |
6 | ||
7 | /* Control/status registers for the MPC8xx. | |
8 | * A write operation to these registers causes serialized access. | |
9 | * During software tablewalk, the registers used perform mask/shift-add | |
10 | * operations when written/read. A TLB entry is created when the Mx_RPN | |
11 | * is written, and the contents of several registers are used to | |
12 | * create the entry. | |
13 | */ | |
14 | #define SPRN_MI_CTR 784 /* Instruction TLB control register */ | |
15 | #define MI_GPM 0x80000000 /* Set domain manager mode */ | |
16 | #define MI_PPM 0x40000000 /* Set subpage protection */ | |
17 | #define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ | |
18 | #define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */ | |
19 | #define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ | |
20 | #define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */ | |
21 | #define MI_RESETVAL 0x00000000 /* Value of register at reset */ | |
22 | ||
23 | /* These are the Ks and Kp from the PowerPC books. For proper operation, | |
24 | * Ks = 0, Kp = 1. | |
25 | */ | |
26 | #define SPRN_MI_AP 786 | |
27 | #define MI_Ks 0x80000000 /* Should not be set */ | |
28 | #define MI_Kp 0x40000000 /* Should always be set */ | |
29 | ||
30 | /* The effective page number register. When read, contains the information | |
31 | * about the last instruction TLB miss. When MI_RPN is written, bits in | |
32 | * this register are used to create the TLB entry. | |
33 | */ | |
34 | #define SPRN_MI_EPN 787 | |
35 | #define MI_EPNMASK 0xfffff000 /* Effective page number for entry */ | |
36 | #define MI_EVALID 0x00000200 /* Entry is valid */ | |
37 | #define MI_ASIDMASK 0x0000000f /* ASID match value */ | |
38 | /* Reset value is undefined */ | |
39 | ||
40 | /* A "level 1" or "segment" or whatever you want to call it register. | |
41 | * For the instruction TLB, it contains bits that get loaded into the | |
42 | * TLB entry when the MI_RPN is written. | |
43 | */ | |
44 | #define SPRN_MI_TWC 789 | |
45 | #define MI_APG 0x000001e0 /* Access protection group (0) */ | |
46 | #define MI_GUARDED 0x00000010 /* Guarded storage */ | |
47 | #define MI_PSMASK 0x0000000c /* Mask of page size bits */ | |
48 | #define MI_PS8MEG 0x0000000c /* 8M page size */ | |
49 | #define MI_PS512K 0x00000004 /* 512K page size */ | |
50 | #define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */ | |
51 | #define MI_SVALID 0x00000001 /* Segment entry is valid */ | |
52 | /* Reset value is undefined */ | |
53 | ||
54 | /* Real page number. Defined by the pte. Writing this register | |
55 | * causes a TLB entry to be created for the instruction TLB, using | |
56 | * additional information from the MI_EPN, and MI_TWC registers. | |
57 | */ | |
58 | #define SPRN_MI_RPN 790 | |
59 | ||
60 | /* Define an RPN value for mapping kernel memory to large virtual | |
61 | * pages for boot initialization. This has real page number of 0, | |
62 | * large page size, shared page, cache enabled, and valid. | |
63 | * Also mark all subpages valid and write access. | |
64 | */ | |
65 | #define MI_BOOTINIT 0x000001fd | |
66 | ||
67 | #define SPRN_MD_CTR 792 /* Data TLB control register */ | |
68 | #define MD_GPM 0x80000000 /* Set domain manager mode */ | |
69 | #define MD_PPM 0x40000000 /* Set subpage protection */ | |
70 | #define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ | |
71 | #define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */ | |
72 | #define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */ | |
73 | #define MD_TWAM 0x04000000 /* Use 4K page hardware assist */ | |
74 | #define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ | |
75 | #define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */ | |
76 | #define MD_RESETVAL 0x04000000 /* Value of register at reset */ | |
77 | ||
78 | #define SPRN_M_CASID 793 /* Address space ID (context) to match */ | |
79 | #define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */ | |
80 | ||
81 | ||
82 | /* These are the Ks and Kp from the PowerPC books. For proper operation, | |
83 | * Ks = 0, Kp = 1. | |
84 | */ | |
85 | #define SPRN_MD_AP 794 | |
86 | #define MD_Ks 0x80000000 /* Should not be set */ | |
87 | #define MD_Kp 0x40000000 /* Should always be set */ | |
88 | ||
89 | /* The effective page number register. When read, contains the information | |
90 | * about the last instruction TLB miss. When MD_RPN is written, bits in | |
91 | * this register are used to create the TLB entry. | |
92 | */ | |
93 | #define SPRN_MD_EPN 795 | |
94 | #define MD_EPNMASK 0xfffff000 /* Effective page number for entry */ | |
95 | #define MD_EVALID 0x00000200 /* Entry is valid */ | |
96 | #define MD_ASIDMASK 0x0000000f /* ASID match value */ | |
97 | /* Reset value is undefined */ | |
98 | ||
99 | /* The pointer to the base address of the first level page table. | |
100 | * During a software tablewalk, reading this register provides the address | |
101 | * of the entry associated with MD_EPN. | |
102 | */ | |
103 | #define SPRN_M_TWB 796 | |
104 | #define M_L1TB 0xfffff000 /* Level 1 table base address */ | |
105 | #define M_L1INDX 0x00000ffc /* Level 1 index, when read */ | |
106 | /* Reset value is undefined */ | |
107 | ||
108 | /* A "level 1" or "segment" or whatever you want to call it register. | |
109 | * For the data TLB, it contains bits that get loaded into the TLB entry | |
110 | * when the MD_RPN is written. It is also provides the hardware assist | |
111 | * for finding the PTE address during software tablewalk. | |
112 | */ | |
113 | #define SPRN_MD_TWC 797 | |
114 | #define MD_L2TB 0xfffff000 /* Level 2 table base address */ | |
115 | #define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */ | |
116 | #define MD_APG 0x000001e0 /* Access protection group (0) */ | |
117 | #define MD_GUARDED 0x00000010 /* Guarded storage */ | |
118 | #define MD_PSMASK 0x0000000c /* Mask of page size bits */ | |
119 | #define MD_PS8MEG 0x0000000c /* 8M page size */ | |
120 | #define MD_PS512K 0x00000004 /* 512K page size */ | |
121 | #define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */ | |
122 | #define MD_WT 0x00000002 /* Use writethrough page attribute */ | |
123 | #define MD_SVALID 0x00000001 /* Segment entry is valid */ | |
124 | /* Reset value is undefined */ | |
125 | ||
126 | ||
127 | /* Real page number. Defined by the pte. Writing this register | |
128 | * causes a TLB entry to be created for the data TLB, using | |
129 | * additional information from the MD_EPN, and MD_TWC registers. | |
130 | */ | |
131 | #define SPRN_MD_RPN 798 | |
132 | ||
133 | /* This is a temporary storage register that could be used to save | |
134 | * a processor working register during a tablewalk. | |
135 | */ | |
136 | #define SPRN_M_TW 799 | |
137 | ||
138 | #ifndef __ASSEMBLY__ | |
31202345 | 139 | typedef struct { |
2ca8cf73 BH |
140 | unsigned int id; |
141 | unsigned int active; | |
31202345 DG |
142 | unsigned long vdso_base; |
143 | } mm_context_t; | |
144 | #endif /* !__ASSEMBLY__ */ | |
145 | ||
25d21ad6 BH |
146 | #define mmu_virtual_psize MMU_PAGE_4K |
147 | #define mmu_linear_psize MMU_PAGE_8M | |
148 | ||
31202345 | 149 | #endif /* _ASM_POWERPC_MMU_8XX_H_ */ |