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d66c82ea KG |
1 | #ifndef _ASM_POWERPC_MMU_BOOK3E_H_ |
2 | #define _ASM_POWERPC_MMU_BOOK3E_H_ | |
67f74c9d | 3 | /* |
d66c82ea | 4 | * Freescale Book-E/Book-3e (ISA 2.06+) MMU support |
67f74c9d DG |
5 | */ |
6 | ||
d66c82ea KG |
7 | /* Book-3e defined page sizes */ |
8 | #define BOOK3E_PAGESZ_1K 0 | |
9 | #define BOOK3E_PAGESZ_2K 1 | |
10 | #define BOOK3E_PAGESZ_4K 2 | |
11 | #define BOOK3E_PAGESZ_8K 3 | |
12 | #define BOOK3E_PAGESZ_16K 4 | |
13 | #define BOOK3E_PAGESZ_32K 5 | |
14 | #define BOOK3E_PAGESZ_64K 6 | |
15 | #define BOOK3E_PAGESZ_128K 7 | |
16 | #define BOOK3E_PAGESZ_256K 8 | |
17 | #define BOOK3E_PAGESZ_512K 9 | |
18 | #define BOOK3E_PAGESZ_1M 10 | |
19 | #define BOOK3E_PAGESZ_2M 11 | |
20 | #define BOOK3E_PAGESZ_4M 12 | |
21 | #define BOOK3E_PAGESZ_8M 13 | |
22 | #define BOOK3E_PAGESZ_16M 14 | |
23 | #define BOOK3E_PAGESZ_32M 15 | |
24 | #define BOOK3E_PAGESZ_64M 16 | |
25 | #define BOOK3E_PAGESZ_128M 17 | |
26 | #define BOOK3E_PAGESZ_256M 18 | |
27 | #define BOOK3E_PAGESZ_512M 19 | |
28 | #define BOOK3E_PAGESZ_1GB 20 | |
29 | #define BOOK3E_PAGESZ_2GB 21 | |
30 | #define BOOK3E_PAGESZ_4GB 22 | |
31 | #define BOOK3E_PAGESZ_8GB 23 | |
32 | #define BOOK3E_PAGESZ_16GB 24 | |
33 | #define BOOK3E_PAGESZ_32GB 25 | |
34 | #define BOOK3E_PAGESZ_64GB 26 | |
35 | #define BOOK3E_PAGESZ_128GB 27 | |
36 | #define BOOK3E_PAGESZ_256GB 28 | |
37 | #define BOOK3E_PAGESZ_512GB 29 | |
38 | #define BOOK3E_PAGESZ_1TB 30 | |
39 | #define BOOK3E_PAGESZ_2TB 31 | |
67f74c9d | 40 | |
1fe1a210 BH |
41 | /* MAS registers bit definitions */ |
42 | ||
b51cbd41 SW |
43 | #define MAS0_TLBSEL(x) (((x) << 28) & 0x30000000) |
44 | #define MAS0_ESEL(x) (((x) << 16) & 0x0FFF0000) | |
1fe1a210 BH |
45 | #define MAS0_NV(x) ((x) & 0x00000FFF) |
46 | #define MAS0_HES 0x00004000 | |
47 | #define MAS0_WQ_ALLWAYS 0x00000000 | |
48 | #define MAS0_WQ_COND 0x00001000 | |
49 | #define MAS0_WQ_CLR_RSRV 0x00002000 | |
50 | ||
51 | #define MAS1_VALID 0x80000000 | |
52 | #define MAS1_IPROT 0x40000000 | |
b51cbd41 | 53 | #define MAS1_TID(x) (((x) << 16) & 0x3FFF0000) |
1fe1a210 BH |
54 | #define MAS1_IND 0x00002000 |
55 | #define MAS1_TS 0x00001000 | |
56 | #define MAS1_TSIZE_MASK 0x00000f80 | |
57 | #define MAS1_TSIZE_SHIFT 7 | |
b51cbd41 | 58 | #define MAS1_TSIZE(x) (((x) << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK) |
1fe1a210 BH |
59 | |
60 | #define MAS2_EPN 0xFFFFF000 | |
61 | #define MAS2_X0 0x00000040 | |
62 | #define MAS2_X1 0x00000020 | |
63 | #define MAS2_W 0x00000010 | |
64 | #define MAS2_I 0x00000008 | |
65 | #define MAS2_M 0x00000004 | |
66 | #define MAS2_G 0x00000002 | |
67 | #define MAS2_E 0x00000001 | |
d66c82ea | 68 | #define MAS2_EPN_MASK(size) (~0 << (size + 10)) |
b3898895 | 69 | #define MAS2_VAL(addr, size, flags) ((addr) & MAS2_EPN_MASK(size) | (flags)) |
67f74c9d | 70 | |
1fe1a210 BH |
71 | #define MAS3_RPN 0xFFFFF000 |
72 | #define MAS3_U0 0x00000200 | |
73 | #define MAS3_U1 0x00000100 | |
74 | #define MAS3_U2 0x00000080 | |
75 | #define MAS3_U3 0x00000040 | |
76 | #define MAS3_UX 0x00000020 | |
77 | #define MAS3_SX 0x00000010 | |
78 | #define MAS3_UW 0x00000008 | |
79 | #define MAS3_SW 0x00000004 | |
80 | #define MAS3_UR 0x00000002 | |
81 | #define MAS3_SR 0x00000001 | |
82 | #define MAS3_SPSIZE 0x0000003e | |
83 | #define MAS3_SPSIZE_SHIFT 1 | |
84 | ||
85 | #define MAS4_TLBSELD(x) MAS0_TLBSEL(x) | |
86 | #define MAS4_INDD 0x00008000 /* Default IND */ | |
87 | #define MAS4_TSIZED(x) MAS1_TSIZE(x) | |
88 | #define MAS4_X0D 0x00000040 | |
89 | #define MAS4_X1D 0x00000020 | |
90 | #define MAS4_WD 0x00000010 | |
91 | #define MAS4_ID 0x00000008 | |
92 | #define MAS4_MD 0x00000004 | |
93 | #define MAS4_GD 0x00000002 | |
94 | #define MAS4_ED 0x00000001 | |
95 | #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */ | |
96 | #define MAS4_WIMGED_SHIFT 0 | |
97 | #define MAS4_VLED MAS4_X1D /* Default VLE */ | |
98 | #define MAS4_ACMD 0x000000c0 /* Default ACM */ | |
99 | #define MAS4_ACMD_SHIFT 6 | |
100 | #define MAS4_TSIZED_MASK 0x00000f80 /* Default TSIZE */ | |
101 | #define MAS4_TSIZED_SHIFT 7 | |
102 | ||
103 | #define MAS6_SPID0 0x3FFF0000 | |
104 | #define MAS6_SPID1 0x00007FFE | |
105 | #define MAS6_ISIZE(x) MAS1_TSIZE(x) | |
106 | #define MAS6_SAS 0x00000001 | |
107 | #define MAS6_SPID MAS6_SPID0 | |
108 | #define MAS6_SIND 0x00000002 /* Indirect page */ | |
109 | #define MAS6_SIND_SHIFT 1 | |
110 | #define MAS6_SPID_MASK 0x3fff0000 | |
111 | #define MAS6_SPID_SHIFT 16 | |
112 | #define MAS6_ISIZE_MASK 0x00000f80 | |
113 | #define MAS6_ISIZE_SHIFT 7 | |
114 | ||
115 | #define MAS7_RPN 0xFFFFFFFF | |
116 | ||
988cf86d KG |
117 | /* Bit definitions for MMUCFG */ |
118 | #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */ | |
119 | #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */ | |
120 | #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */ | |
121 | #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */ | |
122 | #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */ | |
123 | #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */ | |
124 | #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */ | |
125 | #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */ | |
126 | #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */ | |
127 | ||
fc4bdb35 KG |
128 | /* Bit definitions for MMUCSR0 */ |
129 | #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */ | |
130 | #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */ | |
131 | #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */ | |
132 | #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */ | |
133 | #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \ | |
134 | MMUCSR0_TLB2FI | MMUCSR0_TLB3FI) | |
135 | #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */ | |
136 | #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */ | |
137 | #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */ | |
138 | #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */ | |
139 | ||
1fe1a210 BH |
140 | /* TLBnCFG encoding */ |
141 | #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */ | |
142 | #define TLBnCFG_HES 0x00002000 /* HW select supported */ | |
143 | #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */ | |
144 | #define TLBnCFG_GTWE 0x00010000 /* Guest can write */ | |
145 | #define TLBnCFG_IND 0x00020000 /* IND entries supported */ | |
146 | #define TLBnCFG_PT 0x00040000 /* Can load from page table */ | |
988cf86d KG |
147 | #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */ |
148 | #define TLBnCFG_MINSIZE_SHIFT 20 | |
149 | #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */ | |
150 | #define TLBnCFG_MAXSIZE_SHIFT 16 | |
1fe1a210 BH |
151 | #define TLBnCFG_ASSOC 0xff000000 /* Associativity */ |
152 | ||
153 | /* TLBnPS encoding */ | |
154 | #define TLBnPS_4K 0x00000004 | |
155 | #define TLBnPS_8K 0x00000008 | |
156 | #define TLBnPS_16K 0x00000010 | |
157 | #define TLBnPS_32K 0x00000020 | |
158 | #define TLBnPS_64K 0x00000040 | |
159 | #define TLBnPS_128K 0x00000080 | |
160 | #define TLBnPS_256K 0x00000100 | |
161 | #define TLBnPS_512K 0x00000200 | |
162 | #define TLBnPS_1M 0x00000400 | |
163 | #define TLBnPS_2M 0x00000800 | |
164 | #define TLBnPS_4M 0x00001000 | |
165 | #define TLBnPS_8M 0x00002000 | |
166 | #define TLBnPS_16M 0x00004000 | |
167 | #define TLBnPS_32M 0x00008000 | |
168 | #define TLBnPS_64M 0x00010000 | |
169 | #define TLBnPS_128M 0x00020000 | |
170 | #define TLBnPS_256M 0x00040000 | |
171 | #define TLBnPS_512M 0x00080000 | |
172 | #define TLBnPS_1G 0x00100000 | |
173 | #define TLBnPS_2G 0x00200000 | |
174 | #define TLBnPS_4G 0x00400000 | |
175 | #define TLBnPS_8G 0x00800000 | |
176 | #define TLBnPS_16G 0x01000000 | |
177 | #define TLBnPS_32G 0x02000000 | |
178 | #define TLBnPS_64G 0x04000000 | |
179 | #define TLBnPS_128G 0x08000000 | |
180 | #define TLBnPS_256G 0x10000000 | |
181 | ||
182 | /* tlbilx action encoding */ | |
183 | #define TLBILX_T_ALL 0 | |
184 | #define TLBILX_T_TID 1 | |
185 | #define TLBILX_T_FULLMATCH 3 | |
186 | #define TLBILX_T_CLASS0 4 | |
187 | #define TLBILX_T_CLASS1 5 | |
188 | #define TLBILX_T_CLASS2 6 | |
189 | #define TLBILX_T_CLASS3 7 | |
67f74c9d DG |
190 | |
191 | #ifndef __ASSEMBLY__ | |
192 | ||
87c656b4 LY |
193 | extern unsigned int tlbcam_index; |
194 | ||
67f74c9d | 195 | typedef struct { |
2ca8cf73 BH |
196 | unsigned int id; |
197 | unsigned int active; | |
198 | unsigned long vdso_base; | |
67f74c9d | 199 | } mm_context_t; |
57e2a99f BH |
200 | |
201 | /* Page size definitions, common between 32 and 64-bit | |
202 | * | |
203 | * shift : is the "PAGE_SHIFT" value for that page size | |
204 | * penc : is the pte encoding mask | |
205 | * | |
206 | */ | |
207 | struct mmu_psize_def | |
208 | { | |
209 | unsigned int shift; /* number of bits */ | |
210 | unsigned int enc; /* PTE encoding */ | |
f2b26c92 BH |
211 | unsigned int ind; /* Corresponding indirect page size shift */ |
212 | unsigned int flags; | |
213 | #define MMU_PAGE_SIZE_DIRECT 0x1 /* Supported as a direct size */ | |
214 | #define MMU_PAGE_SIZE_INDIRECT 0x2 /* Supported as an indirect size */ | |
57e2a99f BH |
215 | }; |
216 | extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; | |
217 | ||
218 | /* The page sizes use the same names as 64-bit hash but are | |
219 | * constants | |
220 | */ | |
221 | #if defined(CONFIG_PPC_4K_PAGES) | |
222 | #define mmu_virtual_psize MMU_PAGE_4K | |
223 | #elif defined(CONFIG_PPC_64K_PAGES) | |
224 | #define mmu_virtual_psize MMU_PAGE_64K | |
225 | #else | |
226 | #error Unsupported page size | |
227 | #endif | |
228 | ||
229 | extern int mmu_linear_psize; | |
32a74949 | 230 | extern int mmu_vmemmap_psize; |
57e2a99f | 231 | |
67f74c9d DG |
232 | #endif /* !__ASSEMBLY__ */ |
233 | ||
d66c82ea | 234 | #endif /* _ASM_POWERPC_MMU_BOOK3E_H_ */ |