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d66c82ea KG |
1 | #ifndef _ASM_POWERPC_MMU_BOOK3E_H_ |
2 | #define _ASM_POWERPC_MMU_BOOK3E_H_ | |
67f74c9d | 3 | /* |
d66c82ea | 4 | * Freescale Book-E/Book-3e (ISA 2.06+) MMU support |
67f74c9d DG |
5 | */ |
6 | ||
d66c82ea KG |
7 | /* Book-3e defined page sizes */ |
8 | #define BOOK3E_PAGESZ_1K 0 | |
9 | #define BOOK3E_PAGESZ_2K 1 | |
10 | #define BOOK3E_PAGESZ_4K 2 | |
11 | #define BOOK3E_PAGESZ_8K 3 | |
12 | #define BOOK3E_PAGESZ_16K 4 | |
13 | #define BOOK3E_PAGESZ_32K 5 | |
14 | #define BOOK3E_PAGESZ_64K 6 | |
15 | #define BOOK3E_PAGESZ_128K 7 | |
16 | #define BOOK3E_PAGESZ_256K 8 | |
17 | #define BOOK3E_PAGESZ_512K 9 | |
18 | #define BOOK3E_PAGESZ_1M 10 | |
19 | #define BOOK3E_PAGESZ_2M 11 | |
20 | #define BOOK3E_PAGESZ_4M 12 | |
21 | #define BOOK3E_PAGESZ_8M 13 | |
22 | #define BOOK3E_PAGESZ_16M 14 | |
23 | #define BOOK3E_PAGESZ_32M 15 | |
24 | #define BOOK3E_PAGESZ_64M 16 | |
25 | #define BOOK3E_PAGESZ_128M 17 | |
26 | #define BOOK3E_PAGESZ_256M 18 | |
27 | #define BOOK3E_PAGESZ_512M 19 | |
28 | #define BOOK3E_PAGESZ_1GB 20 | |
29 | #define BOOK3E_PAGESZ_2GB 21 | |
30 | #define BOOK3E_PAGESZ_4GB 22 | |
31 | #define BOOK3E_PAGESZ_8GB 23 | |
32 | #define BOOK3E_PAGESZ_16GB 24 | |
33 | #define BOOK3E_PAGESZ_32GB 25 | |
34 | #define BOOK3E_PAGESZ_64GB 26 | |
35 | #define BOOK3E_PAGESZ_128GB 27 | |
36 | #define BOOK3E_PAGESZ_256GB 28 | |
37 | #define BOOK3E_PAGESZ_512GB 29 | |
38 | #define BOOK3E_PAGESZ_1TB 30 | |
39 | #define BOOK3E_PAGESZ_2TB 31 | |
67f74c9d DG |
40 | |
41 | #define MAS0_TLBSEL(x) ((x << 28) & 0x30000000) | |
42 | #define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000) | |
43 | #define MAS0_NV(x) ((x) & 0x00000FFF) | |
44 | ||
45 | #define MAS1_VALID 0x80000000 | |
46 | #define MAS1_IPROT 0x40000000 | |
47 | #define MAS1_TID(x) ((x << 16) & 0x3FFF0000) | |
d66c82ea | 48 | #define MAS1_IND 0x00002000 |
67f74c9d | 49 | #define MAS1_TS 0x00001000 |
d66c82ea | 50 | #define MAS1_TSIZE(x) ((x << 7) & 0x00000F80) |
67f74c9d DG |
51 | |
52 | #define MAS2_EPN 0xFFFFF000 | |
53 | #define MAS2_X0 0x00000040 | |
54 | #define MAS2_X1 0x00000020 | |
55 | #define MAS2_W 0x00000010 | |
56 | #define MAS2_I 0x00000008 | |
57 | #define MAS2_M 0x00000004 | |
58 | #define MAS2_G 0x00000002 | |
59 | #define MAS2_E 0x00000001 | |
d66c82ea | 60 | #define MAS2_EPN_MASK(size) (~0 << (size + 10)) |
b3898895 | 61 | #define MAS2_VAL(addr, size, flags) ((addr) & MAS2_EPN_MASK(size) | (flags)) |
67f74c9d DG |
62 | |
63 | #define MAS3_RPN 0xFFFFF000 | |
64 | #define MAS3_U0 0x00000200 | |
65 | #define MAS3_U1 0x00000100 | |
66 | #define MAS3_U2 0x00000080 | |
67 | #define MAS3_U3 0x00000040 | |
68 | #define MAS3_UX 0x00000020 | |
69 | #define MAS3_SX 0x00000010 | |
70 | #define MAS3_UW 0x00000008 | |
71 | #define MAS3_SW 0x00000004 | |
72 | #define MAS3_UR 0x00000002 | |
73 | #define MAS3_SR 0x00000001 | |
74 | ||
75 | #define MAS4_TLBSELD(x) MAS0_TLBSEL(x) | |
d66c82ea | 76 | #define MAS4_INDD 0x00008000 |
67f74c9d DG |
77 | #define MAS4_TSIZED(x) MAS1_TSIZE(x) |
78 | #define MAS4_X0D 0x00000040 | |
79 | #define MAS4_X1D 0x00000020 | |
80 | #define MAS4_WD 0x00000010 | |
81 | #define MAS4_ID 0x00000008 | |
82 | #define MAS4_MD 0x00000004 | |
83 | #define MAS4_GD 0x00000002 | |
84 | #define MAS4_ED 0x00000001 | |
85 | ||
86 | #define MAS6_SPID0 0x3FFF0000 | |
87 | #define MAS6_SPID1 0x00007FFE | |
d66c82ea | 88 | #define MAS6_ISIZE(x) MAS1_TSIZE(x) |
67f74c9d DG |
89 | #define MAS6_SAS 0x00000001 |
90 | #define MAS6_SPID MAS6_SPID0 | |
91 | ||
92 | #define MAS7_RPN 0xFFFFFFFF | |
93 | ||
94 | #ifndef __ASSEMBLY__ | |
95 | ||
67f74c9d | 96 | typedef struct { |
2ca8cf73 BH |
97 | unsigned int id; |
98 | unsigned int active; | |
99 | unsigned long vdso_base; | |
67f74c9d DG |
100 | } mm_context_t; |
101 | #endif /* !__ASSEMBLY__ */ | |
102 | ||
d66c82ea | 103 | #endif /* _ASM_POWERPC_MMU_BOOK3E_H_ */ |