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8d2169e8 DG |
1 | #ifndef _ASM_POWERPC_MMU_HASH64_H_ |
2 | #define _ASM_POWERPC_MMU_HASH64_H_ | |
3 | /* | |
4 | * PowerPC64 memory management structures | |
5 | * | |
6 | * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com> | |
7 | * PPC64 rework. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | */ | |
14 | ||
15 | #include <asm/asm-compat.h> | |
16 | #include <asm/page.h> | |
891121e6 | 17 | #include <asm/bug.h> |
8d2169e8 | 18 | |
78f1dbde AK |
19 | /* |
20 | * This is necessary to get the definition of PGTABLE_RANGE which we | |
21 | * need for various slices related matters. Note that this isn't the | |
22 | * complete pgtable.h but only a portion of it. | |
23 | */ | |
3dfcb315 | 24 | #include <asm/book3s/64/pgtable.h> |
cf9427b8 | 25 | #include <asm/bug.h> |
dad6f37c | 26 | #include <asm/processor.h> |
78f1dbde | 27 | |
8d2169e8 DG |
28 | /* |
29 | * SLB | |
30 | */ | |
31 | ||
32 | #define SLB_NUM_BOLTED 3 | |
33 | #define SLB_CACHE_ENTRIES 8 | |
46db2f86 | 34 | #define SLB_MIN_SIZE 32 |
8d2169e8 DG |
35 | |
36 | /* Bits in the SLB ESID word */ | |
37 | #define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */ | |
38 | ||
39 | /* Bits in the SLB VSID word */ | |
40 | #define SLB_VSID_SHIFT 12 | |
1189be65 PM |
41 | #define SLB_VSID_SHIFT_1T 24 |
42 | #define SLB_VSID_SSIZE_SHIFT 62 | |
8d2169e8 DG |
43 | #define SLB_VSID_B ASM_CONST(0xc000000000000000) |
44 | #define SLB_VSID_B_256M ASM_CONST(0x0000000000000000) | |
45 | #define SLB_VSID_B_1T ASM_CONST(0x4000000000000000) | |
46 | #define SLB_VSID_KS ASM_CONST(0x0000000000000800) | |
47 | #define SLB_VSID_KP ASM_CONST(0x0000000000000400) | |
48 | #define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */ | |
49 | #define SLB_VSID_L ASM_CONST(0x0000000000000100) | |
50 | #define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */ | |
51 | #define SLB_VSID_LP ASM_CONST(0x0000000000000030) | |
52 | #define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000) | |
53 | #define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010) | |
54 | #define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020) | |
55 | #define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030) | |
56 | #define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP) | |
57 | ||
58 | #define SLB_VSID_KERNEL (SLB_VSID_KP) | |
59 | #define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C) | |
60 | ||
61 | #define SLBIE_C (0x08000000) | |
1189be65 | 62 | #define SLBIE_SSIZE_SHIFT 25 |
8d2169e8 DG |
63 | |
64 | /* | |
65 | * Hash table | |
66 | */ | |
67 | ||
68 | #define HPTES_PER_GROUP 8 | |
69 | ||
2454c7e9 | 70 | #define HPTE_V_SSIZE_SHIFT 62 |
8d2169e8 | 71 | #define HPTE_V_AVPN_SHIFT 7 |
2454c7e9 | 72 | #define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80) |
8d2169e8 | 73 | #define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT) |
91bbbe22 | 74 | #define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80UL)) |
8d2169e8 DG |
75 | #define HPTE_V_BOLTED ASM_CONST(0x0000000000000010) |
76 | #define HPTE_V_LOCK ASM_CONST(0x0000000000000008) | |
77 | #define HPTE_V_LARGE ASM_CONST(0x0000000000000004) | |
78 | #define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002) | |
79 | #define HPTE_V_VALID ASM_CONST(0x0000000000000001) | |
80 | ||
81 | #define HPTE_R_PP0 ASM_CONST(0x8000000000000000) | |
82 | #define HPTE_R_TS ASM_CONST(0x4000000000000000) | |
de56a948 | 83 | #define HPTE_R_KEY_HI ASM_CONST(0x3000000000000000) |
8d2169e8 | 84 | #define HPTE_R_RPN_SHIFT 12 |
de56a948 | 85 | #define HPTE_R_RPN ASM_CONST(0x0ffffffffffff000) |
8d2169e8 DG |
86 | #define HPTE_R_PP ASM_CONST(0x0000000000000003) |
87 | #define HPTE_R_N ASM_CONST(0x0000000000000004) | |
de56a948 PM |
88 | #define HPTE_R_G ASM_CONST(0x0000000000000008) |
89 | #define HPTE_R_M ASM_CONST(0x0000000000000010) | |
90 | #define HPTE_R_I ASM_CONST(0x0000000000000020) | |
91 | #define HPTE_R_W ASM_CONST(0x0000000000000040) | |
92 | #define HPTE_R_WIMG ASM_CONST(0x0000000000000078) | |
8d2169e8 DG |
93 | #define HPTE_R_C ASM_CONST(0x0000000000000080) |
94 | #define HPTE_R_R ASM_CONST(0x0000000000000100) | |
de56a948 | 95 | #define HPTE_R_KEY_LO ASM_CONST(0x0000000000000e00) |
8d2169e8 | 96 | |
b7abc5c5 SS |
97 | #define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000) |
98 | #define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff000000) | |
99 | ||
8d2169e8 | 100 | /* Values for PP (assumes Ks=0, Kp=1) */ |
8d2169e8 DG |
101 | #define PP_RWXX 0 /* Supervisor read/write, User none */ |
102 | #define PP_RWRX 1 /* Supervisor read/write, User read */ | |
103 | #define PP_RWRW 2 /* Supervisor read/write, User read/write */ | |
104 | #define PP_RXRX 3 /* Supervisor read, User read */ | |
697d3899 | 105 | #define PP_RXXX (HPTE_R_PP0 | 2) /* Supervisor read, user none */ |
8d2169e8 | 106 | |
b4072df4 PM |
107 | /* Fields for tlbiel instruction in architecture 2.06 */ |
108 | #define TLBIEL_INVAL_SEL_MASK 0xc00 /* invalidation selector */ | |
109 | #define TLBIEL_INVAL_PAGE 0x000 /* invalidate a single page */ | |
110 | #define TLBIEL_INVAL_SET_LPID 0x800 /* invalidate a set for current LPID */ | |
111 | #define TLBIEL_INVAL_SET 0xc00 /* invalidate a set for all LPIDs */ | |
112 | #define TLBIEL_INVAL_SET_MASK 0xfff000 /* set number to inval. */ | |
113 | #define TLBIEL_INVAL_SET_SHIFT 12 | |
114 | ||
115 | #define POWER7_TLB_SETS 128 /* # sets in POWER7 TLB */ | |
45706bb5 | 116 | #define POWER8_TLB_SETS 512 /* # sets in POWER8 TLB */ |
b4072df4 | 117 | |
8d2169e8 DG |
118 | #ifndef __ASSEMBLY__ |
119 | ||
8e561e7e | 120 | struct hash_pte { |
12f04f2b AB |
121 | __be64 v; |
122 | __be64 r; | |
8e561e7e | 123 | }; |
8d2169e8 | 124 | |
8e561e7e | 125 | extern struct hash_pte *htab_address; |
8d2169e8 DG |
126 | extern unsigned long htab_size_bytes; |
127 | extern unsigned long htab_hash_mask; | |
128 | ||
129 | /* | |
130 | * Page size definition | |
131 | * | |
132 | * shift : is the "PAGE_SHIFT" value for that page size | |
133 | * sllp : is a bit mask with the value of SLB L || LP to be or'ed | |
134 | * directly to a slbmte "vsid" value | |
135 | * penc : is the HPTE encoding mask for the "LP" field: | |
136 | * | |
137 | */ | |
138 | struct mmu_psize_def | |
139 | { | |
140 | unsigned int shift; /* number of bits */ | |
b1022fbd | 141 | int penc[MMU_PAGE_COUNT]; /* HPTE encoding */ |
8d2169e8 DG |
142 | unsigned int tlbiel; /* tlbiel supported for that page size */ |
143 | unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */ | |
144 | unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */ | |
145 | }; | |
cf9427b8 AK |
146 | extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; |
147 | ||
148 | static inline int shift_to_mmu_psize(unsigned int shift) | |
149 | { | |
150 | int psize; | |
151 | ||
152 | for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) | |
153 | if (mmu_psize_defs[psize].shift == shift) | |
154 | return psize; | |
155 | return -1; | |
156 | } | |
157 | ||
158 | static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize) | |
159 | { | |
160 | if (mmu_psize_defs[mmu_psize].shift) | |
161 | return mmu_psize_defs[mmu_psize].shift; | |
162 | BUG(); | |
163 | } | |
8d2169e8 DG |
164 | |
165 | #endif /* __ASSEMBLY__ */ | |
166 | ||
2454c7e9 PM |
167 | /* |
168 | * Segment sizes. | |
169 | * These are the values used by hardware in the B field of | |
170 | * SLB entries and the first dword of MMU hashtable entries. | |
171 | * The B field is 2 bits; the values 2 and 3 are unused and reserved. | |
172 | */ | |
173 | #define MMU_SEGSIZE_256M 0 | |
174 | #define MMU_SEGSIZE_1T 1 | |
175 | ||
5524a27d AK |
176 | /* |
177 | * encode page number shift. | |
178 | * in order to fit the 78 bit va in a 64 bit variable we shift the va by | |
179 | * 12 bits. This enable us to address upto 76 bit va. | |
180 | * For hpt hash from a va we can ignore the page size bits of va and for | |
181 | * hpte encoding we ignore up to 23 bits of va. So ignoring lower 12 bits ensure | |
182 | * we work in all cases including 4k page size. | |
183 | */ | |
184 | #define VPN_SHIFT 12 | |
1189be65 | 185 | |
b1022fbd AK |
186 | /* |
187 | * HPTE Large Page (LP) details | |
188 | */ | |
189 | #define LP_SHIFT 12 | |
190 | #define LP_BITS 8 | |
191 | #define LP_MASK(i) ((0xFF >> (i)) << LP_SHIFT) | |
192 | ||
8d2169e8 DG |
193 | #ifndef __ASSEMBLY__ |
194 | ||
73d16a6e IM |
195 | static inline int slb_vsid_shift(int ssize) |
196 | { | |
197 | if (ssize == MMU_SEGSIZE_256M) | |
198 | return SLB_VSID_SHIFT; | |
199 | return SLB_VSID_SHIFT_1T; | |
200 | } | |
201 | ||
5524a27d AK |
202 | static inline int segment_shift(int ssize) |
203 | { | |
204 | if (ssize == MMU_SEGSIZE_256M) | |
205 | return SID_SHIFT; | |
206 | return SID_SHIFT_1T; | |
207 | } | |
208 | ||
8d2169e8 | 209 | /* |
1189be65 | 210 | * The current system page and segment sizes |
8d2169e8 | 211 | */ |
8d2169e8 DG |
212 | extern int mmu_linear_psize; |
213 | extern int mmu_virtual_psize; | |
214 | extern int mmu_vmalloc_psize; | |
cec08e7a | 215 | extern int mmu_vmemmap_psize; |
8d2169e8 | 216 | extern int mmu_io_psize; |
1189be65 PM |
217 | extern int mmu_kernel_ssize; |
218 | extern int mmu_highuser_ssize; | |
584f8b71 | 219 | extern u16 mmu_slb_size; |
572fb578 | 220 | extern unsigned long tce_alloc_start, tce_alloc_end; |
8d2169e8 DG |
221 | |
222 | /* | |
223 | * If the processor supports 64k normal pages but not 64k cache | |
224 | * inhibited pages, we have to be prepared to switch processes | |
225 | * to use 4k pages when they create cache-inhibited mappings. | |
226 | * If this is the case, mmu_ci_restrictions will be set to 1. | |
227 | */ | |
228 | extern int mmu_ci_restrictions; | |
229 | ||
5524a27d AK |
230 | /* |
231 | * This computes the AVPN and B fields of the first dword of a HPTE, | |
232 | * for use when we want to match an existing PTE. The bottom 7 bits | |
233 | * of the returned value are zero. | |
234 | */ | |
235 | static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize, | |
236 | int ssize) | |
237 | { | |
238 | unsigned long v; | |
239 | /* | |
240 | * The AVA field omits the low-order 23 bits of the 78 bits VA. | |
241 | * These bits are not needed in the PTE, because the | |
242 | * low-order b of these bits are part of the byte offset | |
243 | * into the virtual page and, if b < 23, the high-order | |
244 | * 23-b of these bits are always used in selecting the | |
245 | * PTEGs to be searched | |
246 | */ | |
247 | v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm); | |
248 | v <<= HPTE_V_AVPN_SHIFT; | |
249 | v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT; | |
250 | return v; | |
251 | } | |
252 | ||
8d2169e8 DG |
253 | /* |
254 | * This function sets the AVPN and L fields of the HPTE appropriately | |
b1022fbd | 255 | * using the base page size and actual page size. |
8d2169e8 | 256 | */ |
b1022fbd AK |
257 | static inline unsigned long hpte_encode_v(unsigned long vpn, int base_psize, |
258 | int actual_psize, int ssize) | |
8d2169e8 | 259 | { |
1189be65 | 260 | unsigned long v; |
b1022fbd AK |
261 | v = hpte_encode_avpn(vpn, base_psize, ssize); |
262 | if (actual_psize != MMU_PAGE_4K) | |
8d2169e8 DG |
263 | v |= HPTE_V_LARGE; |
264 | return v; | |
265 | } | |
266 | ||
267 | /* | |
268 | * This function sets the ARPN, and LP fields of the HPTE appropriately | |
269 | * for the page size. We assume the pa is already "clean" that is properly | |
270 | * aligned for the requested page size | |
271 | */ | |
b1022fbd AK |
272 | static inline unsigned long hpte_encode_r(unsigned long pa, int base_psize, |
273 | int actual_psize) | |
8d2169e8 | 274 | { |
8d2169e8 | 275 | /* A 4K page needs no special encoding */ |
b1022fbd | 276 | if (actual_psize == MMU_PAGE_4K) |
8d2169e8 DG |
277 | return pa & HPTE_R_RPN; |
278 | else { | |
b1022fbd AK |
279 | unsigned int penc = mmu_psize_defs[base_psize].penc[actual_psize]; |
280 | unsigned int shift = mmu_psize_defs[actual_psize].shift; | |
281 | return (pa & ~((1ul << shift) - 1)) | (penc << LP_SHIFT); | |
8d2169e8 | 282 | } |
8d2169e8 DG |
283 | } |
284 | ||
285 | /* | |
5524a27d | 286 | * Build a VPN_SHIFT bit shifted va given VSID, EA and segment size. |
8d2169e8 | 287 | */ |
5524a27d AK |
288 | static inline unsigned long hpt_vpn(unsigned long ea, |
289 | unsigned long vsid, int ssize) | |
1189be65 | 290 | { |
5524a27d AK |
291 | unsigned long mask; |
292 | int s_shift = segment_shift(ssize); | |
293 | ||
294 | mask = (1ul << (s_shift - VPN_SHIFT)) - 1; | |
295 | return (vsid << (s_shift - VPN_SHIFT)) | ((ea >> VPN_SHIFT) & mask); | |
1189be65 | 296 | } |
8d2169e8 | 297 | |
1189be65 PM |
298 | /* |
299 | * This hashes a virtual address | |
300 | */ | |
5524a27d AK |
301 | static inline unsigned long hpt_hash(unsigned long vpn, |
302 | unsigned int shift, int ssize) | |
8d2169e8 | 303 | { |
5524a27d | 304 | int mask; |
1189be65 PM |
305 | unsigned long hash, vsid; |
306 | ||
5524a27d | 307 | /* VPN_SHIFT can be atmost 12 */ |
1189be65 | 308 | if (ssize == MMU_SEGSIZE_256M) { |
5524a27d AK |
309 | mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1; |
310 | hash = (vpn >> (SID_SHIFT - VPN_SHIFT)) ^ | |
311 | ((vpn & mask) >> (shift - VPN_SHIFT)); | |
1189be65 | 312 | } else { |
5524a27d AK |
313 | mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1; |
314 | vsid = vpn >> (SID_SHIFT_1T - VPN_SHIFT); | |
315 | hash = vsid ^ (vsid << 25) ^ | |
316 | ((vpn & mask) >> (shift - VPN_SHIFT)) ; | |
1189be65 PM |
317 | } |
318 | return hash & 0x7fffffffffUL; | |
8d2169e8 DG |
319 | } |
320 | ||
aefa5688 AK |
321 | #define HPTE_LOCAL_UPDATE 0x1 |
322 | #define HPTE_NOHPTE_UPDATE 0x2 | |
323 | ||
8d2169e8 DG |
324 | extern int __hash_page_4K(unsigned long ea, unsigned long access, |
325 | unsigned long vsid, pte_t *ptep, unsigned long trap, | |
aefa5688 | 326 | unsigned long flags, int ssize, int subpage_prot); |
8d2169e8 DG |
327 | extern int __hash_page_64K(unsigned long ea, unsigned long access, |
328 | unsigned long vsid, pte_t *ptep, unsigned long trap, | |
aefa5688 | 329 | unsigned long flags, int ssize); |
8d2169e8 | 330 | struct mm_struct; |
0895ecda | 331 | unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap); |
aefa5688 AK |
332 | extern int hash_page_mm(struct mm_struct *mm, unsigned long ea, |
333 | unsigned long access, unsigned long trap, | |
334 | unsigned long flags); | |
335 | extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap, | |
336 | unsigned long dsisr); | |
a4fe3ce7 | 337 | int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid, |
aefa5688 AK |
338 | pte_t *ptep, unsigned long trap, unsigned long flags, |
339 | int ssize, unsigned int shift, unsigned int mmu_psize); | |
6d492ecc AK |
340 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
341 | extern int __hash_page_thp(unsigned long ea, unsigned long access, | |
342 | unsigned long vsid, pmd_t *pmdp, unsigned long trap, | |
aefa5688 | 343 | unsigned long flags, int ssize, unsigned int psize); |
6d492ecc AK |
344 | #else |
345 | static inline int __hash_page_thp(unsigned long ea, unsigned long access, | |
346 | unsigned long vsid, pmd_t *pmdp, | |
aefa5688 | 347 | unsigned long trap, unsigned long flags, |
6d492ecc AK |
348 | int ssize, unsigned int psize) |
349 | { | |
350 | BUG(); | |
ff1e7683 | 351 | return -1; |
6d492ecc AK |
352 | } |
353 | #endif | |
4b8692c0 BH |
354 | extern void hash_failure_debug(unsigned long ea, unsigned long access, |
355 | unsigned long vsid, unsigned long trap, | |
d8139ebf AK |
356 | int ssize, int psize, int lpsize, |
357 | unsigned long pte); | |
8d2169e8 | 358 | extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend, |
bc033b63 | 359 | unsigned long pstart, unsigned long prot, |
1189be65 | 360 | int psize, int ssize); |
f6026df1 AB |
361 | int htab_remove_mapping(unsigned long vstart, unsigned long vend, |
362 | int psize, int ssize); | |
41151e77 | 363 | extern void add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages); |
fa28237c | 364 | extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr); |
8d2169e8 | 365 | |
8d2169e8 DG |
366 | extern void hpte_init_native(void); |
367 | extern void hpte_init_lpar(void); | |
8d2169e8 | 368 | extern void hpte_init_beat(void); |
7f2c8577 | 369 | extern void hpte_init_beat_v3(void); |
8d2169e8 | 370 | |
8d2169e8 DG |
371 | extern void slb_initialize(void); |
372 | extern void slb_flush_and_rebolt(void); | |
8d2169e8 | 373 | |
67439b76 | 374 | extern void slb_vmalloc_update(void); |
46db2f86 | 375 | extern void slb_set_size(u16 size); |
8d2169e8 DG |
376 | #endif /* __ASSEMBLY__ */ |
377 | ||
378 | /* | |
f033d659 | 379 | * VSID allocation (256MB segment) |
8d2169e8 | 380 | * |
c60ac569 AK |
381 | * We first generate a 37-bit "proto-VSID". Proto-VSIDs are generated |
382 | * from mmu context id and effective segment id of the address. | |
8d2169e8 | 383 | * |
c60ac569 AK |
384 | * For user processes max context id is limited to ((1ul << 19) - 5) |
385 | * for kernel space, we use the top 4 context ids to map address as below | |
386 | * NOTE: each context only support 64TB now. | |
387 | * 0x7fffc - [ 0xc000000000000000 - 0xc0003fffffffffff ] | |
388 | * 0x7fffd - [ 0xd000000000000000 - 0xd0003fffffffffff ] | |
389 | * 0x7fffe - [ 0xe000000000000000 - 0xe0003fffffffffff ] | |
390 | * 0x7ffff - [ 0xf000000000000000 - 0xf0003fffffffffff ] | |
8d2169e8 DG |
391 | * |
392 | * The proto-VSIDs are then scrambled into real VSIDs with the | |
393 | * multiplicative hash: | |
394 | * | |
395 | * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS | |
8d2169e8 | 396 | * |
f033d659 | 397 | * VSID_MULTIPLIER is prime, so in particular it is |
8d2169e8 DG |
398 | * co-prime to VSID_MODULUS, making this a 1:1 scrambling function. |
399 | * Because the modulus is 2^n-1 we can compute it efficiently without | |
c60ac569 AK |
400 | * a divide or extra multiply (see below). The scramble function gives |
401 | * robust scattering in the hash table (at least based on some initial | |
402 | * results). | |
8d2169e8 | 403 | * |
c60ac569 AK |
404 | * We also consider VSID 0 special. We use VSID 0 for slb entries mapping |
405 | * bad address. This enables us to consolidate bad address handling in | |
406 | * hash_page. | |
8d2169e8 | 407 | * |
c60ac569 AK |
408 | * We also need to avoid the last segment of the last context, because that |
409 | * would give a protovsid of 0x1fffffffff. That will result in a VSID 0 | |
410 | * because of the modulo operation in vsid scramble. But the vmemmap | |
411 | * (which is what uses region 0xf) will never be close to 64TB in size | |
412 | * (it's 56 bytes per page of system memory). | |
8d2169e8 | 413 | */ |
8d2169e8 | 414 | |
e39d1a47 | 415 | #define CONTEXT_BITS 19 |
af81d787 AK |
416 | #define ESID_BITS 18 |
417 | #define ESID_BITS_1T 6 | |
e39d1a47 | 418 | |
c60ac569 AK |
419 | /* |
420 | * 256MB segment | |
af81d787 | 421 | * The proto-VSID space has 2^(CONTEX_BITS + ESID_BITS) - 1 segments |
c60ac569 AK |
422 | * available for user + kernel mapping. The top 4 contexts are used for |
423 | * kernel mapping. Each segment contains 2^28 bytes. Each | |
424 | * context maps 2^46 bytes (64TB) so we can support 2^19-1 contexts | |
425 | * (19 == 37 + 28 - 46). | |
426 | */ | |
427 | #define MAX_USER_CONTEXT ((ASM_CONST(1) << CONTEXT_BITS) - 5) | |
428 | ||
048ee099 AK |
429 | /* |
430 | * This should be computed such that protovosid * vsid_mulitplier | |
431 | * doesn't overflow 64 bits. It should also be co-prime to vsid_modulus | |
432 | */ | |
433 | #define VSID_MULTIPLIER_256M ASM_CONST(12538073) /* 24-bit prime */ | |
af81d787 | 434 | #define VSID_BITS_256M (CONTEXT_BITS + ESID_BITS) |
1189be65 | 435 | #define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1) |
8d2169e8 | 436 | |
1189be65 | 437 | #define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */ |
af81d787 | 438 | #define VSID_BITS_1T (CONTEXT_BITS + ESID_BITS_1T) |
1189be65 PM |
439 | #define VSID_MODULUS_1T ((1UL<<VSID_BITS_1T)-1) |
440 | ||
8d2169e8 | 441 | |
af81d787 | 442 | #define USER_VSID_RANGE (1UL << (ESID_BITS + SID_SHIFT)) |
8d2169e8 DG |
443 | |
444 | /* | |
445 | * This macro generates asm code to compute the VSID scramble | |
446 | * function. Used in slb_allocate() and do_stab_bolted. The function | |
447 | * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS | |
448 | * | |
449 | * rt = register continaing the proto-VSID and into which the | |
450 | * VSID will be stored | |
451 | * rx = scratch register (clobbered) | |
452 | * | |
453 | * - rt and rx must be different registers | |
1189be65 | 454 | * - The answer will end up in the low VSID_BITS bits of rt. The higher |
8d2169e8 DG |
455 | * bits may contain other garbage, so you may need to mask the |
456 | * result. | |
457 | */ | |
1189be65 PM |
458 | #define ASM_VSID_SCRAMBLE(rt, rx, size) \ |
459 | lis rx,VSID_MULTIPLIER_##size@h; \ | |
460 | ori rx,rx,VSID_MULTIPLIER_##size@l; \ | |
8d2169e8 DG |
461 | mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \ |
462 | \ | |
1189be65 PM |
463 | srdi rx,rt,VSID_BITS_##size; \ |
464 | clrldi rt,rt,(64-VSID_BITS_##size); \ | |
8d2169e8 | 465 | add rt,rt,rx; /* add high and low bits */ \ |
c60ac569 AK |
466 | /* NOTE: explanation based on VSID_BITS_##size = 36 \ |
467 | * Now, r3 == VSID (mod 2^36-1), and lies between 0 and \ | |
8d2169e8 DG |
468 | * 2^36-1+2^28-1. That in particular means that if r3 >= \ |
469 | * 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \ | |
470 | * the bit clear, r3 already has the answer we want, if it \ | |
471 | * doesn't, the answer is the low 36 bits of r3+1. So in all \ | |
472 | * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\ | |
473 | addi rx,rt,1; \ | |
1189be65 | 474 | srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \ |
8d2169e8 DG |
475 | add rt,rt,rx |
476 | ||
78f1dbde AK |
477 | /* 4 bits per slice and we have one slice per 1TB */ |
478 | #define SLICE_ARRAY_SIZE (PGTABLE_RANGE >> 41) | |
8d2169e8 DG |
479 | |
480 | #ifndef __ASSEMBLY__ | |
481 | ||
d28513bc DG |
482 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
483 | /* | |
484 | * For the sub-page protection option, we extend the PGD with one of | |
485 | * these. Basically we have a 3-level tree, with the top level being | |
486 | * the protptrs array. To optimize speed and memory consumption when | |
487 | * only addresses < 4GB are being protected, pointers to the first | |
488 | * four pages of sub-page protection words are stored in the low_prot | |
489 | * array. | |
490 | * Each page of sub-page protection words protects 1GB (4 bytes | |
491 | * protects 64k). For the 3-level tree, each page of pointers then | |
492 | * protects 8TB. | |
493 | */ | |
494 | struct subpage_prot_table { | |
495 | unsigned long maxaddr; /* only addresses < this are protected */ | |
dad6f37c | 496 | unsigned int **protptrs[(TASK_SIZE_USER64 >> 43)]; |
d28513bc DG |
497 | unsigned int *low_prot[4]; |
498 | }; | |
499 | ||
500 | #define SBP_L1_BITS (PAGE_SHIFT - 2) | |
501 | #define SBP_L2_BITS (PAGE_SHIFT - 3) | |
502 | #define SBP_L1_COUNT (1 << SBP_L1_BITS) | |
503 | #define SBP_L2_COUNT (1 << SBP_L2_BITS) | |
504 | #define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS) | |
505 | #define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS) | |
506 | ||
507 | extern void subpage_prot_free(struct mm_struct *mm); | |
508 | extern void subpage_prot_init_new_context(struct mm_struct *mm); | |
509 | #else | |
510 | static inline void subpage_prot_free(struct mm_struct *mm) {} | |
511 | static inline void subpage_prot_init_new_context(struct mm_struct *mm) { } | |
512 | #endif /* CONFIG_PPC_SUBPAGE_PROT */ | |
513 | ||
8d2169e8 | 514 | typedef unsigned long mm_context_id_t; |
851d2e2f | 515 | struct spinlock; |
8d2169e8 DG |
516 | |
517 | typedef struct { | |
518 | mm_context_id_t id; | |
d0f13e3c BH |
519 | u16 user_psize; /* page size index */ |
520 | ||
521 | #ifdef CONFIG_PPC_MM_SLICES | |
522 | u64 low_slices_psize; /* SLB page size encodings */ | |
78f1dbde | 523 | unsigned char high_slices_psize[SLICE_ARRAY_SIZE]; |
d0f13e3c BH |
524 | #else |
525 | u16 sllp; /* SLB page size encoding */ | |
8d2169e8 DG |
526 | #endif |
527 | unsigned long vdso_base; | |
d28513bc DG |
528 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
529 | struct subpage_prot_table spt; | |
530 | #endif /* CONFIG_PPC_SUBPAGE_PROT */ | |
851d2e2f THFL |
531 | #ifdef CONFIG_PPC_ICSWX |
532 | struct spinlock *cop_lockp; /* guard acop and cop_pid */ | |
533 | unsigned long acop; /* mask of enabled coprocessor types */ | |
534 | unsigned int cop_pid; /* pid value used with coprocessors */ | |
535 | #endif /* CONFIG_PPC_ICSWX */ | |
5c1f6ee9 AK |
536 | #ifdef CONFIG_PPC_64K_PAGES |
537 | /* for 4K PTE fragment support */ | |
538 | void *pte_frag; | |
539 | #endif | |
15b244a8 AK |
540 | #ifdef CONFIG_SPAPR_TCE_IOMMU |
541 | struct list_head iommu_group_mem_list; | |
542 | #endif | |
8d2169e8 DG |
543 | } mm_context_t; |
544 | ||
545 | ||
8d2169e8 | 546 | #if 0 |
1189be65 PM |
547 | /* |
548 | * The code below is equivalent to this function for arguments | |
549 | * < 2^VSID_BITS, which is all this should ever be called | |
550 | * with. However gcc is not clever enough to compute the | |
551 | * modulus (2^n-1) without a second multiply. | |
552 | */ | |
34692708 | 553 | #define vsid_scramble(protovsid, size) \ |
1189be65 | 554 | ((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size)) |
8d2169e8 | 555 | |
1189be65 PM |
556 | #else /* 1 */ |
557 | #define vsid_scramble(protovsid, size) \ | |
558 | ({ \ | |
559 | unsigned long x; \ | |
560 | x = (protovsid) * VSID_MULTIPLIER_##size; \ | |
561 | x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \ | |
562 | (x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \ | |
563 | }) | |
8d2169e8 | 564 | #endif /* 1 */ |
8d2169e8 | 565 | |
1189be65 PM |
566 | /* Returns the segment size indicator for a user address */ |
567 | static inline int user_segment_size(unsigned long addr) | |
8d2169e8 | 568 | { |
1189be65 PM |
569 | /* Use 1T segments if possible for addresses >= 1T */ |
570 | if (addr >= (1UL << SID_SHIFT_1T)) | |
571 | return mmu_highuser_ssize; | |
572 | return MMU_SEGSIZE_256M; | |
8d2169e8 DG |
573 | } |
574 | ||
1189be65 PM |
575 | static inline unsigned long get_vsid(unsigned long context, unsigned long ea, |
576 | int ssize) | |
577 | { | |
c60ac569 AK |
578 | /* |
579 | * Bad address. We return VSID 0 for that | |
580 | */ | |
581 | if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) | |
582 | return 0; | |
583 | ||
1189be65 | 584 | if (ssize == MMU_SEGSIZE_256M) |
af81d787 | 585 | return vsid_scramble((context << ESID_BITS) |
1189be65 | 586 | | (ea >> SID_SHIFT), 256M); |
af81d787 | 587 | return vsid_scramble((context << ESID_BITS_1T) |
1189be65 PM |
588 | | (ea >> SID_SHIFT_1T), 1T); |
589 | } | |
590 | ||
c60ac569 AK |
591 | /* |
592 | * This is only valid for addresses >= PAGE_OFFSET | |
593 | * | |
594 | * For kernel space, we use the top 4 context ids to map address as below | |
595 | * 0x7fffc - [ 0xc000000000000000 - 0xc0003fffffffffff ] | |
596 | * 0x7fffd - [ 0xd000000000000000 - 0xd0003fffffffffff ] | |
597 | * 0x7fffe - [ 0xe000000000000000 - 0xe0003fffffffffff ] | |
598 | * 0x7ffff - [ 0xf000000000000000 - 0xf0003fffffffffff ] | |
599 | */ | |
600 | static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize) | |
601 | { | |
602 | unsigned long context; | |
603 | ||
604 | /* | |
605 | * kernel take the top 4 context from the available range | |
606 | */ | |
607 | context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1; | |
608 | return get_vsid(context, ea, ssize); | |
609 | } | |
8d2169e8 DG |
610 | #endif /* __ASSEMBLY__ */ |
611 | ||
612 | #endif /* _ASM_POWERPC_MMU_HASH64_H_ */ |