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powerpc/mm: Fix build warnings with CONFIG_TRANSPARENT_HUGEPAGE disabled
[deliverable/linux.git] / arch / powerpc / include / asm / mmu-hash64.h
CommitLineData
8d2169e8
DG		 1#ifndef _ASM_POWERPC_MMU_HASH64_H_
2#define _ASM_POWERPC_MMU_HASH64_H_
3/*
4 * PowerPC64 memory management structures
5 *
6 * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
7 * PPC64 rework.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15#include <asm/asm-compat.h>
16#include <asm/page.h>
17
78f1dbde
AK		 18/*
19 * This is necessary to get the definition of PGTABLE_RANGE which we
20 * need for various slices related matters. Note that this isn't the
21 * complete pgtable.h but only a portion of it.
22 */
23#include <asm/pgtable-ppc64.h>
cf9427b8 24#include <asm/bug.h>
78f1dbde 25
8d2169e8
DG		 26/*
27 * Segment table
28 */
29
30#define STE_ESID_V 0x80
31#define STE_ESID_KS 0x20
32#define STE_ESID_KP 0x10
33#define STE_ESID_N 0x08
34
35#define STE_VSID_SHIFT 12
36
37/* Location of cpu0's segment table */
84493804 38#define STAB0_PAGE 0x8
8d2169e8
DG		 39#define STAB0_OFFSET (STAB0_PAGE << 12)
40#define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START)
41
42#ifndef __ASSEMBLY__
43extern char initial_stab[];
44#endif /* ! __ASSEMBLY */
45
46/*
47 * SLB
48 */
49
50#define SLB_NUM_BOLTED 3
51#define SLB_CACHE_ENTRIES 8
46db2f86 52#define SLB_MIN_SIZE 32
8d2169e8
DG		 53
54/* Bits in the SLB ESID word */
55#define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
56
57/* Bits in the SLB VSID word */
58#define SLB_VSID_SHIFT 12
1189be65
PM		 59#define SLB_VSID_SHIFT_1T 24
60#define SLB_VSID_SSIZE_SHIFT 62
8d2169e8
DG		 61#define SLB_VSID_B ASM_CONST(0xc000000000000000)
62#define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
63#define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
64#define SLB_VSID_KS ASM_CONST(0x0000000000000800)
65#define SLB_VSID_KP ASM_CONST(0x0000000000000400)
66#define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
67#define SLB_VSID_L ASM_CONST(0x0000000000000100)
68#define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
69#define SLB_VSID_LP ASM_CONST(0x0000000000000030)
70#define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000)
71#define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010)
72#define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020)
73#define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030)
74#define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP)
75
76#define SLB_VSID_KERNEL (SLB_VSID_KP)
77#define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
78
79#define SLBIE_C (0x08000000)
1189be65 80#define SLBIE_SSIZE_SHIFT 25
8d2169e8
DG		 81
82/*
83 * Hash table
84 */
85
86#define HPTES_PER_GROUP 8
87
2454c7e9 88#define HPTE_V_SSIZE_SHIFT 62
8d2169e8 89#define HPTE_V_AVPN_SHIFT 7
2454c7e9 90#define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80)
8d2169e8 91#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
91bbbe22 92#define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80UL))
8d2169e8
DG		 93#define HPTE_V_BOLTED ASM_CONST(0x0000000000000010)
94#define HPTE_V_LOCK ASM_CONST(0x0000000000000008)
95#define HPTE_V_LARGE ASM_CONST(0x0000000000000004)
96#define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002)
97#define HPTE_V_VALID ASM_CONST(0x0000000000000001)
98
99#define HPTE_R_PP0 ASM_CONST(0x8000000000000000)
100#define HPTE_R_TS ASM_CONST(0x4000000000000000)
de56a948 101#define HPTE_R_KEY_HI ASM_CONST(0x3000000000000000)
8d2169e8 102#define HPTE_R_RPN_SHIFT 12
de56a948 103#define HPTE_R_RPN ASM_CONST(0x0ffffffffffff000)
8d2169e8
DG		 104#define HPTE_R_PP ASM_CONST(0x0000000000000003)
105#define HPTE_R_N ASM_CONST(0x0000000000000004)
de56a948
PM		 106#define HPTE_R_G ASM_CONST(0x0000000000000008)
107#define HPTE_R_M ASM_CONST(0x0000000000000010)
108#define HPTE_R_I ASM_CONST(0x0000000000000020)
109#define HPTE_R_W ASM_CONST(0x0000000000000040)
110#define HPTE_R_WIMG ASM_CONST(0x0000000000000078)
8d2169e8
DG		 111#define HPTE_R_C ASM_CONST(0x0000000000000080)
112#define HPTE_R_R ASM_CONST(0x0000000000000100)
de56a948 113#define HPTE_R_KEY_LO ASM_CONST(0x0000000000000e00)
8d2169e8 114
b7abc5c5
SS		 115#define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000)
116#define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff000000)
117
8d2169e8 118/* Values for PP (assumes Ks=0, Kp=1) */
8d2169e8
DG		 119#define PP_RWXX 0 /* Supervisor read/write, User none */
120#define PP_RWRX 1 /* Supervisor read/write, User read */
121#define PP_RWRW 2 /* Supervisor read/write, User read/write */
122#define PP_RXRX 3 /* Supervisor read, User read */
697d3899 123#define PP_RXXX (HPTE_R_PP0 | 2) /* Supervisor read, user none */
8d2169e8 124
b4072df4
PM		 125/* Fields for tlbiel instruction in architecture 2.06 */
126#define TLBIEL_INVAL_SEL_MASK 0xc00 /* invalidation selector */
127#define TLBIEL_INVAL_PAGE 0x000 /* invalidate a single page */
128#define TLBIEL_INVAL_SET_LPID 0x800 /* invalidate a set for current LPID */
129#define TLBIEL_INVAL_SET 0xc00 /* invalidate a set for all LPIDs */
130#define TLBIEL_INVAL_SET_MASK 0xfff000 /* set number to inval. */
131#define TLBIEL_INVAL_SET_SHIFT 12
132
133#define POWER7_TLB_SETS 128 /* # sets in POWER7 TLB */
134
8d2169e8
DG		 135#ifndef __ASSEMBLY__
136
8e561e7e 137struct hash_pte {
8d2169e8
DG		 138 unsigned long v;
139 unsigned long r;
8e561e7e 140};
8d2169e8 141
8e561e7e 142extern struct hash_pte *htab_address;
8d2169e8
DG		 143extern unsigned long htab_size_bytes;
144extern unsigned long htab_hash_mask;
145
146/*
147 * Page size definition
148 *
149 * shift : is the "PAGE_SHIFT" value for that page size
150 * sllp : is a bit mask with the value of SLB L || LP to be or'ed
151 * directly to a slbmte "vsid" value
152 * penc : is the HPTE encoding mask for the "LP" field:
153 *
154 */
155struct mmu_psize_def
156{
157 unsigned int shift; /* number of bits */
b1022fbd 158 int penc[MMU_PAGE_COUNT]; /* HPTE encoding */
8d2169e8
DG		 159 unsigned int tlbiel; /* tlbiel supported for that page size */
160 unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
161 unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
162};
cf9427b8
AK		 163extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
164
165static inline int shift_to_mmu_psize(unsigned int shift)
166{
167 int psize;
168
169 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize)
170 if (mmu_psize_defs[psize].shift == shift)
171 return psize;
172 return -1;
173}
174
175static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
176{
177 if (mmu_psize_defs[mmu_psize].shift)
178 return mmu_psize_defs[mmu_psize].shift;
179 BUG();
180}
8d2169e8
DG		 181
182#endif /* __ASSEMBLY__ */
183
2454c7e9
PM		 184/*
185 * Segment sizes.
186 * These are the values used by hardware in the B field of
187 * SLB entries and the first dword of MMU hashtable entries.
188 * The B field is 2 bits; the values 2 and 3 are unused and reserved.
189 */
190#define MMU_SEGSIZE_256M 0
191#define MMU_SEGSIZE_1T 1
192
5524a27d
AK		 193/*
194 * encode page number shift.
195 * in order to fit the 78 bit va in a 64 bit variable we shift the va by
196 * 12 bits. This enable us to address upto 76 bit va.
197 * For hpt hash from a va we can ignore the page size bits of va and for
198 * hpte encoding we ignore up to 23 bits of va. So ignoring lower 12 bits ensure
199 * we work in all cases including 4k page size.
200 */
201#define VPN_SHIFT 12
1189be65 202
b1022fbd
AK		 203/*
204 * HPTE Large Page (LP) details
205 */
206#define LP_SHIFT 12
207#define LP_BITS 8
208#define LP_MASK(i) ((0xFF >> (i)) << LP_SHIFT)
209
8d2169e8
DG		 210#ifndef __ASSEMBLY__
211
5524a27d
AK		 212static inline int segment_shift(int ssize)
213{
214 if (ssize == MMU_SEGSIZE_256M)
215 return SID_SHIFT;
216 return SID_SHIFT_1T;
217}
218
8d2169e8 219/*
1189be65 220 * The current system page and segment sizes
8d2169e8 221 */
8d2169e8
DG		 222extern int mmu_linear_psize;
223extern int mmu_virtual_psize;
224extern int mmu_vmalloc_psize;
cec08e7a 225extern int mmu_vmemmap_psize;
8d2169e8 226extern int mmu_io_psize;
1189be65
PM		 227extern int mmu_kernel_ssize;
228extern int mmu_highuser_ssize;
584f8b71 229extern u16 mmu_slb_size;
572fb578 230extern unsigned long tce_alloc_start, tce_alloc_end;
8d2169e8
DG		 231
232/*
233 * If the processor supports 64k normal pages but not 64k cache
234 * inhibited pages, we have to be prepared to switch processes
235 * to use 4k pages when they create cache-inhibited mappings.
236 * If this is the case, mmu_ci_restrictions will be set to 1.
237 */
238extern int mmu_ci_restrictions;
239
5524a27d
AK		 240/*
241 * This computes the AVPN and B fields of the first dword of a HPTE,
242 * for use when we want to match an existing PTE. The bottom 7 bits
243 * of the returned value are zero.
244 */
245static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
246 int ssize)
247{
248 unsigned long v;
249 /*
250 * The AVA field omits the low-order 23 bits of the 78 bits VA.
251 * These bits are not needed in the PTE, because the
252 * low-order b of these bits are part of the byte offset
253 * into the virtual page and, if b < 23, the high-order
254 * 23-b of these bits are always used in selecting the
255 * PTEGs to be searched
256 */
257 v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm);
258 v <<= HPTE_V_AVPN_SHIFT;
259 v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
260 return v;
261}
262
8d2169e8
DG		 263/*
264 * This function sets the AVPN and L fields of the HPTE appropriately
b1022fbd 265 * using the base page size and actual page size.
8d2169e8 266 */
b1022fbd
AK		 267static inline unsigned long hpte_encode_v(unsigned long vpn, int base_psize,
268 int actual_psize, int ssize)
8d2169e8 269{
1189be65 270 unsigned long v;
b1022fbd
AK		 271 v = hpte_encode_avpn(vpn, base_psize, ssize);
272 if (actual_psize != MMU_PAGE_4K)
8d2169e8
DG		 273 v |= HPTE_V_LARGE;
274 return v;
275}
276
277/*
278 * This function sets the ARPN, and LP fields of the HPTE appropriately
279 * for the page size. We assume the pa is already "clean" that is properly
280 * aligned for the requested page size
281 */
b1022fbd
AK		 282static inline unsigned long hpte_encode_r(unsigned long pa, int base_psize,
283 int actual_psize)
8d2169e8 284{
8d2169e8 285 /* A 4K page needs no special encoding */
b1022fbd 286 if (actual_psize == MMU_PAGE_4K)
8d2169e8
DG		 287 return pa & HPTE_R_RPN;
288 else {
b1022fbd
AK		 289 unsigned int penc = mmu_psize_defs[base_psize].penc[actual_psize];
290 unsigned int shift = mmu_psize_defs[actual_psize].shift;
291 return (pa & ~((1ul << shift) - 1)) | (penc << LP_SHIFT);
8d2169e8 292 }
8d2169e8
DG		 293}
294
295/*
5524a27d 296 * Build a VPN_SHIFT bit shifted va given VSID, EA and segment size.
8d2169e8 297 */
5524a27d
AK		 298static inline unsigned long hpt_vpn(unsigned long ea,
299 unsigned long vsid, int ssize)
1189be65 300{
5524a27d
AK		 301 unsigned long mask;
302 int s_shift = segment_shift(ssize);
303
304 mask = (1ul << (s_shift - VPN_SHIFT)) - 1;
305 return (vsid << (s_shift - VPN_SHIFT)) | ((ea >> VPN_SHIFT) & mask);
1189be65 306}
8d2169e8 307
1189be65
PM		 308/*
309 * This hashes a virtual address
310 */
5524a27d
AK		 311static inline unsigned long hpt_hash(unsigned long vpn,
312 unsigned int shift, int ssize)
8d2169e8 313{
5524a27d 314 int mask;
1189be65
PM		 315 unsigned long hash, vsid;
316
5524a27d 317 /* VPN_SHIFT can be atmost 12 */
1189be65 318 if (ssize == MMU_SEGSIZE_256M) {
5524a27d
AK		 319 mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1;
320 hash = (vpn >> (SID_SHIFT - VPN_SHIFT)) ^
321 ((vpn & mask) >> (shift - VPN_SHIFT));
1189be65 322 } else {
5524a27d
AK		 323 mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1;
324 vsid = vpn >> (SID_SHIFT_1T - VPN_SHIFT);
325 hash = vsid ^ (vsid << 25) ^
326 ((vpn & mask) >> (shift - VPN_SHIFT)) ;
1189be65
PM		 327 }
328 return hash & 0x7fffffffffUL;
8d2169e8
DG		 329}
330
331extern int __hash_page_4K(unsigned long ea, unsigned long access,
332 unsigned long vsid, pte_t *ptep, unsigned long trap,
fa28237c 333 unsigned int local, int ssize, int subpage_prot);
8d2169e8
DG		 334extern int __hash_page_64K(unsigned long ea, unsigned long access,
335 unsigned long vsid, pte_t *ptep, unsigned long trap,
1189be65 336 unsigned int local, int ssize);
8d2169e8 337struct mm_struct;
0895ecda 338unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap);
8d2169e8 339extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap);
a4fe3ce7
DG		 340int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
341 pte_t *ptep, unsigned long trap, int local, int ssize,
342 unsigned int shift, unsigned int mmu_psize);
6d492ecc
AK		 343#ifdef CONFIG_TRANSPARENT_HUGEPAGE
344extern int __hash_page_thp(unsigned long ea, unsigned long access,
345 unsigned long vsid, pmd_t *pmdp, unsigned long trap,
346 int local, int ssize, unsigned int psize);
347#else
348static inline int __hash_page_thp(unsigned long ea, unsigned long access,
349 unsigned long vsid, pmd_t *pmdp,
350 unsigned long trap, int local,
351 int ssize, unsigned int psize)
352{
353 BUG();
ff1e7683 354 return -1;
6d492ecc
AK		 355}
356#endif
4b8692c0
BH		 357extern void hash_failure_debug(unsigned long ea, unsigned long access,
358 unsigned long vsid, unsigned long trap,
d8139ebf
AK		 359 int ssize, int psize, int lpsize,
360 unsigned long pte);
8d2169e8 361extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
bc033b63 362 unsigned long pstart, unsigned long prot,
1189be65 363 int psize, int ssize);
41151e77 364extern void add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages);
fa28237c 365extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
8d2169e8 366
8d2169e8
DG		 367extern void hpte_init_native(void);
368extern void hpte_init_lpar(void);
8d2169e8 369extern void hpte_init_beat(void);
7f2c8577 370extern void hpte_init_beat_v3(void);
8d2169e8
DG		 371
372extern void stabs_alloc(void);
373extern void slb_initialize(void);
374extern void slb_flush_and_rebolt(void);
375extern void stab_initialize(unsigned long stab);
376
67439b76 377extern void slb_vmalloc_update(void);
46db2f86 378extern void slb_set_size(u16 size);
8d2169e8
DG		 379#endif /* __ASSEMBLY__ */
380
381/*
f033d659 382 * VSID allocation (256MB segment)
8d2169e8 383 *
c60ac569
AK		 384 * We first generate a 37-bit "proto-VSID". Proto-VSIDs are generated
385 * from mmu context id and effective segment id of the address.
8d2169e8 386 *
c60ac569
AK		 387 * For user processes max context id is limited to ((1ul << 19) - 5)
388 * for kernel space, we use the top 4 context ids to map address as below
389 * NOTE: each context only support 64TB now.
390 * 0x7fffc - [ 0xc000000000000000 - 0xc0003fffffffffff ]
391 * 0x7fffd - [ 0xd000000000000000 - 0xd0003fffffffffff ]
392 * 0x7fffe - [ 0xe000000000000000 - 0xe0003fffffffffff ]
393 * 0x7ffff - [ 0xf000000000000000 - 0xf0003fffffffffff ]
8d2169e8
DG		 394 *
395 * The proto-VSIDs are then scrambled into real VSIDs with the
396 * multiplicative hash:
397 *
398 * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
8d2169e8 399 *
f033d659 400 * VSID_MULTIPLIER is prime, so in particular it is
8d2169e8
DG		 401 * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
402 * Because the modulus is 2^n-1 we can compute it efficiently without
c60ac569
AK		 403 * a divide or extra multiply (see below). The scramble function gives
404 * robust scattering in the hash table (at least based on some initial
405 * results).
8d2169e8 406 *
c60ac569
AK		 407 * We also consider VSID 0 special. We use VSID 0 for slb entries mapping
408 * bad address. This enables us to consolidate bad address handling in
409 * hash_page.
8d2169e8 410 *
c60ac569
AK		 411 * We also need to avoid the last segment of the last context, because that
412 * would give a protovsid of 0x1fffffffff. That will result in a VSID 0
413 * because of the modulo operation in vsid scramble. But the vmemmap
414 * (which is what uses region 0xf) will never be close to 64TB in size
415 * (it's 56 bytes per page of system memory).
8d2169e8 416 */
8d2169e8 417
e39d1a47 418#define CONTEXT_BITS 19
af81d787
AK		 419#define ESID_BITS 18
420#define ESID_BITS_1T 6
e39d1a47 421
c60ac569
AK		 422/*
423 * 256MB segment
af81d787 424 * The proto-VSID space has 2^(CONTEX_BITS + ESID_BITS) - 1 segments
c60ac569
AK		 425 * available for user + kernel mapping. The top 4 contexts are used for
426 * kernel mapping. Each segment contains 2^28 bytes. Each
427 * context maps 2^46 bytes (64TB) so we can support 2^19-1 contexts
428 * (19 == 37 + 28 - 46).
429 */
430#define MAX_USER_CONTEXT ((ASM_CONST(1) << CONTEXT_BITS) - 5)
431
048ee099
AK		 432/*
433 * This should be computed such that protovosid * vsid_mulitplier
434 * doesn't overflow 64 bits. It should also be co-prime to vsid_modulus
435 */
436#define VSID_MULTIPLIER_256M ASM_CONST(12538073) /* 24-bit prime */
af81d787 437#define VSID_BITS_256M (CONTEXT_BITS + ESID_BITS)
1189be65 438#define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1)
8d2169e8 439
1189be65 440#define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */
af81d787 441#define VSID_BITS_1T (CONTEXT_BITS + ESID_BITS_1T)
1189be65
PM		 442#define VSID_MODULUS_1T ((1UL<<VSID_BITS_1T)-1)
443
8d2169e8 444
af81d787 445#define USER_VSID_RANGE (1UL << (ESID_BITS + SID_SHIFT))
8d2169e8
DG		 446
447/*
448 * This macro generates asm code to compute the VSID scramble
449 * function. Used in slb_allocate() and do_stab_bolted. The function
450 * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
451 *
452 * rt = register continaing the proto-VSID and into which the
453 * VSID will be stored
454 * rx = scratch register (clobbered)
455 *
456 * - rt and rx must be different registers
1189be65 457 * - The answer will end up in the low VSID_BITS bits of rt. The higher
8d2169e8
DG		 458 * bits may contain other garbage, so you may need to mask the
459 * result.
460 */
1189be65
PM		 461#define ASM_VSID_SCRAMBLE(rt, rx, size) \
462 lis rx,VSID_MULTIPLIER_##size@h; \
463 ori rx,rx,VSID_MULTIPLIER_##size@l; \
8d2169e8
DG		 464 mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \
465 \
1189be65
PM		 466 srdi rx,rt,VSID_BITS_##size; \
467 clrldi rt,rt,(64-VSID_BITS_##size); \
8d2169e8 468 add rt,rt,rx; /* add high and low bits */ \
c60ac569
AK		 469 /* NOTE: explanation based on VSID_BITS_##size = 36 \
470 * Now, r3 == VSID (mod 2^36-1), and lies between 0 and \
8d2169e8
DG		 471 * 2^36-1+2^28-1. That in particular means that if r3 >= \
472 * 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \
473 * the bit clear, r3 already has the answer we want, if it \
474 * doesn't, the answer is the low 36 bits of r3+1. So in all \
475 * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
476 addi rx,rt,1; \
1189be65 477 srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \
8d2169e8
DG		 478 add rt,rt,rx
479
78f1dbde
AK		 480/* 4 bits per slice and we have one slice per 1TB */
481#define SLICE_ARRAY_SIZE (PGTABLE_RANGE >> 41)
8d2169e8
DG		 482
483#ifndef __ASSEMBLY__
484
d28513bc
DG		 485#ifdef CONFIG_PPC_SUBPAGE_PROT
486/*
487 * For the sub-page protection option, we extend the PGD with one of
488 * these. Basically we have a 3-level tree, with the top level being
489 * the protptrs array. To optimize speed and memory consumption when
490 * only addresses < 4GB are being protected, pointers to the first
491 * four pages of sub-page protection words are stored in the low_prot
492 * array.
493 * Each page of sub-page protection words protects 1GB (4 bytes
494 * protects 64k). For the 3-level tree, each page of pointers then
495 * protects 8TB.
496 */
497struct subpage_prot_table {
498 unsigned long maxaddr; /* only addresses < this are protected */
499 unsigned int **protptrs[2];
500 unsigned int *low_prot[4];
501};
502
503#define SBP_L1_BITS (PAGE_SHIFT - 2)
504#define SBP_L2_BITS (PAGE_SHIFT - 3)
505#define SBP_L1_COUNT (1 << SBP_L1_BITS)
506#define SBP_L2_COUNT (1 << SBP_L2_BITS)
507#define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS)
508#define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS)
509
510extern void subpage_prot_free(struct mm_struct *mm);
511extern void subpage_prot_init_new_context(struct mm_struct *mm);
512#else
513static inline void subpage_prot_free(struct mm_struct *mm) {}
514static inline void subpage_prot_init_new_context(struct mm_struct *mm) { }
515#endif /* CONFIG_PPC_SUBPAGE_PROT */
516
8d2169e8 517typedef unsigned long mm_context_id_t;
851d2e2f 518struct spinlock;
8d2169e8
DG		 519
520typedef struct {
521 mm_context_id_t id;
d0f13e3c
BH		 522 u16 user_psize; /* page size index */
523
524#ifdef CONFIG_PPC_MM_SLICES
525 u64 low_slices_psize; /* SLB page size encodings */
78f1dbde 526 unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
d0f13e3c
BH		 527#else
528 u16 sllp; /* SLB page size encoding */
8d2169e8
DG		 529#endif
530 unsigned long vdso_base;
d28513bc
DG		 531#ifdef CONFIG_PPC_SUBPAGE_PROT
532 struct subpage_prot_table spt;
533#endif /* CONFIG_PPC_SUBPAGE_PROT */
851d2e2f
THFL		 534#ifdef CONFIG_PPC_ICSWX
535 struct spinlock *cop_lockp; /* guard acop and cop_pid */
536 unsigned long acop; /* mask of enabled coprocessor types */
537 unsigned int cop_pid; /* pid value used with coprocessors */
538#endif /* CONFIG_PPC_ICSWX */
5c1f6ee9
AK		 539#ifdef CONFIG_PPC_64K_PAGES
540 /* for 4K PTE fragment support */
541 void *pte_frag;
542#endif
8d2169e8
DG		 543} mm_context_t;
544
545
8d2169e8 546#if 0
1189be65
PM		 547/*
548 * The code below is equivalent to this function for arguments
549 * < 2^VSID_BITS, which is all this should ever be called
550 * with. However gcc is not clever enough to compute the
551 * modulus (2^n-1) without a second multiply.
552 */
34692708 553#define vsid_scramble(protovsid, size) \
1189be65 554 ((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size))
8d2169e8 555
1189be65
PM		 556#else /* 1 */
557#define vsid_scramble(protovsid, size) \
558 ({ \
559 unsigned long x; \
560 x = (protovsid) * VSID_MULTIPLIER_##size; \
561 x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \
562 (x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \
563 })
8d2169e8 564#endif /* 1 */
8d2169e8 565
1189be65
PM		 566/* Returns the segment size indicator for a user address */
567static inline int user_segment_size(unsigned long addr)
8d2169e8 568{
1189be65
PM		 569 /* Use 1T segments if possible for addresses >= 1T */
570 if (addr >= (1UL << SID_SHIFT_1T))
571 return mmu_highuser_ssize;
572 return MMU_SEGSIZE_256M;
8d2169e8
DG		 573}
574
1189be65
PM		 575static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
576 int ssize)
577{
c60ac569
AK		 578 /*
579 * Bad address. We return VSID 0 for that
580 */
581 if ((ea & ~REGION_MASK) >= PGTABLE_RANGE)
582 return 0;
583
1189be65 584 if (ssize == MMU_SEGSIZE_256M)
af81d787 585 return vsid_scramble((context << ESID_BITS)
1189be65 586 | (ea >> SID_SHIFT), 256M);
af81d787 587 return vsid_scramble((context << ESID_BITS_1T)
1189be65
PM		 588 | (ea >> SID_SHIFT_1T), 1T);
589}
590
c60ac569
AK		 591/*
592 * This is only valid for addresses >= PAGE_OFFSET
593 *
594 * For kernel space, we use the top 4 context ids to map address as below
595 * 0x7fffc - [ 0xc000000000000000 - 0xc0003fffffffffff ]
596 * 0x7fffd - [ 0xd000000000000000 - 0xd0003fffffffffff ]
597 * 0x7fffe - [ 0xe000000000000000 - 0xe0003fffffffffff ]
598 * 0x7ffff - [ 0xf000000000000000 - 0xf0003fffffffffff ]
599 */
600static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
601{
602 unsigned long context;
603
604 /*
605 * kernel take the top 4 context from the available range
606 */
607 context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1;
608 return get_vsid(context, ea, ssize);
609}
8d2169e8
DG		 610#endif /* __ASSEMBLY__ */
611
612#endif /* _ASM_POWERPC_MMU_HASH64_H_ */
Linux kernel - Deliverables
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