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047ea784 PM |
1 | #ifndef _ASM_POWERPC_MMU_H_ |
2 | #define _ASM_POWERPC_MMU_H_ | |
88ced031 | 3 | #ifdef __KERNEL__ |
047ea784 | 4 | |
7c03d653 BH |
5 | #include <asm/asm-compat.h> |
6 | #include <asm/feature-fixups.h> | |
7 | ||
8 | /* | |
9 | * MMU features bit definitions | |
10 | */ | |
11 | ||
12 | /* | |
13 | * First half is MMU families | |
14 | */ | |
15 | #define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001) | |
16 | #define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002) | |
17 | #define MMU_FTR_TYPE_40x ASM_CONST(0x00000004) | |
18 | #define MMU_FTR_TYPE_44x ASM_CONST(0x00000008) | |
19 | #define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010) | |
20 | ||
21 | /* | |
22 | * This is individual features | |
23 | */ | |
24 | ||
25 | /* Enable use of high BAT registers */ | |
26 | #define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000) | |
27 | ||
28 | /* Enable >32-bit physical addresses on 32-bit processor, only used | |
29 | * by CONFIG_6xx currently as BookE supports that from day 1 | |
30 | */ | |
31 | #define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000) | |
32 | ||
f048aace BH |
33 | /* Enable use of broadcast TLB invalidations. We don't always set it |
34 | * on processors that support it due to other constraints with the | |
35 | * use of such invalidations | |
36 | */ | |
37 | #define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000) | |
38 | ||
c3071951 | 39 | /* Enable use of tlbilx invalidate instructions. |
f048aace | 40 | */ |
c3071951 | 41 | #define MMU_FTR_USE_TLBILX ASM_CONST(0x00080000) |
f048aace BH |
42 | |
43 | /* This indicates that the processor cannot handle multiple outstanding | |
44 | * broadcast tlbivax or tlbsync. This makes the code use a spinlock | |
45 | * around such invalidate forms. | |
46 | */ | |
47 | #define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000) | |
48 | ||
2319f123 KG |
49 | /* This indicates that the processor doesn't handle way selection |
50 | * properly and needs SW to track and update the LRU state. This | |
51 | * is specific to an errata on e300c2/c3/c4 class parts | |
52 | */ | |
53 | #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000) | |
54 | ||
60dbf438 MM |
55 | /* This indicates that the processor uses the ISA 2.06 server tlbie |
56 | * mnemonics | |
57 | */ | |
58 | #define MMU_FTR_TLBIE_206 ASM_CONST(0x00400000) | |
59 | ||
7c03d653 BH |
60 | #ifndef __ASSEMBLY__ |
61 | #include <asm/cputable.h> | |
62 | ||
63 | static inline int mmu_has_feature(unsigned long feature) | |
64 | { | |
65 | return (cur_cpu_spec->mmu_features & feature); | |
66 | } | |
67 | ||
68 | extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup; | |
69 | ||
757c74d2 BH |
70 | /* MMU initialization (64-bit only fo now) */ |
71 | extern void early_init_mmu(void); | |
72 | extern void early_init_mmu_secondary(void); | |
73 | ||
7c03d653 BH |
74 | #endif /* !__ASSEMBLY__ */ |
75 | ||
76 | ||
94491685 | 77 | #if defined(CONFIG_PPC_STD_MMU_64) |
8d2169e8 DG |
78 | /* 64-bit classic hash table MMU */ |
79 | # include <asm/mmu-hash64.h> | |
94491685 | 80 | #elif defined(CONFIG_PPC_STD_MMU_32) |
4db68bfe DG |
81 | /* 32-bit classic hash table MMU */ |
82 | # include <asm/mmu-hash32.h> | |
4d922c8d JB |
83 | #elif defined(CONFIG_40x) |
84 | /* 40x-style software loaded TLB */ | |
85 | # include <asm/mmu-40x.h> | |
57d7909e DG |
86 | #elif defined(CONFIG_44x) |
87 | /* 44x-style software loaded TLB */ | |
88 | # include <asm/mmu-44x.h> | |
70fe3af8 KG |
89 | #elif defined(CONFIG_PPC_BOOK3E_MMU) |
90 | /* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */ | |
91 | # include <asm/mmu-book3e.h> | |
31202345 DG |
92 | #elif defined (CONFIG_PPC_8xx) |
93 | /* Motorola/Freescale 8xx software loaded TLB */ | |
94 | # include <asm/mmu-8xx.h> | |
1f8d419e | 95 | #endif |
1f8d419e | 96 | |
88ced031 | 97 | #endif /* __KERNEL__ */ |
047ea784 | 98 | #endif /* _ASM_POWERPC_MMU_H_ */ |