Commit | Line | Data |
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a8dbceb7 AG |
1 | /* |
2 | * MPC5121 Prototypes and definitions | |
3 | * | |
4 | * This file is licensed under the terms of the GNU General Public | |
5 | * License version 2. | |
6 | */ | |
7 | ||
8 | #ifndef __ASM_POWERPC_MPC5121_H__ | |
9 | #define __ASM_POWERPC_MPC5121_H__ | |
10 | ||
11 | /* MPC512x Reset module registers */ | |
12 | struct mpc512x_reset_module { | |
13 | u32 rcwlr; /* Reset Configuration Word Low Register */ | |
14 | u32 rcwhr; /* Reset Configuration Word High Register */ | |
15 | u32 reserved1; | |
16 | u32 reserved2; | |
17 | u32 rsr; /* Reset Status Register */ | |
18 | u32 rmr; /* Reset Mode Register */ | |
19 | u32 rpr; /* Reset Protection Register */ | |
20 | u32 rcr; /* Reset Control Register */ | |
21 | u32 rcer; /* Reset Control Enable Register */ | |
22 | }; | |
23 | ||
4b5006ec AG |
24 | /* |
25 | * Clock Control Module | |
26 | */ | |
27 | struct mpc512x_ccm { | |
28 | u32 spmr; /* System PLL Mode Register */ | |
29 | u32 sccr1; /* System Clock Control Register 1 */ | |
30 | u32 sccr2; /* System Clock Control Register 2 */ | |
31 | u32 scfr1; /* System Clock Frequency Register 1 */ | |
32 | u32 scfr2; /* System Clock Frequency Register 2 */ | |
33 | u32 scfr2s; /* System Clock Frequency Shadow Register 2 */ | |
34 | u32 bcr; /* Bread Crumb Register */ | |
35 | u32 p0ccr; /* PSC0 Clock Control Register */ | |
36 | u32 p1ccr; /* PSC1 CCR */ | |
37 | u32 p2ccr; /* PSC2 CCR */ | |
38 | u32 p3ccr; /* PSC3 CCR */ | |
39 | u32 p4ccr; /* PSC4 CCR */ | |
40 | u32 p5ccr; /* PSC5 CCR */ | |
41 | u32 p6ccr; /* PSC6 CCR */ | |
42 | u32 p7ccr; /* PSC7 CCR */ | |
43 | u32 p8ccr; /* PSC8 CCR */ | |
44 | u32 p9ccr; /* PSC9 CCR */ | |
45 | u32 p10ccr; /* PSC10 CCR */ | |
46 | u32 p11ccr; /* PSC11 CCR */ | |
47 | u32 spccr; /* SPDIF Clock Control Register */ | |
48 | u32 cccr; /* CFM Clock Control Register */ | |
49 | u32 dccr; /* DIU Clock Control Register */ | |
50 | u32 m1ccr; /* MSCAN1 CCR */ | |
51 | u32 m2ccr; /* MSCAN2 CCR */ | |
52 | u32 m3ccr; /* MSCAN3 CCR */ | |
53 | u32 m4ccr; /* MSCAN4 CCR */ | |
54 | u8 res[0x98]; /* Reserved */ | |
55 | }; | |
a8dbceb7 | 56 | #endif /* __ASM_POWERPC_MPC5121_H__ */ |