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bbeb3f4c SR |
1 | #ifndef _ASM_POWERPC_MPIC_H |
2 | #define _ASM_POWERPC_MPIC_H | |
88ced031 | 3 | #ifdef __KERNEL__ |
bbeb3f4c | 4 | |
14cf11af | 5 | #include <linux/irq.h> |
fbf0274e | 6 | #include <asm/dcr.h> |
25235f71 | 7 | #include <asm/msi_bitmap.h> |
14cf11af PM |
8 | |
9 | /* | |
10 | * Global registers | |
11 | */ | |
12 | ||
13 | #define MPIC_GREG_BASE 0x01000 | |
14 | ||
15 | #define MPIC_GREG_FEATURE_0 0x00000 | |
16 | #define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000 | |
17 | #define MPIC_GREG_FEATURE_LAST_SRC_SHIFT 16 | |
18 | #define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00 | |
19 | #define MPIC_GREG_FEATURE_LAST_CPU_SHIFT 8 | |
20 | #define MPIC_GREG_FEATURE_VERSION_MASK 0xff | |
21 | #define MPIC_GREG_FEATURE_1 0x00010 | |
22 | #define MPIC_GREG_GLOBAL_CONF_0 0x00020 | |
23 | #define MPIC_GREG_GCONF_RESET 0x80000000 | |
d91e4ea7 KG |
24 | /* On the FSL mpic implementations the Mode field is expand to be |
25 | * 2 bits wide: | |
26 | * 0b00 = pass through (interrupts routed to IRQ0) | |
27 | * 0b01 = Mixed mode | |
28 | * 0b10 = reserved | |
29 | * 0b11 = External proxy / coreint | |
30 | */ | |
31 | #define MPIC_GREG_GCONF_COREINT 0x60000000 | |
14cf11af | 32 | #define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000 |
d87bf3be | 33 | #define MPIC_GREG_GCONF_NO_BIAS 0x10000000 |
14cf11af | 34 | #define MPIC_GREG_GCONF_BASE_MASK 0x000fffff |
f365355e | 35 | #define MPIC_GREG_GCONF_MCK 0x08000000 |
14cf11af | 36 | #define MPIC_GREG_GLOBAL_CONF_1 0x00030 |
868ea0c9 MG |
37 | #define MPIC_GREG_GLOBAL_CONF_1_SIE 0x08000000 |
38 | #define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK 0x70000000 | |
39 | #define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r) \ | |
40 | (((r) << 28) & MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK) | |
14cf11af PM |
41 | #define MPIC_GREG_VENDOR_0 0x00040 |
42 | #define MPIC_GREG_VENDOR_1 0x00050 | |
43 | #define MPIC_GREG_VENDOR_2 0x00060 | |
44 | #define MPIC_GREG_VENDOR_3 0x00070 | |
45 | #define MPIC_GREG_VENDOR_ID 0x00080 | |
46 | #define MPIC_GREG_VENDOR_ID_STEPPING_MASK 0x00ff0000 | |
47 | #define MPIC_GREG_VENDOR_ID_STEPPING_SHIFT 16 | |
48 | #define MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00 | |
49 | #define MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT 8 | |
50 | #define MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK 0x000000ff | |
51 | #define MPIC_GREG_PROCESSOR_INIT 0x00090 | |
52 | #define MPIC_GREG_IPI_VECTOR_PRI_0 0x000a0 | |
53 | #define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0 | |
54 | #define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0 | |
55 | #define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0 | |
7233593b | 56 | #define MPIC_GREG_IPI_STRIDE 0x10 |
14cf11af PM |
57 | #define MPIC_GREG_SPURIOUS 0x000e0 |
58 | #define MPIC_GREG_TIMER_FREQ 0x000f0 | |
59 | ||
60 | /* | |
61 | * | |
62 | * Timer registers | |
63 | */ | |
64 | #define MPIC_TIMER_BASE 0x01100 | |
65 | #define MPIC_TIMER_STRIDE 0x40 | |
03bcb7e3 | 66 | #define MPIC_TIMER_GROUP_STRIDE 0x1000 |
14cf11af PM |
67 | |
68 | #define MPIC_TIMER_CURRENT_CNT 0x00000 | |
69 | #define MPIC_TIMER_BASE_CNT 0x00010 | |
70 | #define MPIC_TIMER_VECTOR_PRI 0x00020 | |
71 | #define MPIC_TIMER_DESTINATION 0x00030 | |
72 | ||
73 | /* | |
74 | * Per-Processor registers | |
75 | */ | |
76 | ||
77 | #define MPIC_CPU_THISBASE 0x00000 | |
78 | #define MPIC_CPU_BASE 0x20000 | |
79 | #define MPIC_CPU_STRIDE 0x01000 | |
80 | ||
81 | #define MPIC_CPU_IPI_DISPATCH_0 0x00040 | |
82 | #define MPIC_CPU_IPI_DISPATCH_1 0x00050 | |
83 | #define MPIC_CPU_IPI_DISPATCH_2 0x00060 | |
84 | #define MPIC_CPU_IPI_DISPATCH_3 0x00070 | |
7233593b | 85 | #define MPIC_CPU_IPI_DISPATCH_STRIDE 0x00010 |
14cf11af PM |
86 | #define MPIC_CPU_CURRENT_TASK_PRI 0x00080 |
87 | #define MPIC_CPU_TASKPRI_MASK 0x0000000f | |
88 | #define MPIC_CPU_WHOAMI 0x00090 | |
89 | #define MPIC_CPU_WHOAMI_MASK 0x0000001f | |
90 | #define MPIC_CPU_INTACK 0x000a0 | |
91 | #define MPIC_CPU_EOI 0x000b0 | |
f365355e | 92 | #define MPIC_CPU_MCACK 0x000c0 |
14cf11af PM |
93 | |
94 | /* | |
95 | * Per-source registers | |
96 | */ | |
97 | ||
98 | #define MPIC_IRQ_BASE 0x10000 | |
99 | #define MPIC_IRQ_STRIDE 0x00020 | |
100 | #define MPIC_IRQ_VECTOR_PRI 0x00000 | |
101 | #define MPIC_VECPRI_MASK 0x80000000 | |
102 | #define MPIC_VECPRI_ACTIVITY 0x40000000 /* Read Only */ | |
103 | #define MPIC_VECPRI_PRIORITY_MASK 0x000f0000 | |
104 | #define MPIC_VECPRI_PRIORITY_SHIFT 16 | |
105 | #define MPIC_VECPRI_VECTOR_MASK 0x000007ff | |
106 | #define MPIC_VECPRI_POLARITY_POSITIVE 0x00800000 | |
107 | #define MPIC_VECPRI_POLARITY_NEGATIVE 0x00000000 | |
108 | #define MPIC_VECPRI_POLARITY_MASK 0x00800000 | |
109 | #define MPIC_VECPRI_SENSE_LEVEL 0x00400000 | |
110 | #define MPIC_VECPRI_SENSE_EDGE 0x00000000 | |
111 | #define MPIC_VECPRI_SENSE_MASK 0x00400000 | |
112 | #define MPIC_IRQ_DESTINATION 0x00010 | |
113 | ||
03bcb7e3 VS |
114 | #define MPIC_FSL_BRR1 0x00000 |
115 | #define MPIC_FSL_BRR1_VER 0x0000ffff | |
116 | ||
14cf11af PM |
117 | #define MPIC_MAX_IRQ_SOURCES 2048 |
118 | #define MPIC_MAX_CPUS 32 | |
119 | #define MPIC_MAX_ISU 32 | |
120 | ||
0a408164 VS |
121 | #define MPIC_MAX_ERR 32 |
122 | #define MPIC_FSL_ERR_INT 16 | |
123 | ||
7233593b ZR |
124 | /* |
125 | * Tsi108 implementation of MPIC has many differences from the original one | |
126 | */ | |
127 | ||
128 | /* | |
129 | * Global registers | |
130 | */ | |
131 | ||
132 | #define TSI108_GREG_BASE 0x00000 | |
133 | #define TSI108_GREG_FEATURE_0 0x00000 | |
134 | #define TSI108_GREG_GLOBAL_CONF_0 0x00004 | |
135 | #define TSI108_GREG_VENDOR_ID 0x0000c | |
136 | #define TSI108_GREG_IPI_VECTOR_PRI_0 0x00204 /* Doorbell 0 */ | |
137 | #define TSI108_GREG_IPI_STRIDE 0x0c | |
138 | #define TSI108_GREG_SPURIOUS 0x00010 | |
139 | #define TSI108_GREG_TIMER_FREQ 0x00014 | |
140 | ||
141 | /* | |
142 | * Timer registers | |
143 | */ | |
144 | #define TSI108_TIMER_BASE 0x0030 | |
145 | #define TSI108_TIMER_STRIDE 0x10 | |
146 | #define TSI108_TIMER_CURRENT_CNT 0x00000 | |
147 | #define TSI108_TIMER_BASE_CNT 0x00004 | |
148 | #define TSI108_TIMER_VECTOR_PRI 0x00008 | |
149 | #define TSI108_TIMER_DESTINATION 0x0000c | |
150 | ||
151 | /* | |
152 | * Per-Processor registers | |
153 | */ | |
154 | #define TSI108_CPU_BASE 0x00300 | |
155 | #define TSI108_CPU_STRIDE 0x00040 | |
156 | #define TSI108_CPU_IPI_DISPATCH_0 0x00200 | |
157 | #define TSI108_CPU_IPI_DISPATCH_STRIDE 0x00000 | |
158 | #define TSI108_CPU_CURRENT_TASK_PRI 0x00000 | |
159 | #define TSI108_CPU_WHOAMI 0xffffffff | |
160 | #define TSI108_CPU_INTACK 0x00004 | |
161 | #define TSI108_CPU_EOI 0x00008 | |
f365355e | 162 | #define TSI108_CPU_MCACK 0x00004 /* Doesn't really exist here */ |
7233593b ZR |
163 | |
164 | /* | |
165 | * Per-source registers | |
166 | */ | |
167 | #define TSI108_IRQ_BASE 0x00100 | |
168 | #define TSI108_IRQ_STRIDE 0x00008 | |
169 | #define TSI108_IRQ_VECTOR_PRI 0x00000 | |
170 | #define TSI108_VECPRI_VECTOR_MASK 0x000000ff | |
171 | #define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000 | |
172 | #define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000 | |
173 | #define TSI108_VECPRI_SENSE_LEVEL 0x02000000 | |
174 | #define TSI108_VECPRI_SENSE_EDGE 0x00000000 | |
175 | #define TSI108_VECPRI_POLARITY_MASK 0x01000000 | |
176 | #define TSI108_VECPRI_SENSE_MASK 0x02000000 | |
177 | #define TSI108_IRQ_DESTINATION 0x00004 | |
178 | ||
179 | /* weird mpic register indices and mask bits in the HW info array */ | |
180 | enum { | |
181 | MPIC_IDX_GREG_BASE = 0, | |
182 | MPIC_IDX_GREG_FEATURE_0, | |
183 | MPIC_IDX_GREG_GLOBAL_CONF_0, | |
184 | MPIC_IDX_GREG_VENDOR_ID, | |
185 | MPIC_IDX_GREG_IPI_VECTOR_PRI_0, | |
186 | MPIC_IDX_GREG_IPI_STRIDE, | |
187 | MPIC_IDX_GREG_SPURIOUS, | |
188 | MPIC_IDX_GREG_TIMER_FREQ, | |
189 | ||
190 | MPIC_IDX_TIMER_BASE, | |
191 | MPIC_IDX_TIMER_STRIDE, | |
192 | MPIC_IDX_TIMER_CURRENT_CNT, | |
193 | MPIC_IDX_TIMER_BASE_CNT, | |
194 | MPIC_IDX_TIMER_VECTOR_PRI, | |
195 | MPIC_IDX_TIMER_DESTINATION, | |
196 | ||
197 | MPIC_IDX_CPU_BASE, | |
198 | MPIC_IDX_CPU_STRIDE, | |
199 | MPIC_IDX_CPU_IPI_DISPATCH_0, | |
200 | MPIC_IDX_CPU_IPI_DISPATCH_STRIDE, | |
201 | MPIC_IDX_CPU_CURRENT_TASK_PRI, | |
202 | MPIC_IDX_CPU_WHOAMI, | |
203 | MPIC_IDX_CPU_INTACK, | |
204 | MPIC_IDX_CPU_EOI, | |
f365355e | 205 | MPIC_IDX_CPU_MCACK, |
7233593b ZR |
206 | |
207 | MPIC_IDX_IRQ_BASE, | |
208 | MPIC_IDX_IRQ_STRIDE, | |
209 | MPIC_IDX_IRQ_VECTOR_PRI, | |
210 | ||
211 | MPIC_IDX_VECPRI_VECTOR_MASK, | |
212 | MPIC_IDX_VECPRI_POLARITY_POSITIVE, | |
213 | MPIC_IDX_VECPRI_POLARITY_NEGATIVE, | |
214 | MPIC_IDX_VECPRI_SENSE_LEVEL, | |
215 | MPIC_IDX_VECPRI_SENSE_EDGE, | |
216 | MPIC_IDX_VECPRI_POLARITY_MASK, | |
217 | MPIC_IDX_VECPRI_SENSE_MASK, | |
218 | MPIC_IDX_IRQ_DESTINATION, | |
219 | MPIC_IDX_END | |
220 | }; | |
221 | ||
222 | ||
6cfef5b2 | 223 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
14cf11af PM |
224 | /* Fixup table entry */ |
225 | struct mpic_irq_fixup | |
226 | { | |
227 | u8 __iomem *base; | |
1beb6a7d | 228 | u8 __iomem *applebase; |
c4b22f26 | 229 | u32 data; |
1beb6a7d | 230 | unsigned int index; |
14cf11af | 231 | }; |
6cfef5b2 | 232 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
14cf11af PM |
233 | |
234 | ||
fbf0274e BH |
235 | enum mpic_reg_type { |
236 | mpic_access_mmio_le, | |
237 | mpic_access_mmio_be, | |
238 | #ifdef CONFIG_PPC_DCR | |
239 | mpic_access_dcr | |
240 | #endif | |
241 | }; | |
242 | ||
243 | struct mpic_reg_bank { | |
244 | u32 __iomem *base; | |
245 | #ifdef CONFIG_PPC_DCR | |
246 | dcr_host_t dhost; | |
fbf0274e BH |
247 | #endif /* CONFIG_PPC_DCR */ |
248 | }; | |
249 | ||
3669e930 JB |
250 | struct mpic_irq_save { |
251 | u32 vecprio, | |
252 | dest; | |
253 | #ifdef CONFIG_MPIC_U3_HT_IRQS | |
254 | u32 fixup_data; | |
255 | #endif | |
256 | }; | |
257 | ||
14cf11af PM |
258 | /* The instance data of a given MPIC */ |
259 | struct mpic | |
260 | { | |
c51242e7 KM |
261 | /* The OpenFirmware dt node for this MPIC */ |
262 | struct device_node *node; | |
263 | ||
0ebfff14 | 264 | /* The remapper for this MPIC */ |
bae1d8f1 | 265 | struct irq_domain *irqhost; |
0ebfff14 | 266 | |
14cf11af | 267 | /* The "linux" controller struct */ |
b9e5b4e6 | 268 | struct irq_chip hc_irq; |
6cfef5b2 | 269 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
b9e5b4e6 BH |
270 | struct irq_chip hc_ht_irq; |
271 | #endif | |
14cf11af | 272 | #ifdef CONFIG_SMP |
b9e5b4e6 | 273 | struct irq_chip hc_ipi; |
14cf11af | 274 | #endif |
ea94187f | 275 | struct irq_chip hc_tm; |
0a408164 | 276 | struct irq_chip hc_err; |
14cf11af PM |
277 | const char *name; |
278 | /* Flags */ | |
279 | unsigned int flags; | |
280 | /* How many irq sources in a given ISU */ | |
281 | unsigned int isu_size; | |
282 | unsigned int isu_shift; | |
283 | unsigned int isu_mask; | |
14cf11af PM |
284 | /* Number of sources */ |
285 | unsigned int num_sources; | |
14cf11af | 286 | |
7df2457d OJ |
287 | /* vector numbers used for internal sources (ipi/timers) */ |
288 | unsigned int ipi_vecs[4]; | |
ea94187f | 289 | unsigned int timer_vecs[8]; |
0a408164 VS |
290 | /* vector numbers used for FSL MPIC error interrupts */ |
291 | unsigned int err_int_vecs[MPIC_MAX_ERR]; | |
7df2457d OJ |
292 | |
293 | /* Spurious vector to program into unused sources */ | |
294 | unsigned int spurious_vec; | |
295 | ||
6cfef5b2 | 296 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
14cf11af PM |
297 | /* The fixup table */ |
298 | struct mpic_irq_fixup *fixups; | |
203041ad | 299 | raw_spinlock_t fixup_lock; |
14cf11af PM |
300 | #endif |
301 | ||
fbf0274e BH |
302 | /* Register access method */ |
303 | enum mpic_reg_type reg_type; | |
304 | ||
e7a98675 KM |
305 | /* The physical base address of the MPIC */ |
306 | phys_addr_t paddr; | |
307 | ||
14cf11af | 308 | /* The various ioremap'ed bases */ |
03bcb7e3 | 309 | struct mpic_reg_bank thiscpuregs; |
fbf0274e BH |
310 | struct mpic_reg_bank gregs; |
311 | struct mpic_reg_bank tmregs; | |
312 | struct mpic_reg_bank cpuregs[MPIC_MAX_CPUS]; | |
313 | struct mpic_reg_bank isus[MPIC_MAX_ISU]; | |
314 | ||
0a408164 VS |
315 | /* ioremap'ed base for error interrupt registers */ |
316 | u32 __iomem *err_regs; | |
317 | ||
7fd72186 BH |
318 | /* Protected sources */ |
319 | unsigned long *protected; | |
320 | ||
7233593b ZR |
321 | #ifdef CONFIG_MPIC_WEIRD |
322 | /* Pointer to HW info array */ | |
323 | u32 *hw_set; | |
324 | #endif | |
325 | ||
a7de7c74 | 326 | #ifdef CONFIG_PCI_MSI |
25235f71 | 327 | struct msi_bitmap msi_bitmap; |
a7de7c74 ME |
328 | #endif |
329 | ||
0d72ba93 OJ |
330 | #ifdef CONFIG_MPIC_BROKEN_REGREAD |
331 | u32 isu_reg0_shadow[MPIC_MAX_IRQ_SOURCES]; | |
332 | #endif | |
333 | ||
14cf11af PM |
334 | /* link */ |
335 | struct mpic *next; | |
3669e930 | 336 | |
3669e930 JB |
337 | #ifdef CONFIG_PM |
338 | struct mpic_irq_save *save_data; | |
339 | #endif | |
14cf11af PM |
340 | }; |
341 | ||
7233593b ZR |
342 | /* |
343 | * MPIC flags (passed to mpic_alloc) | |
344 | * | |
345 | * The top 4 bits contain an MPIC bhw id that is used to index the | |
346 | * register offsets and some masks when CONFIG_MPIC_WEIRD is set. | |
347 | * Note setting any ID (leaving those bits to 0) means standard MPIC | |
348 | */ | |
349 | ||
be8bec56 KM |
350 | /* |
351 | * This is a secondary ("chained") controller; it only uses the CPU0 | |
352 | * registers. Primary controllers have IPIs and affinity control. | |
14cf11af | 353 | */ |
be8bec56 | 354 | #define MPIC_SECONDARY 0x00000001 |
7233593b | 355 | |
14cf11af PM |
356 | /* Set this for a big-endian MPIC */ |
357 | #define MPIC_BIG_ENDIAN 0x00000002 | |
358 | /* Broken U3 MPIC */ | |
6cfef5b2 | 359 | #define MPIC_U3_HT_IRQS 0x00000004 |
14cf11af PM |
360 | /* Broken IPI registers (autodetected) */ |
361 | #define MPIC_BROKEN_IPI 0x00000008 | |
7233593b ZR |
362 | /* Spurious vector requires EOI */ |
363 | #define MPIC_SPV_EOI 0x00000020 | |
364 | /* No passthrough disable */ | |
365 | #define MPIC_NO_PTHROU_DIS 0x00000040 | |
fbf0274e BH |
366 | /* DCR based MPIC */ |
367 | #define MPIC_USES_DCR 0x00000080 | |
7df2457d OJ |
368 | /* MPIC has 11-bit vector fields (or larger) */ |
369 | #define MPIC_LARGE_VECTORS 0x00000100 | |
f365355e OJ |
370 | /* Enable delivery of prio 15 interrupts as MCK instead of EE */ |
371 | #define MPIC_ENABLE_MCK 0x00000200 | |
d87bf3be OJ |
372 | /* Disable bias among target selection, spread interrupts evenly */ |
373 | #define MPIC_NO_BIAS 0x00000400 | |
3c10c9c4 KG |
374 | /* Destination only supports a single CPU at a time */ |
375 | #define MPIC_SINGLE_DEST_CPU 0x00001000 | |
d91e4ea7 KG |
376 | /* Enable CoreInt delivery of interrupts */ |
377 | #define MPIC_ENABLE_COREINT 0x00002000 | |
e55d7f73 | 378 | /* Do not reset the MPIC during initialization */ |
dfec2202 | 379 | #define MPIC_NO_RESET 0x00004000 |
22d168ce SW |
380 | /* Freescale MPIC (compatible includes "fsl,mpic") */ |
381 | #define MPIC_FSL 0x00008000 | |
0a408164 VS |
382 | /* Freescale MPIC supports EIMR (error interrupt mask register). |
383 | * This flag is set for MPIC version >= 4.1 (version determined | |
384 | * from the BRR1 register). | |
385 | */ | |
386 | #define MPIC_FSL_HAS_EIMR 0x00010000 | |
7233593b ZR |
387 | |
388 | /* MPIC HW modification ID */ | |
389 | #define MPIC_REGSET_MASK 0xf0000000 | |
390 | #define MPIC_REGSET(val) (((val) & 0xf ) << 28) | |
391 | #define MPIC_GET_REGSET(flags) (((flags) >> 28) & 0xf) | |
392 | ||
393 | #define MPIC_REGSET_STANDARD MPIC_REGSET(0) /* Original MPIC */ | |
394 | #define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109 PIC */ | |
14cf11af PM |
395 | |
396 | /* Allocate the controller structure and setup the linux irq descs | |
397 | * for the range if interrupts passed in. No HW initialization is | |
398 | * actually performed. | |
399 | * | |
400 | * @phys_addr: physial base address of the MPIC | |
401 | * @flags: flags, see constants above | |
402 | * @isu_size: number of interrupts in an ISU. Use 0 to use a | |
403 | * standard ISU-less setup (aka powermac) | |
404 | * @irq_offset: first irq number to assign to this mpic | |
405 | * @irq_count: number of irqs to use with this mpic IRQ sources. Pass 0 | |
406 | * to match the number of sources | |
407 | * @ipi_offset: first irq number to assign to this mpic IPI sources, | |
408 | * used only on primary mpic | |
409 | * @senses: array of sense values | |
410 | * @senses_num: number of entries in the array | |
411 | * | |
412 | * Note about the sense array. If none is passed, all interrupts are | |
6cfef5b2 | 413 | * setup to be level negative unless MPIC_U3_HT_IRQS is set in which |
14cf11af PM |
414 | * case they are edge positive (and the array is ignored anyway). |
415 | * The values in the array start at the first source of the MPIC, | |
416 | * that is senses[0] correspond to linux irq "irq_offset". | |
417 | */ | |
0ebfff14 | 418 | extern struct mpic *mpic_alloc(struct device_node *node, |
a959ff56 | 419 | phys_addr_t phys_addr, |
14cf11af PM |
420 | unsigned int flags, |
421 | unsigned int isu_size, | |
14cf11af | 422 | unsigned int irq_count, |
14cf11af PM |
423 | const char *name); |
424 | ||
425 | /* Assign ISUs, to call before mpic_init() | |
426 | * | |
427 | * @mpic: controller structure as returned by mpic_alloc() | |
428 | * @isu_num: ISU number | |
429 | * @phys_addr: physical address of the ISU | |
430 | */ | |
431 | extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, | |
a959ff56 | 432 | phys_addr_t phys_addr); |
14cf11af | 433 | |
0ebfff14 | 434 | |
14cf11af PM |
435 | /* Initialize the controller. After this has been called, none of the above |
436 | * should be called again for this mpic | |
437 | */ | |
438 | extern void mpic_init(struct mpic *mpic); | |
439 | ||
14cf11af PM |
440 | /* |
441 | * All of the following functions must only be used after the | |
442 | * ISUs have been assigned and the controller fully initialized | |
443 | * with mpic_init() | |
444 | */ | |
445 | ||
446 | ||
06a901c5 | 447 | /* Change the priority of an interrupt. Default is 8 for irqs and |
14cf11af PM |
448 | * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the |
449 | * IPI number is then the offset'ed (linux irq number mapped to the IPI) | |
450 | */ | |
451 | extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri); | |
14cf11af PM |
452 | |
453 | /* Setup a non-boot CPU */ | |
454 | extern void mpic_setup_this_cpu(void); | |
455 | ||
456 | /* Clean up for kexec (or cpu offline or ...) */ | |
457 | extern void mpic_teardown_this_cpu(int secondary); | |
458 | ||
459 | /* Get the current cpu priority for this cpu (0..15) */ | |
460 | extern int mpic_cpu_get_priority(void); | |
461 | ||
462 | /* Set the current cpu priority for this cpu */ | |
463 | extern void mpic_cpu_set_priority(int prio); | |
464 | ||
465 | /* Request IPIs on primary mpic */ | |
466 | extern void mpic_request_ipis(void); | |
467 | ||
a9c59264 PM |
468 | /* Send a message (IPI) to a given target (cpu number or MSG_*) */ |
469 | void smp_mpic_message_pass(int target, int msg); | |
470 | ||
f365355e | 471 | /* Unmask a specific virq */ |
835c0553 | 472 | extern void mpic_unmask_irq(struct irq_data *d); |
f365355e | 473 | /* Mask a specific virq */ |
835c0553 | 474 | extern void mpic_mask_irq(struct irq_data *d); |
f365355e | 475 | /* EOI a specific virq */ |
835c0553 | 476 | extern void mpic_end_irq(struct irq_data *d); |
f365355e | 477 | |
14cf11af | 478 | /* Fetch interrupt from a given mpic */ |
35a84c2f | 479 | extern unsigned int mpic_get_one_irq(struct mpic *mpic); |
f365355e | 480 | /* This one gets from the primary mpic */ |
35a84c2f | 481 | extern unsigned int mpic_get_irq(void); |
d91e4ea7 KG |
482 | /* This one gets from the primary mpic via CoreInt*/ |
483 | extern unsigned int mpic_get_coreint_irq(void); | |
f365355e OJ |
484 | /* Fetch Machine Check interrupt from primary mpic */ |
485 | extern unsigned int mpic_get_mcirq(void); | |
14cf11af | 486 | |
868ea0c9 MG |
487 | /* Set the EPIC clock ratio */ |
488 | void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio); | |
489 | ||
490 | /* Enable/Disable EPIC serial interrupt mode */ | |
491 | void mpic_set_serial_int(struct mpic *mpic, int enable); | |
492 | ||
88ced031 | 493 | #endif /* __KERNEL__ */ |
bbeb3f4c | 494 | #endif /* _ASM_POWERPC_MPIC_H */ |