Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
8882a4da DG |
2 | * This control block defines the PACA which defines the processor |
3 | * specific data for each logical processor on the system. | |
1da177e4 LT |
4 | * There are some pointers defined that are utilized by PLIC. |
5 | * | |
6 | * C 2001 PPC 64 Team, IBM Corp | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version | |
11 | * 2 of the License, or (at your option) any later version. | |
8882a4da DG |
12 | */ |
13 | #ifndef _ASM_POWERPC_PACA_H | |
14 | #define _ASM_POWERPC_PACA_H | |
88ced031 | 15 | #ifdef __KERNEL__ |
1da177e4 | 16 | |
1426d5a3 ME |
17 | #ifdef CONFIG_PPC64 |
18 | ||
2fc251a8 | 19 | #include <linux/string.h> |
dce6670a BH |
20 | #include <asm/types.h> |
21 | #include <asm/lppaca.h> | |
22 | #include <asm/mmu.h> | |
23 | #include <asm/page.h> | |
24 | #include <asm/exception-64e.h> | |
7e57cba0 | 25 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
2191d657 | 26 | #include <asm/kvm_book3s_asm.h> |
7e57cba0 | 27 | #endif |
c223c903 | 28 | #include <asm/accounting.h> |
fd7bacbc | 29 | #include <asm/hmi.h> |
1da177e4 LT |
30 | |
31 | register struct paca_struct *local_paca asm("r13"); | |
048c8bc9 HD |
32 | |
33 | #if defined(CONFIG_DEBUG_PREEMPT) && defined(CONFIG_SMP) | |
34 | extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */ | |
35 | /* | |
36 | * Add standard checks that preemption cannot occur when using get_paca(): | |
37 | * otherwise the paca_struct it points to may be the wrong one just after. | |
38 | */ | |
39 | #define get_paca() ((void) debug_smp_processor_id(), local_paca) | |
40 | #else | |
1da177e4 | 41 | #define get_paca() local_paca |
048c8bc9 HD |
42 | #endif |
43 | ||
3356bb9f | 44 | #define get_lppaca() (get_paca()->lppaca_ptr) |
2f6093c8 | 45 | #define get_slb_shadow() (get_paca()->slb_shadow_ptr) |
1da177e4 LT |
46 | |
47 | struct task_struct; | |
1da177e4 LT |
48 | |
49 | /* | |
50 | * Defines the layout of the paca. | |
51 | * | |
52 | * This structure is not directly accessed by firmware or the service | |
30ff2e87 | 53 | * processor. |
1da177e4 LT |
54 | */ |
55 | struct paca_struct { | |
91c60b5b | 56 | #ifdef CONFIG_PPC_BOOK3S |
1da177e4 LT |
57 | /* |
58 | * Because hw_cpu_id, unlike other paca fields, is accessed | |
59 | * routinely from other CPUs (from the IRQ code), we stick to | |
60 | * read-only (after boot) fields in the first cacheline to | |
61 | * avoid cacheline bouncing. | |
62 | */ | |
63 | ||
1da177e4 | 64 | struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */ |
91c60b5b | 65 | #endif /* CONFIG_PPC_BOOK3S */ |
1da177e4 | 66 | /* |
2ef9481e | 67 | * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c |
1da177e4 LT |
68 | * load lock_token and paca_index with a single lwz |
69 | * instruction. They must travel together and be properly | |
70 | * aligned. | |
71 | */ | |
54bb7f4b | 72 | #ifdef __BIG_ENDIAN__ |
1da177e4 LT |
73 | u16 lock_token; /* Constant 0x8000, used in locks */ |
74 | u16 paca_index; /* Logical processor number */ | |
54bb7f4b AB |
75 | #else |
76 | u16 paca_index; /* Logical processor number */ | |
77 | u16 lock_token; /* Constant 0x8000, used in locks */ | |
78 | #endif | |
1da177e4 | 79 | |
1da177e4 | 80 | u64 kernel_toc; /* Kernel TOC address */ |
1f6a93e4 PM |
81 | u64 kernelbase; /* Base address of kernel */ |
82 | u64 kernel_msr; /* MSR while running in kernel */ | |
1da177e4 | 83 | void *emergency_sp; /* pointer to emergency stack */ |
7a0268fa | 84 | u64 data_offset; /* per cpu data offset */ |
1da177e4 LT |
85 | s16 hw_cpu_id; /* Physical processor number */ |
86 | u8 cpu_start; /* At startup, processor spins until */ | |
87 | /* this becomes non-zero. */ | |
1fc711f7 | 88 | u8 kexec_state; /* set when kexec down has irqs off */ |
91c60b5b | 89 | #ifdef CONFIG_PPC_STD_MMU_64 |
e91948fd | 90 | struct slb_shadow *slb_shadow_ptr; |
cf9efce0 PM |
91 | struct dtl_entry *dispatch_log; |
92 | struct dtl_entry *dispatch_log_end; | |
1739ea9e S |
93 | #endif /* CONFIG_PPC_STD_MMU_64 */ |
94 | u64 dscr_default; /* per-CPU default DSCR */ | |
1da177e4 | 95 | |
1739ea9e | 96 | #ifdef CONFIG_PPC_STD_MMU_64 |
1da177e4 LT |
97 | /* |
98 | * Now, starting in cacheline 2, the exception save areas | |
99 | */ | |
3c726f8d | 100 | /* used for most interrupts/exceptions */ |
bc2e6c6a MN |
101 | u64 exgen[13] __attribute__((aligned(0x80))); |
102 | u64 exmc[13]; /* used for machine checks */ | |
103 | u64 exslb[13]; /* used for SLB/segment table misses | |
3c726f8d | 104 | * on the linear mapping */ |
91c60b5b | 105 | /* SLB related definitions */ |
bf72aeba | 106 | u16 vmalloc_sllp; |
1da177e4 | 107 | u16 slb_cache_ptr; |
735cafc3 | 108 | u32 slb_cache[SLB_CACHE_ENTRIES]; |
91c60b5b BH |
109 | #endif /* CONFIG_PPC_STD_MMU_64 */ |
110 | ||
dce6670a | 111 | #ifdef CONFIG_PPC_BOOK3E |
016f8cf0 | 112 | u64 exgen[8] __aligned(0x40); |
f67f4ef5 | 113 | /* Keep pgd in the same cacheline as the start of extlb */ |
016f8cf0 | 114 | pgd_t *pgd __aligned(0x40); /* Current PGD */ |
f67f4ef5 | 115 | pgd_t *kernel_pgd; /* Kernel PGD */ |
28efc35f SW |
116 | |
117 | /* Shared by all threads of a core -- points to tcd of first thread */ | |
118 | struct tlb_core_data *tcd_ptr; | |
119 | ||
609af38f SW |
120 | /* |
121 | * We can have up to 3 levels of reentrancy in the TLB miss handler, | |
122 | * in each of four exception levels (normal, crit, mcheck, debug). | |
123 | */ | |
124 | u64 extlb[12][EX_TLB_SIZE / sizeof(u64)]; | |
dce6670a BH |
125 | u64 exmc[8]; /* used for machine checks */ |
126 | u64 excrit[8]; /* used for crit interrupts */ | |
127 | u64 exdbg[8]; /* used for debug interrupts */ | |
128 | ||
129 | /* Kernel stack pointers for use by special exceptions */ | |
130 | void *mc_kstack; | |
131 | void *crit_kstack; | |
132 | void *dbg_kstack; | |
28efc35f SW |
133 | |
134 | struct tlb_core_data tcd; | |
dce6670a BH |
135 | #endif /* CONFIG_PPC_BOOK3E */ |
136 | ||
c395465d | 137 | #ifdef CONFIG_PPC_BOOK3S |
2fc251a8 MN |
138 | mm_context_id_t mm_ctx_id; |
139 | #ifdef CONFIG_PPC_MM_SLICES | |
140 | u64 mm_ctx_low_slices_psize; | |
141 | unsigned char mm_ctx_high_slices_psize[SLICE_ARRAY_SIZE]; | |
142 | #else | |
c33e54fa | 143 | u16 mm_ctx_user_psize; |
2fc251a8 MN |
144 | u16 mm_ctx_sllp; |
145 | #endif | |
c395465d | 146 | #endif |
1da177e4 LT |
147 | |
148 | /* | |
149 | * then miscellaneous read-write fields | |
150 | */ | |
151 | struct task_struct *__current; /* Pointer to current */ | |
152 | u64 kstack; /* Saved Kernel stack addr */ | |
153 | u64 stab_rr; /* stab/slb round-robin counter */ | |
948cf67c | 154 | u64 saved_r1; /* r1 save for RTAS calls or PM */ |
1da177e4 | 155 | u64 saved_msr; /* MSR saved here by enter_rtas */ |
68730401 | 156 | u16 trap_save; /* Used when bad stack is encountered */ |
d04c56f7 | 157 | u8 soft_enabled; /* irq soft-enable flag */ |
7230c564 | 158 | u8 irq_happened; /* irq happened while soft-disabled */ |
f007cacf | 159 | u8 io_sync; /* writel() needs spin_unlock sync */ |
e360adbe | 160 | u8 irq_work_pending; /* IRQ_WORK interrupt while soft-disable */ |
2fde6d20 | 161 | u8 nap_state_lost; /* NV GPR values lost in power7_idle */ |
9d378dfa | 162 | u64 sprg_vdso; /* Saved user-visible sprg */ |
afc07701 MN |
163 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
164 | u64 tm_scratch; /* TM scratch area for reclaim */ | |
165 | #endif | |
c6622f63 | 166 | |
7cba160a SP |
167 | #ifdef CONFIG_PPC_POWERNV |
168 | /* Per-core mask tracking idle threads and a lock bit-[L][TTTTTTTT] */ | |
169 | u32 *core_idle_state_ptr; | |
170 | u8 thread_idle_state; /* PNV_THREAD_RUNNING/NAP/SLEEP */ | |
171 | /* Mask to indicate thread id in core */ | |
172 | u8 thread_mask; | |
77b54e9f SP |
173 | /* Mask to denote subcore sibling threads */ |
174 | u8 subcore_sibling_mask; | |
7cba160a SP |
175 | #endif |
176 | ||
729b0f71 MS |
177 | #ifdef CONFIG_PPC_BOOK3S_64 |
178 | /* Exclusive emergency stack pointer for machine check exception. */ | |
179 | void *mc_emergency_sp; | |
180 | /* | |
181 | * Flag to check whether we are in machine check early handler | |
182 | * and already using emergency stack. | |
183 | */ | |
184 | u16 in_mce; | |
0ef95b41 | 185 | u8 hmi_event_available; /* HMI event is available */ |
729b0f71 | 186 | #endif |
ed79ba9e | 187 | |
c6622f63 | 188 | /* Stuff for accurate time accounting */ |
c223c903 | 189 | struct cpu_accounting_data accounting; |
cf9efce0 PM |
190 | u64 stolen_time; /* TB ticks taken by hypervisor */ |
191 | u64 dtl_ridx; /* read index in dispatch log */ | |
192 | struct dtl_entry *dtl_curr; /* pointer corresponding to dtl_ridx */ | |
4b7ae55d | 193 | |
c14dea04 | 194 | #ifdef CONFIG_KVM_BOOK3S_HANDLER |
7aa79938 | 195 | #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE |
7e57cba0 AG |
196 | /* We use this to store guest state in */ |
197 | struct kvmppc_book3s_shadow_vcpu shadow_vcpu; | |
de56a948 | 198 | #endif |
3c42bf8a | 199 | struct kvmppc_host_state kvm_hstate; |
7c379526 PB |
200 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
201 | /* | |
202 | * Bitmap for sibling subcore status. See kvm/book3s_hv_ras.c for | |
203 | * more details | |
204 | */ | |
205 | struct sibling_subcore_state *sibling_subcore_state; | |
206 | #endif | |
4b7ae55d | 207 | #endif |
1da177e4 LT |
208 | }; |
209 | ||
c395465d MN |
210 | #ifdef CONFIG_PPC_BOOK3S |
211 | static inline void copy_mm_to_paca(mm_context_t *context) | |
212 | { | |
2fc251a8 MN |
213 | get_paca()->mm_ctx_id = context->id; |
214 | #ifdef CONFIG_PPC_MM_SLICES | |
215 | get_paca()->mm_ctx_low_slices_psize = context->low_slices_psize; | |
216 | memcpy(&get_paca()->mm_ctx_high_slices_psize, | |
217 | &context->high_slices_psize, SLICE_ARRAY_SIZE); | |
218 | #else | |
c33e54fa | 219 | get_paca()->mm_ctx_user_psize = context->user_psize; |
2fc251a8 MN |
220 | get_paca()->mm_ctx_sllp = context->sllp; |
221 | #endif | |
c395465d MN |
222 | } |
223 | #else | |
224 | static inline void copy_mm_to_paca(mm_context_t *context){} | |
225 | #endif | |
226 | ||
1426d5a3 | 227 | extern struct paca_struct *paca; |
1426d5a3 | 228 | extern void initialise_paca(struct paca_struct *new_paca, int cpu); |
fc53b420 | 229 | extern void setup_paca(struct paca_struct *new_paca); |
1426d5a3 ME |
230 | extern void allocate_pacas(void); |
231 | extern void free_unused_pacas(void); | |
232 | ||
233 | #else /* CONFIG_PPC64 */ | |
234 | ||
235 | static inline void allocate_pacas(void) { }; | |
236 | static inline void free_unused_pacas(void) { }; | |
237 | ||
238 | #endif /* CONFIG_PPC64 */ | |
1da177e4 | 239 | |
88ced031 | 240 | #endif /* __KERNEL__ */ |
8882a4da | 241 | #endif /* _ASM_POWERPC_PACA_H */ |