[deliverable/linux.git] / arch / powerpc / include / asm / pci-bridge.h

#ifndef _ASM_POWERPC_PCI_BRIDGE_H
#define _ASM_POWERPC_PCI_BRIDGE_H
#ifdef __KERNEL__
/*
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */
#include <linux/pci.h>
#include <linux/list.h>
#include <linux/ioport.h>
#include <asm-generic/pci-bridge.h>

/* Return values for pci_controller_ops.probe_mode function */
#define PCI_PROBE_NONE		-1	/* Don't look at this bus at all */
#define PCI_PROBE_NORMAL	0	/* Do normal PCI probing */
#define PCI_PROBE_DEVTREE	1	/* Instantiate from device tree */

struct device_node;

/*
 * PCI controller operations
 */
struct pci_controller_ops {
	void		(*dma_dev_setup)(struct pci_dev *dev);
	void		(*dma_bus_setup)(struct pci_bus *bus);

	int		(*probe_mode)(struct pci_bus *);

	/* Called when pci_enable_device() is called. Returns true to
	 * allow assignment/enabling of the device. */
	bool		(*enable_device_hook)(struct pci_dev *);

	/* Called during PCI resource reassignment */
	resource_size_t (*window_alignment)(struct pci_bus *, unsigned long type);
	void		(*reset_secondary_bus)(struct pci_dev *dev);
};

/*
 * Structure of a PCI controller (host bridge)
 */
struct pci_controller {
	struct pci_bus *bus;
	char is_dynamic;
#ifdef CONFIG_PPC64
	int node;
#endif
	struct device_node *dn;
	struct list_head list_node;
	struct device *parent;

	int first_busno;
	int last_busno;
	int self_busno;
	struct resource busn;

	void __iomem *io_base_virt;
#ifdef CONFIG_PPC64
	void *io_base_alloc;
#endif
	resource_size_t io_base_phys;
	resource_size_t pci_io_size;

	/* Some machines have a special region to forward the ISA
	 * "memory" cycles such as VGA memory regions. Left to 0
	 * if unsupported
	 */
	resource_size_t	isa_mem_phys;
	resource_size_t	isa_mem_size;

	struct pci_controller_ops controller_ops;
	struct pci_ops *ops;
	unsigned int __iomem *cfg_addr;
	void __iomem *cfg_data;

	/*
	 * Used for variants of PCI indirect handling and possible quirks:
	 *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
	 *  EXT_REG - provides access to PCI-e extended registers
	 *  SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
	 *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
	 *   to determine which bus number to match on when generating type0
	 *   config cycles
	 *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
	 *   hanging if we don't have link and try to do config cycles to
	 *   anything but the PHB.  Only allow talking to the PHB if this is
	 *   set.
	 *  BIG_ENDIAN - cfg_addr is a big endian register
	 *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
	 *   the PLB4.  Effectively disable MRM commands by setting this.
	 *  FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
	 *   link status is in a RC PCIe cfg register (vs being a SoC register)
	 */
#define PPC_INDIRECT_TYPE_SET_CFG_TYPE		0x00000001
#define PPC_INDIRECT_TYPE_EXT_REG		0x00000002
#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS	0x00000004
#define PPC_INDIRECT_TYPE_NO_PCIE_LINK		0x00000008
#define PPC_INDIRECT_TYPE_BIG_ENDIAN		0x00000010
#define PPC_INDIRECT_TYPE_BROKEN_MRM		0x00000020
#define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK	0x00000040
	u32 indirect_type;
	/* Currently, we limit ourselves to 1 IO range and 3 mem
	 * ranges since the common pci_bus structure can't handle more
	 */
	struct resource	io_resource;
	struct resource mem_resources[3];
	resource_size_t mem_offset[3];
	int global_number;		/* PCI domain number */

	resource_size_t dma_window_base_cur;
	resource_size_t dma_window_size;

#ifdef CONFIG_PPC64
	unsigned long buid;
	struct pci_dn *pci_data;
#endif	/* CONFIG_PPC64 */

	void *private_data;
};

/* These are used for config access before all the PCI probing
   has been done. */
extern int early_read_config_byte(struct pci_controller *hose, int bus,
			int dev_fn, int where, u8 *val);
extern int early_read_config_word(struct pci_controller *hose, int bus,
			int dev_fn, int where, u16 *val);
extern int early_read_config_dword(struct pci_controller *hose, int bus,
			int dev_fn, int where, u32 *val);
extern int early_write_config_byte(struct pci_controller *hose, int bus,
			int dev_fn, int where, u8 val);
extern int early_write_config_word(struct pci_controller *hose, int bus,
			int dev_fn, int where, u16 val);
extern int early_write_config_dword(struct pci_controller *hose, int bus,
			int dev_fn, int where, u32 val);

extern int early_find_capability(struct pci_controller *hose, int bus,
				 int dev_fn, int cap);

extern void setup_indirect_pci(struct pci_controller* hose,
			       resource_size_t cfg_addr,
			       resource_size_t cfg_data, u32 flags);

extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
				int offset, int len, u32 *val);

extern int __indirect_read_config(struct pci_controller *hose,
				  unsigned char bus_number, unsigned int devfn,
				  int offset, int len, u32 *val);

extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
				 int offset, int len, u32 val);

static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
{
	return bus->sysdata;
}

#ifndef CONFIG_PPC64

extern int pci_device_from_OF_node(struct device_node *node,
				   u8 *bus, u8 *devfn);
extern void pci_create_OF_bus_map(void);

static inline int isa_vaddr_is_ioport(void __iomem *address)
{
	/* No specific ISA handling on ppc32 at this stage, it
	 * all goes through PCI
	 */
	return 0;
}

#else	/* CONFIG_PPC64 */

/*
 * PCI stuff, for nodes representing PCI devices, pointed to
 * by device_node->data.
 */
struct iommu_table;

struct pci_dn {
	int     flags;

	int	busno;			/* pci bus number */
	int	devfn;			/* pci device and function number */
	int	vendor_id;		/* Vendor ID */
	int	device_id;		/* Device ID */
	int	class_code;		/* Device class code */

	struct  pci_dn *parent;
	struct  pci_controller *phb;	/* for pci devices */
	struct	iommu_table *iommu_table;	/* for phb's or bridges */
	struct	device_node *node;	/* back-pointer to the device_node */

	int	pci_ext_config_space;	/* for pci devices */

	struct	pci_dev *pcidev;	/* back-pointer to the pci device */
#ifdef CONFIG_EEH
	struct eeh_dev *edev;		/* eeh device */
#endif
#define IODA_INVALID_PE		(-1)
#ifdef CONFIG_PPC_POWERNV
	int	pe_number;
#endif
	struct list_head child_list;
	struct list_head list;
};

/* Get the pointer to a device_node's pci_dn */
#define PCI_DN(dn)	((struct pci_dn *) (dn)->data)

extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus,
					   int devfn);
extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev);
extern void *update_dn_pci_info(struct device_node *dn, void *data);

static inline int pci_device_from_OF_node(struct device_node *np,
					  u8 *bus, u8 *devfn)
{
	if (!PCI_DN(np))
		return -ENODEV;
	*bus = PCI_DN(np)->busno;
	*devfn = PCI_DN(np)->devfn;
	return 0;
}

#if defined(CONFIG_EEH)
static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn)
{
	return pdn ? pdn->edev : NULL;
}
#else
#define pdn_to_eeh_dev(x)	(NULL)
#endif

/** Find the bus corresponding to the indicated device node */
extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);

/** Remove all of the PCI devices under this bus */
extern void pcibios_remove_pci_devices(struct pci_bus *bus);

/** Discover new pci devices under this bus, and add them */
extern void pcibios_add_pci_devices(struct pci_bus *bus);


extern void isa_bridge_find_early(struct pci_controller *hose);

static inline int isa_vaddr_is_ioport(void __iomem *address)
{
	/* Check if address hits the reserved legacy IO range */
	unsigned long ea = (unsigned long)address;
	return ea >= ISA_IO_BASE && ea < ISA_IO_END;
}

extern int pcibios_unmap_io_space(struct pci_bus *bus);
extern int pcibios_map_io_space(struct pci_bus *bus);

#ifdef CONFIG_NUMA
#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = (NODE))
#else
#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = -1)
#endif

#endif	/* CONFIG_PPC64 */

/* Get the PCI host controller for an OF device */
extern struct pci_controller *pci_find_hose_for_OF_device(
			struct device_node* node);

/* Fill up host controller resources from the OF node */
extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
			struct device_node *dev, int primary);

/* Allocate & free a PCI host bridge structure */
extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
extern void pcibios_free_controller(struct pci_controller *phb);

#ifdef CONFIG_PCI
extern int pcibios_vaddr_is_ioport(void __iomem *address);
#else
static inline int pcibios_vaddr_is_ioport(void __iomem *address)
{
	return 0;
}
#endif	/* CONFIG_PCI */

/*
 * Shims to prefer pci_controller version over ppc_md where available.
 */
static inline void pci_dma_dev_setup(struct pci_dev *dev)
{
	struct pci_controller *phb = pci_bus_to_host(dev->bus);

	if (phb->controller_ops.dma_dev_setup)
		phb->controller_ops.dma_dev_setup(dev);
	else if (ppc_md.pci_dma_dev_setup)
		ppc_md.pci_dma_dev_setup(dev);
}

static inline void pci_dma_bus_setup(struct pci_bus *bus)
{
	struct pci_controller *phb = pci_bus_to_host(bus);

	if (phb->controller_ops.dma_bus_setup)
		phb->controller_ops.dma_bus_setup(bus);
	else if (ppc_md.pci_dma_bus_setup)
		ppc_md.pci_dma_bus_setup(bus);
}

static inline int pci_probe_mode(struct pci_bus *bus)
{
	struct pci_controller *phb = pci_bus_to_host(bus);

	if (phb->controller_ops.probe_mode)
		return phb->controller_ops.probe_mode(bus);
	if (ppc_md.pci_probe_mode)
		return ppc_md.pci_probe_mode(bus);
	return PCI_PROBE_NORMAL;
}

static inline bool pcibios_enable_device_hook(struct pci_dev *dev)
{
	struct pci_controller *phb = pci_bus_to_host(dev->bus);

	if (phb->controller_ops.enable_device_hook)
		return phb->controller_ops.enable_device_hook(dev);
	if (ppc_md.pcibios_enable_device_hook)
		return ppc_md.pcibios_enable_device_hook(dev);
	return true;
}

static inline resource_size_t pci_window_alignment(struct pci_bus *bus,
						   unsigned long type)
{
	struct pci_controller *phb = pci_bus_to_host(bus);

	if (phb->controller_ops.window_alignment)
		return phb->controller_ops.window_alignment(bus, type);
	if (ppc_md.pcibios_window_alignment)
		return ppc_md.pcibios_window_alignment(bus, type);

	/*
	 * PCI core will figure out the default
	 * alignment: 4KiB for I/O and 1MiB for
	 * memory window.
	 */
	return 1;
}

static inline void pcibios_reset_secondary_bus_shim(struct pci_dev *dev)
{
	struct pci_controller *phb = pci_bus_to_host(dev->bus);

	if (phb->controller_ops.reset_secondary_bus)
		phb->controller_ops.reset_secondary_bus(dev);
	else if (ppc_md.pcibios_reset_secondary_bus)
		ppc_md.pcibios_reset_secondary_bus(dev);
	else
		/*
		 * Fallback to the generic function if no
		 * platform-specific one is provided
		 */
		pci_reset_secondary_bus(dev);
}

#endif	/* __KERNEL__ */
#endif	/* _ASM_POWERPC_PCI_BRIDGE_H */
Commit	Line	Data
047ea784 PM	1	#ifndef _ASM_POWERPC_PCI_BRIDGE_H
047ea784 PM	2	#define _ASM_POWERPC_PCI_BRIDGE_H
88ced031	3	#ifdef __KERNEL__
7cd1de6b SR	4	/*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version
	8	* 2 of the License, or (at your option) any later version.
	9	*/
5531e41b	10	#include <linux/pci.h>
a4c9e328 KG	11	#include <linux/list.h>
a4c9e328 KG	12	#include <linux/ioport.h>
f4ffd5e5	13	#include <asm-generic/pci-bridge.h>
a4c9e328	14
ff9df8c8 DA	15	/* Return values for pci_controller_ops.probe_mode function */
	16	#define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
	17	#define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
	18	#define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
	19
44ef3390 SR	20	struct device_node;
44ef3390 SR	21
e02def5b DA	22	/*
	23	* PCI controller operations
	24	*/
	25	struct pci_controller_ops {
	26	void (dma_dev_setup)(struct pci_dev dev);
b122c954	27	void (dma_bus_setup)(struct pci_bus bus);
ff9df8c8 DA	28
ff9df8c8 DA	29	int (probe_mode)(struct pci_bus );
b31e79f8 DA	30
	31	/* Called when pci_enable_device() is called. Returns true to
	32	* allow assignment/enabling of the device. */
	33	bool (enable_device_hook)(struct pci_dev );
542070ba DA	34
	35	/* Called during PCI resource reassignment */
	36	resource_size_t (window_alignment)(struct pci_bus , unsigned long type);
cd16c7ba	37	void (reset_secondary_bus)(struct pci_dev dev);
e02def5b DA	38	};
e02def5b DA	39
5531e41b KG	40	/*
	41	* Structure of a PCI controller (host bridge)
	42	*/
	43	struct pci_controller {
	44	struct pci_bus *bus;
a4c9e328	45	char is_dynamic;
7211991f SR	46	#ifdef CONFIG_PPC64
	47	int node;
	48	#endif
44ef3390	49	struct device_node *dn;
a4c9e328	50	struct list_head list_node;
5531e41b KG	51	struct device *parent;
	52
	53	int first_busno;
	54	int last_busno;
	55	int self_busno;
be8e60d8	56	struct resource busn;
5531e41b KG	57
5531e41b KG	58	void __iomem *io_base_virt;
7211991f SR	59	#ifdef CONFIG_PPC64
	60	void *io_base_alloc;
	61	#endif
5531e41b	62	resource_size_t io_base_phys;
13dccb9e	63	resource_size_t pci_io_size;
5531e41b	64
e9f82cb7 BH	65	/* Some machines have a special region to forward the ISA
	66	* "memory" cycles such as VGA memory regions. Left to 0
	67	* if unsupported
	68	*/
	69	resource_size_t isa_mem_phys;
	70	resource_size_t isa_mem_size;
	71
e02def5b	72	struct pci_controller_ops controller_ops;
5531e41b	73	struct pci_ops *ops;
70fbb938 SR	74	unsigned int __iomem *cfg_addr;
70fbb938 SR	75	void __iomem *cfg_data;
5531e41b KG	76
	77	/*
	78	* Used for variants of PCI indirect handling and possible quirks:
	79	* SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
	80	* EXT_REG - provides access to PCI-e extended registers
25985edc	81	* SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
5531e41b KG	82	* on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
	83	* to determine which bus number to match on when generating type0
	84	* config cycles
62c66c8e KG	85	* NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
	86	* hanging if we don't have link and try to do config cycles to
	87	* anything but the PHB. Only allow talking to the PHB if this is
	88	* set.
2e56ff20	89	* BIG_ENDIAN - cfg_addr is a big endian register
5ce4b596 JB	90	* BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
5ce4b596 JB	91	* the PLB4. Effectively disable MRM commands by setting this.
34642bbb KG	92	* FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
34642bbb KG	93	* link status is in a RC PCIe cfg register (vs being a SoC register)
5531e41b	94	*/
7cd1de6b SR	95	#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
	96	#define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
	97	#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
	98	#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
	99	#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
5ce4b596	100	#define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
34642bbb	101	#define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040
5531e41b	102	u32 indirect_type;
5531e41b KG	103	/* Currently, we limit ourselves to 1 IO range and 3 mem
	104	* ranges since the common pci_bus structure can't handle more
	105	*/
	106	struct resource io_resource;
	107	struct resource mem_resources[3];
3fd47f06	108	resource_size_t mem_offset[3];
5516b540	109	int global_number; /* PCI domain number */
89d93347 BB	110
	111	resource_size_t dma_window_base_cur;
	112	resource_size_t dma_window_size;
	113
7211991f SR	114	#ifdef CONFIG_PPC64
7211991f SR	115	unsigned long buid;
cca87d30	116	struct pci_dn *pci_data;
34642bbb	117	#endif /* CONFIG_PPC64 */
7211991f SR	118
7211991f SR	119	void *private_data;
5531e41b KG	120	};
5531e41b KG	121
5531e41b KG	122	/* These are used for config access before all the PCI probing
5531e41b KG	123	has been done. */
7cd1de6b SR	124	extern int early_read_config_byte(struct pci_controller *hose, int bus,
	125	int dev_fn, int where, u8 *val);
	126	extern int early_read_config_word(struct pci_controller *hose, int bus,
	127	int dev_fn, int where, u16 *val);
	128	extern int early_read_config_dword(struct pci_controller *hose, int bus,
	129	int dev_fn, int where, u32 *val);
	130	extern int early_write_config_byte(struct pci_controller *hose, int bus,
	131	int dev_fn, int where, u8 val);
	132	extern int early_write_config_word(struct pci_controller *hose, int bus,
	133	int dev_fn, int where, u16 val);
	134	extern int early_write_config_dword(struct pci_controller *hose, int bus,
	135	int dev_fn, int where, u32 val);
5531e41b	136
38805e5f KG	137	extern int early_find_capability(struct pci_controller *hose, int bus,
	138	int dev_fn, int cap);
	139
5531e41b	140	extern void setup_indirect_pci(struct pci_controller* hose,
d94bad82 VB	141	resource_size_t cfg_addr,
d94bad82 VB	142	resource_size_t cfg_data, u32 flags);
89c2dd62	143
50d8f87d RI	144	extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
	145	int offset, int len, u32 *val);
	146
6d5f6a0e KP	147	extern int __indirect_read_config(struct pci_controller *hose,
	148	unsigned char bus_number, unsigned int devfn,
	149	int offset, int len, u32 *val);
	150
50d8f87d RI	151	extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
	152	int offset, int len, u32 val);
	153
89c2dd62 KG	154	static inline struct pci_controller pci_bus_to_host(const struct pci_bus bus)
	155	{
	156	return bus->sysdata;
	157	}
	158
98d9f30c BH	159	#ifndef CONFIG_PPC64
	160
	161	extern int pci_device_from_OF_node(struct device_node *node,
	162	u8 bus, u8 devfn);
	163	extern void pci_create_OF_bus_map(void);
	164
89c2dd62 KG	165	static inline int isa_vaddr_is_ioport(void __iomem *address)
	166	{
	167	/* No specific ISA handling on ppc32 at this stage, it
	168	* all goes through PCI
	169	*/
	170	return 0;
	171	}
	172
7cd1de6b	173	#else /* CONFIG_PPC64 */
1da177e4	174
1635317f PM	175	/*
	176	* PCI stuff, for nodes representing PCI devices, pointed to
	177	* by device_node->data.
	178	*/
1635317f PM	179	struct iommu_table;
	180
	181	struct pci_dn {
cca87d30 GS	182	int flags;
cca87d30 GS	183
7684b40c	184	int busno; /* pci bus number */
7684b40c	185	int devfn; /* pci device and function number */
c035ff1d GS	186	int vendor_id; /* Vendor ID */
	187	int device_id; /* Device ID */
	188	int class_code; /* Device class code */
b5166cc2	189
cca87d30	190	struct pci_dn *parent;
c2e221e8 LV	191	struct pci_controller phb; / for pci devices */
c2e221e8 LV	192	struct iommu_table iommu_table; / for phb's or bridges */
c2e221e8 LV	193	struct device_node node; / back-pointer to the device_node */
	194
	195	int pci_ext_config_space; /* for pci devices */
	196
b6ed42a7	197	struct pci_dev pcidev; / back-pointer to the pci device */
184cd4a3	198	#ifdef CONFIG_EEH
2a0352fa	199	struct eeh_dev edev; / eeh device */
c2e221e8	200	#endif
184cd4a3 BH	201	#define IODA_INVALID_PE (-1)
	202	#ifdef CONFIG_PPC_POWERNV
	203	int pe_number;
	204	#endif
cca87d30 GS	205	struct list_head child_list;
cca87d30 GS	206	struct list_head list;
1635317f PM	207	};
	208
	209	/* Get the pointer to a device_node's pci_dn */
	210	#define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
	211
cca87d30 GS	212	extern struct pci_dn pci_get_pdn_by_devfn(struct pci_bus bus,
cca87d30 GS	213	int devfn);
b72c1f65	214	extern struct pci_dn pci_get_pdn(struct pci_dev pdev);
cca87d30	215	extern void update_dn_pci_info(struct device_node dn, void *data);
1da177e4	216
40ef8cbc PM	217	static inline int pci_device_from_OF_node(struct device_node *np,
	218	u8 bus, u8 devfn)
	219	{
	220	if (!PCI_DN(np))
	221	return -ENODEV;
	222	*bus = PCI_DN(np)->busno;
	223	*devfn = PCI_DN(np)->devfn;
	224	return 0;
	225	}
	226
2a0352fa	227	#if defined(CONFIG_EEH)
e8e9b34c GS	228	static inline struct eeh_dev pdn_to_eeh_dev(struct pci_dn pdn)
	229	{
	230	return pdn ? pdn->edev : NULL;
	231	}
f8f7d63f	232	#else
e8e9b34c	233	#define pdn_to_eeh_dev(x) (NULL)
2a0352fa GS	234	#endif
2a0352fa GS	235
2bf6a8fa	236	/** Find the bus corresponding to the indicated device node */
7cd1de6b	237	extern struct pci_bus pcibios_find_pci_bus(struct device_node dn);
2bf6a8fa	238
2bf6a8fa	239	/** Remove all of the PCI devices under this bus */
7cd1de6b	240	extern void pcibios_remove_pci_devices(struct pci_bus *bus);
2bf6a8fa LV	241
2bf6a8fa LV	242	/** Discover new pci devices under this bus, and add them */
7cd1de6b	243	extern void pcibios_add_pci_devices(struct pci_bus *bus);
1da177e4	244
b5166cc2	245
3d5134ee BH	246	extern void isa_bridge_find_early(struct pci_controller *hose);
3d5134ee BH	247
6dfbde20 BH	248	static inline int isa_vaddr_is_ioport(void __iomem *address)
	249	{
	250	/* Check if address hits the reserved legacy IO range */
	251	unsigned long ea = (unsigned long)address;
	252	return ea >= ISA_IO_BASE && ea < ISA_IO_END;
	253	}
	254
3d5134ee BH	255	extern int pcibios_unmap_io_space(struct pci_bus *bus);
	256	extern int pcibios_map_io_space(struct pci_bus *bus);
	257
357518fa AB	258	#ifdef CONFIG_NUMA
	259	#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
	260	#else
	261	#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
	262	#endif
	263
7cd1de6b	264	#endif /* CONFIG_PPC64 */
5531e41b KG	265
5531e41b KG	266	/* Get the PCI host controller for an OF device */
7cd1de6b SR	267	extern struct pci_controller *pci_find_hose_for_OF_device(
7cd1de6b SR	268	struct device_node* node);
5531e41b KG	269
5531e41b KG	270	/* Fill up host controller resources from the OF node */
7cd1de6b SR	271	extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
7cd1de6b SR	272	struct device_node *dev, int primary);
5531e41b	273
5131d4d8	274	/* Allocate & free a PCI host bridge structure */
7cd1de6b	275	extern struct pci_controller pcibios_alloc_controller(struct device_node dev);
5131d4d8 BH	276	extern void pcibios_free_controller(struct pci_controller *phb);
5131d4d8 BH	277
5531e41b	278	#ifdef CONFIG_PCI
6dfbde20	279	extern int pcibios_vaddr_is_ioport(void __iomem *address);
5531e41b	280	#else
6dfbde20 BH	281	static inline int pcibios_vaddr_is_ioport(void __iomem *address)
	282	{
	283	return 0;
	284	}
7cd1de6b	285	#endif /* CONFIG_PCI */
5531e41b	286
e02def5b DA	287	/*
	288	* Shims to prefer pci_controller version over ppc_md where available.
	289	*/
	290	static inline void pci_dma_dev_setup(struct pci_dev *dev)
	291	{
	292	struct pci_controller *phb = pci_bus_to_host(dev->bus);
	293
	294	if (phb->controller_ops.dma_dev_setup)
	295	phb->controller_ops.dma_dev_setup(dev);
	296	else if (ppc_md.pci_dma_dev_setup)
	297	ppc_md.pci_dma_dev_setup(dev);
	298	}
	299
b122c954 DA	300	static inline void pci_dma_bus_setup(struct pci_bus *bus)
	301	{
	302	struct pci_controller *phb = pci_bus_to_host(bus);
	303
	304	if (phb->controller_ops.dma_bus_setup)
	305	phb->controller_ops.dma_bus_setup(bus);
	306	else if (ppc_md.pci_dma_bus_setup)
	307	ppc_md.pci_dma_bus_setup(bus);
	308	}
	309
ff9df8c8 DA	310	static inline int pci_probe_mode(struct pci_bus *bus)
	311	{
	312	struct pci_controller *phb = pci_bus_to_host(bus);
	313
	314	if (phb->controller_ops.probe_mode)
	315	return phb->controller_ops.probe_mode(bus);
	316	if (ppc_md.pci_probe_mode)
	317	return ppc_md.pci_probe_mode(bus);
	318	return PCI_PROBE_NORMAL;
	319	}
	320
b31e79f8 DA	321	static inline bool pcibios_enable_device_hook(struct pci_dev *dev)
	322	{
	323	struct pci_controller *phb = pci_bus_to_host(dev->bus);
	324
	325	if (phb->controller_ops.enable_device_hook)
	326	return phb->controller_ops.enable_device_hook(dev);
	327	if (ppc_md.pcibios_enable_device_hook)
	328	return ppc_md.pcibios_enable_device_hook(dev);
	329	return true;
	330	}
	331
542070ba DA	332	static inline resource_size_t pci_window_alignment(struct pci_bus *bus,
	333	unsigned long type)
	334	{
	335	struct pci_controller *phb = pci_bus_to_host(bus);
	336
	337	if (phb->controller_ops.window_alignment)
	338	return phb->controller_ops.window_alignment(bus, type);
	339	if (ppc_md.pcibios_window_alignment)
	340	return ppc_md.pcibios_window_alignment(bus, type);
	341
	342	/*
	343	* PCI core will figure out the default
	344	* alignment: 4KiB for I/O and 1MiB for
	345	* memory window.
	346	*/
	347	return 1;
	348	}
	349
cd16c7ba DA	350	static inline void pcibios_reset_secondary_bus_shim(struct pci_dev *dev)
	351	{
	352	struct pci_controller *phb = pci_bus_to_host(dev->bus);
	353
	354	if (phb->controller_ops.reset_secondary_bus)
	355	phb->controller_ops.reset_secondary_bus(dev);
	356	else if (ppc_md.pcibios_reset_secondary_bus)
	357	ppc_md.pcibios_reset_secondary_bus(dev);
	358	else
	359	/*
	360	* Fallback to the generic function if no
	361	* platform-specific one is provided
	362	*/
	363	pci_reset_secondary_bus(dev);
	364	}
	365
7cd1de6b SR	366	#endif /* __KERNEL__ */
7cd1de6b SR	367	#endif /* _ASM_POWERPC_PCI_BRIDGE_H */