[deliverable/linux.git] / arch / powerpc / include / asm / pgtable-ppc32.h

#ifndef _ASM_POWERPC_PGTABLE_PPC32_H
#define _ASM_POWERPC_PGTABLE_PPC32_H

#include <asm-generic/pgtable-nopmd.h>

#ifndef __ASSEMBLY__
#include <linux/sched.h>
#include <linux/threads.h>
#include <asm/io.h>			/* For sub-arch specific PPC_PIN_SIZE */

extern unsigned long va_to_phys(unsigned long address);
extern pte_t *va_to_pte(unsigned long address);
extern unsigned long ioremap_bot, ioremap_base;

#ifdef CONFIG_44x
extern int icache_44x_need_flush;
#endif

#endif /* __ASSEMBLY__ */

/*
 * The normal case is that PTEs are 32-bits and we have a 1-page
 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages.  -- paulus
 *
 * For any >32-bit physical address platform, we can use the following
 * two level page table layout where the pgdir is 8KB and the MS 13 bits
 * are an index to the second level table.  The combined pgdir/pmd first
 * level has 2048 entries and the second level has 512 64-bit PTE entries.
 * -Matt
 */
/* PGDIR_SHIFT determines what a top-level page table entry can map */
#define PGDIR_SHIFT	(PAGE_SHIFT + PTE_SHIFT)
#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
#define PGDIR_MASK	(~(PGDIR_SIZE-1))

/*
 * entries per page directory level: our page-table tree is two-level, so
 * we don't really have any PMD directory.
 */
#ifndef __ASSEMBLY__
#define PTE_TABLE_SIZE	(sizeof(pte_t) << PTE_SHIFT)
#define PGD_TABLE_SIZE	(sizeof(pgd_t) << (32 - PGDIR_SHIFT))
#endif	/* __ASSEMBLY__ */

#define PTRS_PER_PTE	(1 << PTE_SHIFT)
#define PTRS_PER_PMD	1
#define PTRS_PER_PGD	(1 << (32 - PGDIR_SHIFT))

#define USER_PTRS_PER_PGD	(TASK_SIZE / PGDIR_SIZE)
#define FIRST_USER_ADDRESS	0

#define pte_ERROR(e) \
	printk("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
		(unsigned long long)pte_val(e))
#define pgd_ERROR(e) \
	printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))

/*
 * Just any arbitrary offset to the start of the vmalloc VM area: the
 * current 64MB value just means that there will be a 64MB "hole" after the
 * physical memory until the kernel virtual memory starts.  That means that
 * any out-of-bounds memory accesses will hopefully be caught.
 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
 * area for the same reason. ;)
 *
 * We no longer map larger than phys RAM with the BATs so we don't have
 * to worry about the VMALLOC_OFFSET causing problems.  We do have to worry
 * about clashes between our early calls to ioremap() that start growing down
 * from ioremap_base being run into the VM area allocations (growing upwards
 * from VMALLOC_START).  For this reason we have ioremap_bot to check when
 * we actually run into our mappings setup in the early boot with the VM
 * system.  This really does become a problem for machines with good amounts
 * of RAM.  -- Cort
 */
#define VMALLOC_OFFSET (0x1000000) /* 16M */
#ifdef PPC_PIN_SIZE
#define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
#else
#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
#endif
#define VMALLOC_END	ioremap_bot

/*
 * Bits in a linux-style PTE.  These match the bits in the
 * (hardware-defined) PowerPC PTE as closely as possible.
 */

#if defined(CONFIG_40x)
#include <asm/pte-40x.h>
#elif defined(CONFIG_44x)
#include <asm/pte-44x.h>
#elif defined(CONFIG_FSL_BOOKE)
#include <asm/pte-fsl-booke.h>
#elif defined(CONFIG_8xx)
#include <asm/pte-8xx.h>
#else /* CONFIG_6xx */
#include <asm/pte-hash32.h>
#endif

/* If _PAGE_SPECIAL is defined, then we advertise our support for it */
#ifdef _PAGE_SPECIAL
#define __HAVE_ARCH_PTE_SPECIAL
#endif

/*
 * Some bits are only used on some cpu families... Make sure that all
 * the undefined gets defined as 0
 */
#ifndef _PAGE_HASHPTE
#define _PAGE_HASHPTE	0
#endif
#ifndef _PTE_NONE_MASK
#define _PTE_NONE_MASK 0
#endif
#ifndef _PAGE_SHARED
#define _PAGE_SHARED	0
#endif
#ifndef _PAGE_HWWRITE
#define _PAGE_HWWRITE	0
#endif
#ifndef _PAGE_HWEXEC
#define _PAGE_HWEXEC	0
#endif
#ifndef _PAGE_EXEC
#define _PAGE_EXEC	0
#endif
#ifndef _PAGE_ENDIAN
#define _PAGE_ENDIAN	0
#endif
#ifndef _PAGE_COHERENT
#define _PAGE_COHERENT	0
#endif
#ifndef _PAGE_WRITETHRU
#define _PAGE_WRITETHRU	0
#endif
#ifndef _PAGE_SPECIAL
#define _PAGE_SPECIAL	0
#endif
#ifndef _PMD_PRESENT_MASK
#define _PMD_PRESENT_MASK	_PMD_PRESENT
#endif
#ifndef _PMD_SIZE
#define _PMD_SIZE	0
#define PMD_PAGE_SIZE(pmd)	bad_call_to_PMD_PAGE_SIZE()
#endif

#ifndef _PAGE_KERNEL_RO
#define _PAGE_KERNEL_RO	0
#endif
#ifndef _PAGE_KERNEL_RW
#define _PAGE_KERNEL_RW	(_PAGE_DIRTY | _PAGE_RW | _PAGE_HWWRITE)
#endif

#define _PAGE_HPTEFLAGS _PAGE_HASHPTE

/* Location of the PFN in the PTE. Most platforms use the same as _PAGE_SHIFT
 * here (ie, naturally aligned). Platform who don't just pre-define the
 * value so we don't override it here
 */
#ifndef PTE_RPN_SHIFT
#define PTE_RPN_SHIFT	(PAGE_SHIFT)
#endif

#ifdef CONFIG_PTE_64BIT
#define PTE_RPN_MAX	(1ULL << (64 - PTE_RPN_SHIFT))
#define PTE_RPN_MASK	(~((1ULL<<PTE_RPN_SHIFT)-1))
#else
#define PTE_RPN_MAX	(1UL << (32 - PTE_RPN_SHIFT))
#define PTE_RPN_MASK	(~((1UL<<PTE_RPN_SHIFT)-1))
#endif

/* _PAGE_CHG_MASK masks of bits that are to be preserved accross
 * pgprot changes
 */
#define _PAGE_CHG_MASK	(PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
                         _PAGE_ACCESSED | _PAGE_SPECIAL)

/* Mask of bits returned by pte_pgprot() */
#define PAGE_PROT_BITS	(_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \
			 _PAGE_WRITETHRU | _PAGE_ENDIAN | \
			 _PAGE_USER | _PAGE_ACCESSED | \
			 _PAGE_RW | _PAGE_HWWRITE | _PAGE_DIRTY | \
			 _PAGE_EXEC | _PAGE_HWEXEC)

/*
 * We define 2 sets of base prot bits, one for basic pages (ie,
 * cacheable kernel and user pages) and one for non cacheable
 * pages. We always set _PAGE_COHERENT when SMP is enabled or
 * the processor might need it for DMA coherency.
 */
#if defined(CONFIG_SMP) || defined(CONFIG_PPC_STD_MMU)
#define _PAGE_BASE	(_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT)
#else
#define _PAGE_BASE	(_PAGE_PRESENT | _PAGE_ACCESSED)
#endif
#define _PAGE_BASE_NC	(_PAGE_PRESENT | _PAGE_ACCESSED)

/* Permission masks used for kernel mappings */
#define PAGE_KERNEL	__pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
#define PAGE_KERNEL_NC	__pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
				 _PAGE_NO_CACHE)
#define PAGE_KERNEL_NCG	__pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
				 _PAGE_NO_CACHE | _PAGE_GUARDED)
#define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW | _PAGE_EXEC)
#define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
#define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO | _PAGE_EXEC)

#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\
	defined(CONFIG_KPROBES)
/* We want the debuggers to be able to set breakpoints anywhere, so
 * don't write protect the kernel text */
#define PAGE_KERNEL_TEXT	PAGE_KERNEL_X
#else
#define PAGE_KERNEL_TEXT	PAGE_KERNEL_ROX
#endif

#define PAGE_NONE	__pgprot(_PAGE_BASE)
#define PAGE_READONLY	__pgprot(_PAGE_BASE | _PAGE_USER)
#define PAGE_READONLY_X	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
#define PAGE_SHARED	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
#define PAGE_SHARED_X	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
#define PAGE_COPY	__pgprot(_PAGE_BASE | _PAGE_USER)
#define PAGE_COPY_X	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)

/*
 * The PowerPC can only do execute protection on a segment (256MB) basis,
 * not on a page basis.  So we consider execute permission the same as read.
 * Also, write permissions imply read permissions.
 * This is the closest we can get..
 */
#define __P000	PAGE_NONE
#define __P001	PAGE_READONLY_X
#define __P010	PAGE_COPY
#define __P011	PAGE_COPY_X
#define __P100	PAGE_READONLY
#define __P101	PAGE_READONLY_X
#define __P110	PAGE_COPY
#define __P111	PAGE_COPY_X

#define __S000	PAGE_NONE
#define __S001	PAGE_READONLY_X
#define __S010	PAGE_SHARED
#define __S011	PAGE_SHARED_X
#define __S100	PAGE_READONLY
#define __S101	PAGE_READONLY_X
#define __S110	PAGE_SHARED
#define __S111	PAGE_SHARED_X

#ifndef __ASSEMBLY__
/* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a
 * kernel without large page PMD support */
extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);

/*
 * Conversions between PTE values and page frame numbers.
 */

#define pte_pfn(x)		(pte_val(x) >> PTE_RPN_SHIFT)
#define pte_page(x)		pfn_to_page(pte_pfn(x))

#define pfn_pte(pfn, prot)	__pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) |\
					pgprot_val(prot))
#define mk_pte(page, prot)	pfn_pte(page_to_pfn(page), prot)
#endif /* __ASSEMBLY__ */

#define pte_none(pte)		((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
#define pte_present(pte)	(pte_val(pte) & _PAGE_PRESENT)
#define pte_clear(mm, addr, ptep) \
	do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)

#define pmd_none(pmd)		(!pmd_val(pmd))
#define	pmd_bad(pmd)		(pmd_val(pmd) & _PMD_BAD)
#define	pmd_present(pmd)	(pmd_val(pmd) & _PMD_PRESENT_MASK)
#define	pmd_clear(pmdp)		do { pmd_val(*(pmdp)) = 0; } while (0)

#ifndef __ASSEMBLY__
/*
 * The following only work if pte_present() is true.
 * Undefined behaviour if not..
 */
static inline int pte_write(pte_t pte)		{ return pte_val(pte) & _PAGE_RW; }
static inline int pte_dirty(pte_t pte)		{ return pte_val(pte) & _PAGE_DIRTY; }
static inline int pte_young(pte_t pte)		{ return pte_val(pte) & _PAGE_ACCESSED; }
static inline int pte_file(pte_t pte)		{ return pte_val(pte) & _PAGE_FILE; }
static inline int pte_special(pte_t pte)	{ return pte_val(pte) & _PAGE_SPECIAL; }

static inline pte_t pte_wrprotect(pte_t pte) {
	pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
static inline pte_t pte_mkclean(pte_t pte) {
	pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
static inline pte_t pte_mkold(pte_t pte) {
	pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }

static inline pte_t pte_mkwrite(pte_t pte) {
	pte_val(pte) |= _PAGE_RW; return pte; }
static inline pte_t pte_mkdirty(pte_t pte) {
	pte_val(pte) |= _PAGE_DIRTY; return pte; }
static inline pte_t pte_mkyoung(pte_t pte) {
	pte_val(pte) |= _PAGE_ACCESSED; return pte; }
static inline pte_t pte_mkspecial(pte_t pte) {
	pte_val(pte) |= _PAGE_SPECIAL; return pte; }
static inline pgprot_t pte_pgprot(pte_t pte)
{
	return __pgprot(pte_val(pte) & PAGE_PROT_BITS);
}

static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
	pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
	return pte;
}

/*
 * When flushing the tlb entry for a page, we also need to flush the hash
 * table entry.  flush_hash_pages is assembler (for speed) in hashtable.S.
 */
extern int flush_hash_pages(unsigned context, unsigned long va,
			    unsigned long pmdval, int count);

/* Add an HPTE to the hash table */
extern void add_hash_page(unsigned context, unsigned long va,
			  unsigned long pmdval);

/* Flush an entry from the TLB/hash table */
extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
			     unsigned long address);

/*
 * PTE updates. This function is called whenever an existing
 * valid PTE is updated. This does -not- include set_pte_at()
 * which nowadays only sets a new PTE.
 *
 * Depending on the type of MMU, we may need to use atomic updates
 * and the PTE may be either 32 or 64 bit wide. In the later case,
 * when using atomic updates, only the low part of the PTE is
 * accessed atomically.
 *
 * In addition, on 44x, we also maintain a global flag indicating
 * that an executable user mapping was modified, which is needed
 * to properly flush the virtually tagged instruction cache of
 * those implementations.
 */
#ifndef CONFIG_PTE_64BIT
static inline unsigned long pte_update(pte_t *p,
				       unsigned long clr,
				       unsigned long set)
{
#ifdef PTE_ATOMIC_UPDATES
	unsigned long old, tmp;

	__asm__ __volatile__("\
1:	lwarx	%0,0,%3\n\
	andc	%1,%0,%4\n\
	or	%1,%1,%5\n"
	PPC405_ERR77(0,%3)
"	stwcx.	%1,0,%3\n\
	bne-	1b"
	: "=&r" (old), "=&r" (tmp), "=m" (*p)
	: "r" (p), "r" (clr), "r" (set), "m" (*p)
	: "cc" );
#else /* PTE_ATOMIC_UPDATES */
	unsigned long old = pte_val(*p);
	*p = __pte((old & ~clr) | set);
#endif /* !PTE_ATOMIC_UPDATES */

#ifdef CONFIG_44x
	if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
		icache_44x_need_flush = 1;
#endif
	return old;
}
#else /* CONFIG_PTE_64BIT */
static inline unsigned long long pte_update(pte_t *p,
					    unsigned long clr,
					    unsigned long set)
{
#ifdef PTE_ATOMIC_UPDATES
	unsigned long long old;
	unsigned long tmp;

	__asm__ __volatile__("\
1:	lwarx	%L0,0,%4\n\
	lwzx	%0,0,%3\n\
	andc	%1,%L0,%5\n\
	or	%1,%1,%6\n"
	PPC405_ERR77(0,%3)
"	stwcx.	%1,0,%4\n\
	bne-	1b"
	: "=&r" (old), "=&r" (tmp), "=m" (*p)
	: "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
	: "cc" );
#else /* PTE_ATOMIC_UPDATES */
	unsigned long long old = pte_val(*p);
	*p = __pte((old & ~(unsigned long long)clr) | set);
#endif /* !PTE_ATOMIC_UPDATES */

#ifdef CONFIG_44x
	if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
		icache_44x_need_flush = 1;
#endif
	return old;
}
#endif /* CONFIG_PTE_64BIT */

/*
 * 2.6 calls this without flushing the TLB entry; this is wrong
 * for our hash-based implementation, we fix that up here.
 */
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
{
	unsigned long old;
	old = pte_update(ptep, _PAGE_ACCESSED, 0);
#if _PAGE_HASHPTE != 0
	if (old & _PAGE_HASHPTE) {
		unsigned long ptephys = __pa(ptep) & PAGE_MASK;
		flush_hash_pages(context, addr, ptephys, 1);
	}
#endif
	return (old & _PAGE_ACCESSED) != 0;
}
#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
	__ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)

#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
				       pte_t *ptep)
{
	return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
}

#define __HAVE_ARCH_PTEP_SET_WRPROTECT
static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
				      pte_t *ptep)
{
	pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
}
static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
					   unsigned long addr, pte_t *ptep)
{
	ptep_set_wrprotect(mm, addr, ptep);
}


static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
{
	unsigned long bits = pte_val(entry) &
		(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW |
		 _PAGE_HWEXEC | _PAGE_EXEC);
	pte_update(ptep, 0, bits);
}

#define __HAVE_ARCH_PTE_SAME
#define pte_same(A,B)	(((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)

/*
 * Note that on Book E processors, the pmd contains the kernel virtual
 * (lowmem) address of the pte page.  The physical address is less useful
 * because everything runs with translation enabled (even the TLB miss
 * handler).  On everything else the pmd contains the physical address
 * of the pte page.  -- paulus
 */
#ifndef CONFIG_BOOKE
#define pmd_page_vaddr(pmd)	\
	((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
#define pmd_page(pmd)		\
	(mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
#else
#define pmd_page_vaddr(pmd)	\
	((unsigned long) (pmd_val(pmd) & PAGE_MASK))
#define pmd_page(pmd)		\
	pfn_to_page((__pa(pmd_val(pmd)) >> PAGE_SHIFT))
#endif

/* to find an entry in a kernel page-table-directory */
#define pgd_offset_k(address) pgd_offset(&init_mm, address)

/* to find an entry in a page-table-directory */
#define pgd_index(address)	 ((address) >> PGDIR_SHIFT)
#define pgd_offset(mm, address)	 ((mm)->pgd + pgd_index(address))

/* Find an entry in the third-level page table.. */
#define pte_index(address)		\
	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
#define pte_offset_kernel(dir, addr)	\
	((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
#define pte_offset_map(dir, addr)		\
	((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr))
#define pte_offset_map_nested(dir, addr)	\
	((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr))

#define pte_unmap(pte)		kunmap_atomic(pte, KM_PTE0)
#define pte_unmap_nested(pte)	kunmap_atomic(pte, KM_PTE1)

/*
 * Encode and decode a swap entry.
 * Note that the bits we use in a PTE for representing a swap entry
 * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the
 *_PAGE_HASHPTE bit (if used).  -- paulus
 */
#define __swp_type(entry)		((entry).val & 0x1f)
#define __swp_offset(entry)		((entry).val >> 5)
#define __swp_entry(type, offset)	((swp_entry_t) { (type) | ((offset) << 5) })
#define __pte_to_swp_entry(pte)		((swp_entry_t) { pte_val(pte) >> 3 })
#define __swp_entry_to_pte(x)		((pte_t) { (x).val << 3 })

/* Encode and decode a nonlinear file mapping entry */
#define PTE_FILE_MAX_BITS	29
#define pte_to_pgoff(pte)	(pte_val(pte) >> 3)
#define pgoff_to_pte(off)	((pte_t) { ((off) << 3) | _PAGE_FILE })

/*
 * No page table caches to initialise
 */
#define pgtable_cache_init()	do { } while (0)

extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep,
		      pmd_t **pmdp);

#endif /* !__ASSEMBLY__ */

#endif /* _ASM_POWERPC_PGTABLE_PPC32_H */
Commit	Line	Data
f88df14b DG	1	#ifndef _ASM_POWERPC_PGTABLE_PPC32_H
	2	#define _ASM_POWERPC_PGTABLE_PPC32_H
	3
d1953c88	4	#include <asm-generic/pgtable-nopmd.h>
f88df14b DG	5
	6	#ifndef __ASSEMBLY__
	7	#include <linux/sched.h>
	8	#include <linux/threads.h>
f88df14b	9	#include <asm/io.h> /* For sub-arch specific PPC_PIN_SIZE */
f88df14b DG	10
	11	extern unsigned long va_to_phys(unsigned long address);
	12	extern pte_t *va_to_pte(unsigned long address);
	13	extern unsigned long ioremap_bot, ioremap_base;
b98ac05d BH	14
	15	#ifdef CONFIG_44x
	16	extern int icache_44x_need_flush;
	17	#endif
	18
f88df14b DG	19	#endif /* __ASSEMBLY__ */
f88df14b DG	20
f88df14b DG	21	/*
	22	* The normal case is that PTEs are 32-bits and we have a 1-page
	23	* 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
	24	*
	25	* For any >32-bit physical address platform, we can use the following
	26	* two level page table layout where the pgdir is 8KB and the MS 13 bits
	27	* are an index to the second level table. The combined pgdir/pmd first
	28	* level has 2048 entries and the second level has 512 64-bit PTE entries.
	29	* -Matt
	30	*/
f88df14b	31	/* PGDIR_SHIFT determines what a top-level page table entry can map */
d1953c88	32	#define PGDIR_SHIFT (PAGE_SHIFT + PTE_SHIFT)
f88df14b DG	33	#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
	34	#define PGDIR_MASK (~(PGDIR_SIZE-1))
	35
	36	/*
	37	* entries per page directory level: our page-table tree is two-level, so
	38	* we don't really have any PMD directory.
	39	*/
bee86f14 KG	40	#ifndef __ASSEMBLY__
	41	#define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_SHIFT)
	42	#define PGD_TABLE_SIZE (sizeof(pgd_t) << (32 - PGDIR_SHIFT))
	43	#endif /* __ASSEMBLY__ */
	44
f88df14b DG	45	#define PTRS_PER_PTE (1 << PTE_SHIFT)
	46	#define PTRS_PER_PMD 1
	47	#define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT))
	48
	49	#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
	50	#define FIRST_USER_ADDRESS 0
	51
f88df14b	52	#define pte_ERROR(e) \
0aeafb0c DG	53	printk("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
0aeafb0c DG	54	(unsigned long long)pte_val(e))
f88df14b DG	55	#define pgd_ERROR(e) \
	56	printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
	57
	58	/*
	59	* Just any arbitrary offset to the start of the vmalloc VM area: the
	60	* current 64MB value just means that there will be a 64MB "hole" after the
	61	* physical memory until the kernel virtual memory starts. That means that
	62	* any out-of-bounds memory accesses will hopefully be caught.
	63	* The vmalloc() routines leaves a hole of 4kB between each vmalloced
	64	* area for the same reason. ;)
	65	*
	66	* We no longer map larger than phys RAM with the BATs so we don't have
	67	* to worry about the VMALLOC_OFFSET causing problems. We do have to worry
	68	* about clashes between our early calls to ioremap() that start growing down
	69	* from ioremap_base being run into the VM area allocations (growing upwards
	70	* from VMALLOC_START). For this reason we have ioremap_bot to check when
	71	* we actually run into our mappings setup in the early boot with the VM
	72	* system. This really does become a problem for machines with good amounts
	73	* of RAM. -- Cort
	74	*/
	75	#define VMALLOC_OFFSET (0x1000000) /* 16M */
	76	#ifdef PPC_PIN_SIZE
	77	#define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
	78	#else
	79	#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
	80	#endif
	81	#define VMALLOC_END ioremap_bot
	82
	83	/*
	84	* Bits in a linux-style PTE. These match the bits in the
	85	* (hardware-defined) PowerPC PTE as closely as possible.
	86	*/
	87
	88	#if defined(CONFIG_40x)
c605782b	89	#include <asm/pte-40x.h>
f88df14b	90	#elif defined(CONFIG_44x)
c605782b	91	#include <asm/pte-44x.h>
f88df14b	92	#elif defined(CONFIG_FSL_BOOKE)
c605782b	93	#include <asm/pte-fsl-booke.h>
f88df14b	94	#elif defined(CONFIG_8xx)
c605782b	95	#include <asm/pte-8xx.h>
f88df14b	96	#else /* CONFIG_6xx */
c605782b	97	#include <asm/pte-hash32.h>
4ee7084e	98	#endif
f88df14b	99
c605782b BH	100	/* If _PAGE_SPECIAL is defined, then we advertise our support for it */
c605782b BH	101	#ifdef _PAGE_SPECIAL
9a62c051	102	#define __HAVE_ARCH_PTE_SPECIAL
f88df14b DG	103	#endif
	104
	105	/*
c605782b BH	106	* Some bits are only used on some cpu families... Make sure that all
c605782b BH	107	* the undefined gets defined as 0
f88df14b DG	108	*/
	109	#ifndef _PAGE_HASHPTE
	110	#define _PAGE_HASHPTE 0
	111	#endif
	112	#ifndef _PTE_NONE_MASK
	113	#define _PTE_NONE_MASK 0
	114	#endif
	115	#ifndef _PAGE_SHARED
	116	#define _PAGE_SHARED 0
	117	#endif
	118	#ifndef _PAGE_HWWRITE
	119	#define _PAGE_HWWRITE 0
	120	#endif
	121	#ifndef _PAGE_HWEXEC
	122	#define _PAGE_HWEXEC 0
	123	#endif
	124	#ifndef _PAGE_EXEC
	125	#define _PAGE_EXEC 0
	126	#endif
a1f242ff BH	127	#ifndef _PAGE_ENDIAN
	128	#define _PAGE_ENDIAN 0
	129	#endif
	130	#ifndef _PAGE_COHERENT
	131	#define _PAGE_COHERENT 0
	132	#endif
ff8dc769 KG	133	#ifndef _PAGE_WRITETHRU
	134	#define _PAGE_WRITETHRU 0
	135	#endif
9a62c051 KG	136	#ifndef _PAGE_SPECIAL
	137	#define _PAGE_SPECIAL 0
	138	#endif
f88df14b DG	139	#ifndef _PMD_PRESENT_MASK
	140	#define _PMD_PRESENT_MASK _PMD_PRESENT
	141	#endif
	142	#ifndef _PMD_SIZE
	143	#define _PMD_SIZE 0
	144	#define PMD_PAGE_SIZE(pmd) bad_call_to_PMD_PAGE_SIZE()
	145	#endif
	146
8d1cf34e BH	147	#ifndef _PAGE_KERNEL_RO
	148	#define _PAGE_KERNEL_RO 0
	149	#endif
	150	#ifndef _PAGE_KERNEL_RW
	151	#define _PAGE_KERNEL_RW (_PAGE_DIRTY \| _PAGE_RW \| _PAGE_HWWRITE)
	152	#endif
	153
8d30c14c BH	154	#define _PAGE_HPTEFLAGS _PAGE_HASHPTE
8d30c14c BH	155
a7d2dac8 BH	156	/* Location of the PFN in the PTE. Most platforms use the same as _PAGE_SHIFT
	157	* here (ie, naturally aligned). Platform who don't just pre-define the
	158	* value so we don't override it here
	159	*/
	160	#ifndef PTE_RPN_SHIFT
	161	#define PTE_RPN_SHIFT (PAGE_SHIFT)
	162	#endif
	163
	164	#ifdef CONFIG_PTE_64BIT
	165	#define PTE_RPN_MAX (1ULL << (64 - PTE_RPN_SHIFT))
	166	#define PTE_RPN_MASK (~((1ULL<<PTE_RPN_SHIFT)-1))
	167	#else
	168	#define PTE_RPN_MAX (1UL << (32 - PTE_RPN_SHIFT))
	169	#define PTE_RPN_MASK (~((1UL<<PTE_RPN_SHIFT)-1))
	170	#endif
a1f242ff	171
a7d2dac8 BH	172	/* _PAGE_CHG_MASK masks of bits that are to be preserved accross
	173	* pgprot changes
	174	*/
	175	#define _PAGE_CHG_MASK (PTE_RPN_MASK \| _PAGE_HPTEFLAGS \| _PAGE_DIRTY \| \
	176	_PAGE_ACCESSED \| _PAGE_SPECIAL)
	177
	178	/* Mask of bits returned by pte_pgprot() */
f5ea64dc DG	179	#define PAGE_PROT_BITS (_PAGE_GUARDED \| _PAGE_COHERENT \| _PAGE_NO_CACHE \| \
	180	_PAGE_WRITETHRU \| _PAGE_ENDIAN \| \
	181	_PAGE_USER \| _PAGE_ACCESSED \| \
	182	_PAGE_RW \| _PAGE_HWWRITE \| _PAGE_DIRTY \| \
	183	_PAGE_EXEC \| _PAGE_HWEXEC)
64b3d0e8	184
f88df14b	185	/*
64b3d0e8 BH	186	* We define 2 sets of base prot bits, one for basic pages (ie,
	187	* cacheable kernel and user pages) and one for non cacheable
	188	* pages. We always set _PAGE_COHERENT when SMP is enabled or
	189	* the processor might need it for DMA coherency.
f88df14b	190	*/
64b3d0e8 BH	191	#if defined(CONFIG_SMP) \|\| defined(CONFIG_PPC_STD_MMU)
64b3d0e8 BH	192	#define _PAGE_BASE (_PAGE_PRESENT \| _PAGE_ACCESSED \| _PAGE_COHERENT)
f88df14b DG	193	#else
	194	#define _PAGE_BASE (_PAGE_PRESENT \| _PAGE_ACCESSED)
	195	#endif
8d1cf34e	196	#define _PAGE_BASE_NC (_PAGE_PRESENT \| _PAGE_ACCESSED)
f88df14b	197
8d1cf34e BH	198	/* Permission masks used for kernel mappings */
	199	#define PAGE_KERNEL __pgprot(_PAGE_BASE \| _PAGE_KERNEL_RW)
	200	#define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC \| _PAGE_KERNEL_RW \| \
	201	_PAGE_NO_CACHE)
	202	#define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC \| _PAGE_KERNEL_RW \| \
	203	_PAGE_NO_CACHE \| _PAGE_GUARDED)
	204	#define PAGE_KERNEL_X __pgprot(_PAGE_BASE \| _PAGE_KERNEL_RW \| _PAGE_EXEC)
	205	#define PAGE_KERNEL_RO __pgprot(_PAGE_BASE \| _PAGE_KERNEL_RO)
	206	#define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE \| _PAGE_KERNEL_RO \| _PAGE_EXEC)
f88df14b	207
221ac329 IN	208	#if defined(CONFIG_KGDB) \|\| defined(CONFIG_XMON) \|\| defined(CONFIG_BDI_SWITCH) \|\|\
221ac329 IN	209	defined(CONFIG_KPROBES)
f88df14b DG	210	/* We want the debuggers to be able to set breakpoints anywhere, so
f88df14b DG	211	* don't write protect the kernel text */
8d1cf34e	212	#define PAGE_KERNEL_TEXT PAGE_KERNEL_X
f88df14b	213	#else
8d1cf34e	214	#define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX
f88df14b DG	215	#endif
	216
	217	#define PAGE_NONE __pgprot(_PAGE_BASE)
	218	#define PAGE_READONLY __pgprot(_PAGE_BASE \| _PAGE_USER)
	219	#define PAGE_READONLY_X __pgprot(_PAGE_BASE \| _PAGE_USER \| _PAGE_EXEC)
	220	#define PAGE_SHARED __pgprot(_PAGE_BASE \| _PAGE_USER \| _PAGE_RW)
	221	#define PAGE_SHARED_X __pgprot(_PAGE_BASE \| _PAGE_USER \| _PAGE_RW \| _PAGE_EXEC)
	222	#define PAGE_COPY __pgprot(_PAGE_BASE \| _PAGE_USER)
	223	#define PAGE_COPY_X __pgprot(_PAGE_BASE \| _PAGE_USER \| _PAGE_EXEC)
	224
f88df14b DG	225	/*
	226	* The PowerPC can only do execute protection on a segment (256MB) basis,
	227	* not on a page basis. So we consider execute permission the same as read.
	228	* Also, write permissions imply read permissions.
	229	* This is the closest we can get..
	230	*/
	231	#define __P000 PAGE_NONE
	232	#define __P001 PAGE_READONLY_X
	233	#define __P010 PAGE_COPY
	234	#define __P011 PAGE_COPY_X
	235	#define __P100 PAGE_READONLY
	236	#define __P101 PAGE_READONLY_X
	237	#define __P110 PAGE_COPY
	238	#define __P111 PAGE_COPY_X
	239
	240	#define __S000 PAGE_NONE
	241	#define __S001 PAGE_READONLY_X
	242	#define __S010 PAGE_SHARED
	243	#define __S011 PAGE_SHARED_X
	244	#define __S100 PAGE_READONLY
	245	#define __S101 PAGE_READONLY_X
	246	#define __S110 PAGE_SHARED
	247	#define __S111 PAGE_SHARED_X
	248
	249	#ifndef __ASSEMBLY__
	250	/* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a
	251	* kernel without large page PMD support */
	252	extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
	253
	254	/*
	255	* Conversions between PTE values and page frame numbers.
	256	*/
	257
a7d2dac8	258	#define pte_pfn(x) (pte_val(x) >> PTE_RPN_SHIFT)
f88df14b DG	259	#define pte_page(x) pfn_to_page(pte_pfn(x))
f88df14b DG	260
a7d2dac8	261	#define pfn_pte(pfn, prot) __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) \|\
f88df14b DG	262	pgprot_val(prot))
f88df14b DG	263	#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
f88df14b DG	264	#endif /* __ASSEMBLY__ */
	265
	266	#define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
	267	#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
9bf2b5cd KG	268	#define pte_clear(mm, addr, ptep) \
9bf2b5cd KG	269	do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)
f88df14b DG	270
	271	#define pmd_none(pmd) (!pmd_val(pmd))
	272	#define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD)
	273	#define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK)
	274	#define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0)
	275
	276	#ifndef __ASSEMBLY__
f88df14b DG	277	/*
	278	* The following only work if pte_present() is true.
	279	* Undefined behaviour if not..
	280	*/
f88df14b	281	static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; }
f88df14b DG	282	static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
	283	static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
	284	static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
9a62c051	285	static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; }
f88df14b	286
f88df14b DG	287	static inline pte_t pte_wrprotect(pte_t pte) {
f88df14b DG	288	pte_val(pte) &= ~(_PAGE_RW \| _PAGE_HWWRITE); return pte; }
f88df14b DG	289	static inline pte_t pte_mkclean(pte_t pte) {
	290	pte_val(pte) &= ~(_PAGE_DIRTY \| _PAGE_HWWRITE); return pte; }
	291	static inline pte_t pte_mkold(pte_t pte) {
	292	pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
	293
f88df14b DG	294	static inline pte_t pte_mkwrite(pte_t pte) {
	295	pte_val(pte) \|= _PAGE_RW; return pte; }
	296	static inline pte_t pte_mkdirty(pte_t pte) {
	297	pte_val(pte) \|= _PAGE_DIRTY; return pte; }
	298	static inline pte_t pte_mkyoung(pte_t pte) {
	299	pte_val(pte) \|= _PAGE_ACCESSED; return pte; }
7e675137	300	static inline pte_t pte_mkspecial(pte_t pte) {
9a62c051	301	pte_val(pte) \|= _PAGE_SPECIAL; return pte; }
f5ea64dc	302	static inline pgprot_t pte_pgprot(pte_t pte)
a1f242ff	303	{
f5ea64dc	304	return __pgprot(pte_val(pte) & PAGE_PROT_BITS);
a1f242ff	305	}
f88df14b DG	306
	307	static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
	308	{
	309	pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) \| pgprot_val(newprot);
	310	return pte;
	311	}
	312
	313	/*
	314	* When flushing the tlb entry for a page, we also need to flush the hash
	315	* table entry. flush_hash_pages is assembler (for speed) in hashtable.S.
	316	*/
	317	extern int flush_hash_pages(unsigned context, unsigned long va,
	318	unsigned long pmdval, int count);
	319
	320	/* Add an HPTE to the hash table */
	321	extern void add_hash_page(unsigned context, unsigned long va,
	322	unsigned long pmdval);
	323
4ee7084e BB	324	/* Flush an entry from the TLB/hash table */
	325	extern void flush_hash_entry(struct mm_struct mm, pte_t ptep,
	326	unsigned long address);
	327
f88df14b	328	/*
c605782b BH	329	* PTE updates. This function is called whenever an existing
	330	* valid PTE is updated. This does -not- include set_pte_at()
	331	* which nowadays only sets a new PTE.
	332	*
	333	* Depending on the type of MMU, we may need to use atomic updates
	334	* and the PTE may be either 32 or 64 bit wide. In the later case,
	335	* when using atomic updates, only the low part of the PTE is
	336	* accessed atomically.
f88df14b	337	*
c605782b BH	338	* In addition, on 44x, we also maintain a global flag indicating
	339	* that an executable user mapping was modified, which is needed
	340	* to properly flush the virtually tagged instruction cache of
	341	* those implementations.
f88df14b DG	342	*/
f88df14b DG	343	#ifndef CONFIG_PTE_64BIT
1bc54c03 BH	344	static inline unsigned long pte_update(pte_t *p,
1bc54c03 BH	345	unsigned long clr,
f88df14b DG	346	unsigned long set)
f88df14b DG	347	{
1bc54c03	348	#ifdef PTE_ATOMIC_UPDATES
f88df14b DG	349	unsigned long old, tmp;
	350
	351	__asm__ __volatile__("\
	352	1: lwarx %0,0,%3\n\
	353	andc %1,%0,%4\n\
	354	or %1,%1,%5\n"
	355	PPC405_ERR77(0,%3)
	356	" stwcx. %1,0,%3\n\
	357	bne- 1b"
	358	: "=&r" (old), "=&r" (tmp), "=m" (*p)
	359	: "r" (p), "r" (clr), "r" (set), "m" (*p)
	360	: "cc" );
1bc54c03 BH	361	#else /* PTE_ATOMIC_UPDATES */
	362	unsigned long old = pte_val(*p);
	363	*p = __pte((old & ~clr) \| set);
	364	#endif /* !PTE_ATOMIC_UPDATES */
	365
b98ac05d BH	366	#ifdef CONFIG_44x
	367	if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
	368	icache_44x_need_flush = 1;
	369	#endif
f88df14b DG	370	return old;
f88df14b DG	371	}
1bc54c03	372	#else /* CONFIG_PTE_64BIT */
1bc54c03 BH	373	static inline unsigned long long pte_update(pte_t *p,
	374	unsigned long clr,
	375	unsigned long set)
f88df14b	376	{
1bc54c03	377	#ifdef PTE_ATOMIC_UPDATES
f88df14b DG	378	unsigned long long old;
	379	unsigned long tmp;
	380
	381	__asm__ __volatile__("\
	382	1: lwarx %L0,0,%4\n\
	383	lwzx %0,0,%3\n\
	384	andc %1,%L0,%5\n\
	385	or %1,%1,%6\n"
	386	PPC405_ERR77(0,%3)
	387	" stwcx. %1,0,%4\n\
	388	bne- 1b"
	389	: "=&r" (old), "=&r" (tmp), "=m" (*p)
	390	: "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
	391	: "cc" );
1bc54c03 BH	392	#else /* PTE_ATOMIC_UPDATES */
1bc54c03 BH	393	unsigned long long old = pte_val(*p);
585583d9	394	*p = __pte((old & ~(unsigned long long)clr) \| set);
1bc54c03 BH	395	#endif /* !PTE_ATOMIC_UPDATES */
1bc54c03 BH	396
b98ac05d BH	397	#ifdef CONFIG_44x
	398	if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
	399	icache_44x_need_flush = 1;
	400	#endif
f88df14b DG	401	return old;
f88df14b DG	402	}
1bc54c03	403	#endif /* CONFIG_PTE_64BIT */
f88df14b	404
f88df14b	405	/*
bf2737f7 BB	406	* 2.6 calls this without flushing the TLB entry; this is wrong
bf2737f7 BB	407	* for our hash-based implementation, we fix that up here.
f88df14b DG	408	*/
	409	#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
	410	static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
	411	{
	412	unsigned long old;
	413	old = pte_update(ptep, _PAGE_ACCESSED, 0);
	414	#if _PAGE_HASHPTE != 0
	415	if (old & _PAGE_HASHPTE) {
	416	unsigned long ptephys = __pa(ptep) & PAGE_MASK;
	417	flush_hash_pages(context, addr, ptephys, 1);
	418	}
	419	#endif
	420	return (old & _PAGE_ACCESSED) != 0;
	421	}
	422	#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
	423	__ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
	424
f88df14b DG	425	#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
	426	static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
	427	pte_t *ptep)
	428	{
	429	return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
	430	}
	431
	432	#define __HAVE_ARCH_PTEP_SET_WRPROTECT
	433	static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
	434	pte_t *ptep)
	435	{
	436	pte_update(ptep, (_PAGE_RW \| _PAGE_HWWRITE), 0);
	437	}
016b33c4 AW	438	static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
	439	unsigned long addr, pte_t *ptep)
	440	{
	441	ptep_set_wrprotect(mm, addr, ptep);
	442	}
	443
f88df14b	444
8d30c14c	445	static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
f88df14b DG	446	{
f88df14b DG	447	unsigned long bits = pte_val(entry) &
8d30c14c BH	448	(_PAGE_DIRTY \| _PAGE_ACCESSED \| _PAGE_RW \|
8d30c14c BH	449	_PAGE_HWEXEC \| _PAGE_EXEC);
f88df14b DG	450	pte_update(ptep, 0, bits);
	451	}
	452
f88df14b DG	453	#define __HAVE_ARCH_PTE_SAME
	454	#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
	455
	456	/*
	457	* Note that on Book E processors, the pmd contains the kernel virtual
	458	* (lowmem) address of the pte page. The physical address is less useful
	459	* because everything runs with translation enabled (even the TLB miss
	460	* handler). On everything else the pmd contains the physical address
	461	* of the pte page. -- paulus
	462	*/
	463	#ifndef CONFIG_BOOKE
	464	#define pmd_page_vaddr(pmd) \
	465	((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
	466	#define pmd_page(pmd) \
	467	(mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
	468	#else
	469	#define pmd_page_vaddr(pmd) \
	470	((unsigned long) (pmd_val(pmd) & PAGE_MASK))
	471	#define pmd_page(pmd) \
af892e0f	472	pfn_to_page((__pa(pmd_val(pmd)) >> PAGE_SHIFT))
f88df14b DG	473	#endif
	474
	475	/* to find an entry in a kernel page-table-directory */
	476	#define pgd_offset_k(address) pgd_offset(&init_mm, address)
	477
	478	/* to find an entry in a page-table-directory */
	479	#define pgd_index(address) ((address) >> PGDIR_SHIFT)
	480	#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
	481
f88df14b DG	482	/* Find an entry in the third-level page table.. */
	483	#define pte_index(address) \
	484	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
	485	#define pte_offset_kernel(dir, addr) \
	486	((pte_t ) pmd_page_vaddr((dir)) + pte_index(addr))
	487	#define pte_offset_map(dir, addr) \
	488	((pte_t ) kmap_atomic(pmd_page((dir)), KM_PTE0) + pte_index(addr))
	489	#define pte_offset_map_nested(dir, addr) \
	490	((pte_t ) kmap_atomic(pmd_page((dir)), KM_PTE1) + pte_index(addr))
	491
	492	#define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0)
	493	#define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1)
	494
f88df14b DG	495	/*
	496	* Encode and decode a swap entry.
	497	* Note that the bits we use in a PTE for representing a swap entry
	498	* must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the
	499	*_PAGE_HASHPTE bit (if used). -- paulus
	500	*/
	501	#define __swp_type(entry) ((entry).val & 0x1f)
	502	#define __swp_offset(entry) ((entry).val >> 5)
	503	#define __swp_entry(type, offset) ((swp_entry_t) { (type) \| ((offset) << 5) })
	504	#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 })
	505	#define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 })
	506
	507	/* Encode and decode a nonlinear file mapping entry */
	508	#define PTE_FILE_MAX_BITS 29
	509	#define pte_to_pgoff(pte) (pte_val(pte) >> 3)
	510	#define pgoff_to_pte(off) ((pte_t) { ((off) << 3) \| _PAGE_FILE })
	511
f88df14b DG	512	/*
	513	* No page table caches to initialise
	514	*/
	515	#define pgtable_cache_init() do { } while (0)
	516
	517	extern int get_pteptr(struct mm_struct mm, unsigned long addr, pte_t *ptep,
	518	pmd_t **pmdp);
	519
	520	#endif /* !__ASSEMBLY__ */
	521
	522	#endif /* _ASM_POWERPC_PGTABLE_PPC32_H */