projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 16c57b36 KG |
1 | /* |
| 2 | * Copyright 2009 Freescale Semicondutor, Inc. | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or | |
| 5 | * modify it under the terms of the GNU General Public License | |
| 6 | * as published by the Free Software Foundation; either version | |
| 7 | * 2 of the License, or (at your option) any later version. | |
| 8 | * | |
| 9 | * provides masks and opcode images for use by code generation, emulation | |
| 10 | * and for instructions that older assemblers might not know about | |
| 11 | */ | |
| 12 | #ifndef _ASM_POWERPC_PPC_OPCODE_H | |
| 13 | #define _ASM_POWERPC_PPC_OPCODE_H | |
| 14 | ||
| 15 | #include <linux/stringify.h> | |
| 16 | #include <asm/asm-compat.h> | |
| 17 | ||
| 0972def4 MN |
18 | #define __REG_R0 0 |
| 19 | #define __REG_R1 1 | |
| 20 | #define __REG_R2 2 | |
| 21 | #define __REG_R3 3 | |
| 22 | #define __REG_R4 4 | |
| 23 | #define __REG_R5 5 | |
| 24 | #define __REG_R6 6 | |
| 25 | #define __REG_R7 7 | |
| 26 | #define __REG_R8 8 | |
| 27 | #define __REG_R9 9 | |
| 28 | #define __REG_R10 10 | |
| 29 | #define __REG_R11 11 | |
| 30 | #define __REG_R12 12 | |
| 31 | #define __REG_R13 13 | |
| 32 | #define __REG_R14 14 | |
| 33 | #define __REG_R15 15 | |
| 34 | #define __REG_R16 16 | |
| 35 | #define __REG_R17 17 | |
| 36 | #define __REG_R18 18 | |
| 37 | #define __REG_R19 19 | |
| 38 | #define __REG_R20 20 | |
| 39 | #define __REG_R21 21 | |
| 40 | #define __REG_R22 22 | |
| 41 | #define __REG_R23 23 | |
| 42 | #define __REG_R24 24 | |
| 43 | #define __REG_R25 25 | |
| 44 | #define __REG_R26 26 | |
| 45 | #define __REG_R27 27 | |
| 46 | #define __REG_R28 28 | |
| 47 | #define __REG_R29 29 | |
| 48 | #define __REG_R30 30 | |
| 49 | #define __REG_R31 31 | |
| 50 | ||
| f4c01579 MN |
51 | #define __REGA0_0 0 |
| 52 | #define __REGA0_R1 1 | |
| 53 | #define __REGA0_R2 2 | |
| 54 | #define __REGA0_R3 3 | |
| 55 | #define __REGA0_R4 4 | |
| 56 | #define __REGA0_R5 5 | |
| 57 | #define __REGA0_R6 6 | |
| 58 | #define __REGA0_R7 7 | |
| 59 | #define __REGA0_R8 8 | |
| 60 | #define __REGA0_R9 9 | |
| 61 | #define __REGA0_R10 10 | |
| 62 | #define __REGA0_R11 11 | |
| 63 | #define __REGA0_R12 12 | |
| 64 | #define __REGA0_R13 13 | |
| 65 | #define __REGA0_R14 14 | |
| 66 | #define __REGA0_R15 15 | |
| 67 | #define __REGA0_R16 16 | |
| 68 | #define __REGA0_R17 17 | |
| 69 | #define __REGA0_R18 18 | |
| 70 | #define __REGA0_R19 19 | |
| 71 | #define __REGA0_R20 20 | |
| 72 | #define __REGA0_R21 21 | |
| 73 | #define __REGA0_R22 22 | |
| 74 | #define __REGA0_R23 23 | |
| 75 | #define __REGA0_R24 24 | |
| 76 | #define __REGA0_R25 25 | |
| 77 | #define __REGA0_R26 26 | |
| 78 | #define __REGA0_R27 27 | |
| 79 | #define __REGA0_R28 28 | |
| 80 | #define __REGA0_R29 29 | |
| 81 | #define __REGA0_R30 30 | |
| 82 | #define __REGA0_R31 31 | |
| 83 | ||
| 16c57b36 KG |
84 | /* sorted alphabetically */ |
| 85 | #define PPC_INST_DCBA 0x7c0005ec | |
| 86 | #define PPC_INST_DCBA_MASK 0xfc0007fe | |
| 87 | #define PPC_INST_DCBAL 0x7c2005ec | |
| 88 | #define PPC_INST_DCBZL 0x7c2007ec | |
| 89 | #define PPC_INST_ISEL 0x7c00001e | |
| 90 | #define PPC_INST_ISEL_MASK 0xfc00003e | |
| 864b9e6f | 91 | #define PPC_INST_LDARX 0x7c0000a8 |
| 16c57b36 KG |
92 | #define PPC_INST_LSWI 0x7c0004aa |
| 93 | #define PPC_INST_LSWX 0x7c00042a | |
| d6ccb1f5 | 94 | #define PPC_INST_LWARX 0x7c000028 |
| 16c57b36 | 95 | #define PPC_INST_LWSYNC 0x7c2004ac |
| dfb432cb | 96 | #define PPC_INST_LXVD2X 0x7c000698 |
| 16c57b36 KG |
97 | #define PPC_INST_MCRXR 0x7c000400 |
| 98 | #define PPC_INST_MCRXR_MASK 0xfc0007fe | |
| 99 | #define PPC_INST_MFSPR_PVR 0x7c1f42a6 | |
| 100 | #define PPC_INST_MFSPR_PVR_MASK 0xfc1fffff | |
| 101 | #define PPC_INST_MSGSND 0x7c00019c | |
| 102 | #define PPC_INST_NOP 0x60000000 | |
| 103 | #define PPC_INST_POPCNTB 0x7c0000f4 | |
| 104 | #define PPC_INST_POPCNTB_MASK 0xfc0007fe | |
| b5f9b666 AB |
105 | #define PPC_INST_POPCNTD 0x7c0003f4 |
| 106 | #define PPC_INST_POPCNTW 0x7c0002f4 | |
| 16c57b36 KG |
107 | #define PPC_INST_RFCI 0x4c000066 |
| 108 | #define PPC_INST_RFDI 0x4c00004e | |
| 109 | #define PPC_INST_RFMCI 0x4c00004c | |
| efcac658 AK |
110 | #define PPC_INST_MFSPR_DSCR 0x7c1102a6 |
| 111 | #define PPC_INST_MFSPR_DSCR_MASK 0xfc1fffff | |
| 112 | #define PPC_INST_MTSPR_DSCR 0x7c1103a6 | |
| 113 | #define PPC_INST_MTSPR_DSCR_MASK 0xfc1fffff | |
| 697d3899 | 114 | #define PPC_INST_SLBFEE 0x7c0007a7 |
| 16c57b36 KG |
115 | |
| 116 | #define PPC_INST_STRING 0x7c00042a | |
| 117 | #define PPC_INST_STRING_MASK 0xfc0007fe | |
| 118 | #define PPC_INST_STRING_GEN_MASK 0xfc00067e | |
| 119 | ||
| 120 | #define PPC_INST_STSWI 0x7c0005aa | |
| 121 | #define PPC_INST_STSWX 0x7c00052a | |
| dfb432cb | 122 | #define PPC_INST_STXVD2X 0x7c000798 |
| 60dbf438 | 123 | #define PPC_INST_TLBIE 0x7c000264 |
| 7281f5dc | 124 | #define PPC_INST_TLBILX 0x7c000024 |
| 16c57b36 | 125 | #define PPC_INST_WAIT 0x7c00007c |
| 29c09e8f BH |
126 | #define PPC_INST_TLBIVAX 0x7c000624 |
| 127 | #define PPC_INST_TLBSRX_DOT 0x7c0006a5 | |
| 0016a4cf | 128 | #define PPC_INST_XXLOR 0xf0000510 |
| b92a66a6 | 129 | #define PPC_INST_XVCPSGNDP 0xf0000780 |
| 16c57b36 | 130 | |
| 948cf67c BH |
131 | #define PPC_INST_NAP 0x4c000364 |
| 132 | #define PPC_INST_SLEEP 0x4c0003a4 | |
| 133 | ||
| 931e1241 BH |
134 | /* A2 specific instructions */ |
| 135 | #define PPC_INST_ERATWE 0x7c0001a6 | |
| 136 | #define PPC_INST_ERATRE 0x7c000166 | |
| 137 | #define PPC_INST_ERATILX 0x7c000066 | |
| 138 | #define PPC_INST_ERATIVAX 0x7c000666 | |
| 139 | #define PPC_INST_ERATSX 0x7c000126 | |
| 140 | #define PPC_INST_ERATSX_DOT 0x7c000127 | |
| 141 | ||
| 0ca87f05 ME |
142 | /* Misc instructions for BPF compiler */ |
| 143 | #define PPC_INST_LD 0xe8000000 | |
| 144 | #define PPC_INST_LHZ 0xa0000000 | |
| 145 | #define PPC_INST_LWZ 0x80000000 | |
| 146 | #define PPC_INST_STD 0xf8000000 | |
| 147 | #define PPC_INST_STDU 0xf8000001 | |
| 148 | #define PPC_INST_MFLR 0x7c0802a6 | |
| 149 | #define PPC_INST_MTLR 0x7c0803a6 | |
| 150 | #define PPC_INST_CMPWI 0x2c000000 | |
| 151 | #define PPC_INST_CMPDI 0x2c200000 | |
| 152 | #define PPC_INST_CMPLW 0x7c000040 | |
| 153 | #define PPC_INST_CMPLWI 0x28000000 | |
| 154 | #define PPC_INST_ADDI 0x38000000 | |
| 155 | #define PPC_INST_ADDIS 0x3c000000 | |
| 156 | #define PPC_INST_ADD 0x7c000214 | |
| 157 | #define PPC_INST_SUB 0x7c000050 | |
| 158 | #define PPC_INST_BLR 0x4e800020 | |
| 159 | #define PPC_INST_BLRL 0x4e800021 | |
| 160 | #define PPC_INST_MULLW 0x7c0001d6 | |
| 161 | #define PPC_INST_MULHWU 0x7c000016 | |
| 162 | #define PPC_INST_MULLI 0x1c000000 | |
| 163 | #define PPC_INST_DIVWU 0x7c0003d6 | |
| 164 | #define PPC_INST_RLWINM 0x54000000 | |
| 165 | #define PPC_INST_RLDICR 0x78000004 | |
| 166 | #define PPC_INST_SLW 0x7c000030 | |
| 167 | #define PPC_INST_SRW 0x7c000430 | |
| 168 | #define PPC_INST_AND 0x7c000038 | |
| 169 | #define PPC_INST_ANDDOT 0x7c000039 | |
| 170 | #define PPC_INST_OR 0x7c000378 | |
| 02871903 | 171 | #define PPC_INST_XOR 0x7c000278 |
| 0ca87f05 ME |
172 | #define PPC_INST_ANDI 0x70000000 |
| 173 | #define PPC_INST_ORI 0x60000000 | |
| 174 | #define PPC_INST_ORIS 0x64000000 | |
| 02871903 DB |
175 | #define PPC_INST_XORI 0x68000000 |
| 176 | #define PPC_INST_XORIS 0x6c000000 | |
| 0ca87f05 ME |
177 | #define PPC_INST_NEG 0x7c0000d0 |
| 178 | #define PPC_INST_BRANCH 0x48000000 | |
| 179 | #define PPC_INST_BRANCH_COND 0x40800000 | |
| 4404a9f9 MN |
180 | #define PPC_INST_LBZCIX 0x7c0006aa |
| 181 | #define PPC_INST_STBCIX 0x7c0007aa | |
| 0ca87f05 | 182 | |
| 16c57b36 | 183 | /* macros to insert fields into opcodes */ |
| 55a5db18 MN |
184 | #define ___PPC_RA(a) (((a) & 0x1f) << 16) |
| 185 | #define ___PPC_RB(b) (((b) & 0x1f) << 11) | |
| 186 | #define ___PPC_RS(s) (((s) & 0x1f) << 21) | |
| 187 | #define ___PPC_RT(t) ___PPC_RS(t) | |
| 0b7673c3 | 188 | #define __PPC_RA(a) ___PPC_RA(__REG_##a) |
| f4c01579 | 189 | #define __PPC_RA0(a) ___PPC_RA(__REGA0_##a) |
| 0b7673c3 MN |
190 | #define __PPC_RB(b) ___PPC_RB(__REG_##b) |
| 191 | #define __PPC_RS(s) ___PPC_RS(__REG_##s) | |
| 192 | #define __PPC_RT(t) ___PPC_RT(__REG_##t) | |
| 0016a4cf PM |
193 | #define __PPC_XA(a) ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3)) |
| 194 | #define __PPC_XB(b) ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4)) | |
| dfb432cb | 195 | #define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5)) |
| 0016a4cf | 196 | #define __PPC_XT(s) __PPC_XS(s) |
| da6b43c8 MN |
197 | #define __PPC_T_TLB(t) (((t) & 0x3) << 21) |
| 198 | #define __PPC_WC(w) (((w) & 0x3) << 21) | |
| 931e1241 | 199 | #define __PPC_WS(w) (((w) & 0x1f) << 11) |
| 0ca87f05 ME |
200 | #define __PPC_SH(s) __PPC_WS(s) |
| 201 | #define __PPC_MB(s) (((s) & 0x1f) << 6) | |
| 202 | #define __PPC_ME(s) (((s) & 0x1f) << 1) | |
| 203 | #define __PPC_BI(s) (((s) & 0x1f) << 16) | |
| 931e1241 | 204 | |
| 4e14a4d1 | 205 | /* |
| d6ccb1f5 KG |
206 | * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a |
| 207 | * larx with EH set as an illegal instruction. | |
| 4e14a4d1 AB |
208 | */ |
| 209 | #ifdef CONFIG_PPC64 | |
| 210 | #define __PPC_EH(eh) (((eh) & 0x1) << 0) | |
| 211 | #else | |
| 212 | #define __PPC_EH(eh) 0 | |
| 213 | #endif | |
| 16c57b36 KG |
214 | |
| 215 | /* Deal with instructions that older assemblers aren't aware of */ | |
| 216 | #define PPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \ | |
| 217 | __PPC_RA(a) | __PPC_RB(b)) | |
| 218 | #define PPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \ | |
| 219 | __PPC_RA(a) | __PPC_RB(b)) | |
| 864b9e6f | 220 | #define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LDARX | \ |
| cdaade71 MN |
221 | ___PPC_RT(t) | ___PPC_RA(a) | \ |
| 222 | ___PPC_RB(b) | __PPC_EH(eh)) | |
| 4e14a4d1 | 223 | #define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX | \ |
| cdaade71 MN |
224 | ___PPC_RT(t) | ___PPC_RA(a) | \ |
| 225 | ___PPC_RB(b) | __PPC_EH(eh)) | |
| 16c57b36 | 226 | #define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \ |
| cdaade71 | 227 | ___PPC_RB(b)) |
| b5f9b666 AB |
228 | #define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_INST_POPCNTB | \ |
| 229 | __PPC_RA(a) | __PPC_RS(s)) | |
| 230 | #define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_INST_POPCNTD | \ | |
| 231 | __PPC_RA(a) | __PPC_RS(s)) | |
| 232 | #define PPC_POPCNTW(a, s) stringify_in_c(.long PPC_INST_POPCNTW | \ | |
| 233 | __PPC_RA(a) | __PPC_RS(s)) | |
| 16c57b36 KG |
234 | #define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI) |
| 235 | #define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI) | |
| 236 | #define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI) | |
| 237 | #define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \ | |
| 962cffbd | 238 | __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b)) |
| 16c57b36 KG |
239 | #define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b) |
| 240 | #define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b) | |
| 241 | #define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b) | |
| 242 | #define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \ | |
| 243 | __PPC_WC(w)) | |
| 60dbf438 | 244 | #define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE | \ |
| cdaade71 | 245 | ___PPC_RB(a) | ___PPC_RS(lp)) |
| 29c09e8f | 246 | #define PPC_TLBSRX_DOT(a,b) stringify_in_c(.long PPC_INST_TLBSRX_DOT | \ |
| 962cffbd | 247 | __PPC_RA0(a) | __PPC_RB(b)) |
| 29c09e8f | 248 | #define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \ |
| 962cffbd | 249 | __PPC_RA0(a) | __PPC_RB(b)) |
| 16c57b36 | 250 | |
| 931e1241 BH |
251 | #define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_INST_ERATWE | \ |
| 252 | __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w)) | |
| 253 | #define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_INST_ERATRE | \ | |
| 254 | __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w)) | |
| 255 | #define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_INST_ERATILX | \ | |
| 962cffbd | 256 | __PPC_T_TLB(t) | __PPC_RA0(a) | \ |
| 931e1241 BH |
257 | __PPC_RB(b)) |
| 258 | #define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_INST_ERATIVAX | \ | |
| 962cffbd | 259 | __PPC_RS(s) | __PPC_RA0(a) | __PPC_RB(b)) |
| 931e1241 | 260 | #define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_INST_ERATSX | \ |
| 962cffbd | 261 | __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b)) |
| 931e1241 | 262 | #define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT | \ |
| 962cffbd | 263 | __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b)) |
| 697d3899 PM |
264 | #define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_INST_SLBFEE | \ |
| 265 | __PPC_RT(t) | __PPC_RB(b)) | |
| 4404a9f9 MN |
266 | /* PASemi instructions */ |
| 267 | #define LBZCIX(t,a,b) stringify_in_c(.long PPC_INST_LBZCIX | \ | |
| 268 | __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b)) | |
| 269 | #define STBCIX(s,a,b) stringify_in_c(.long PPC_INST_STBCIX | \ | |
| 270 | __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b)) | |
| 931e1241 | 271 | |
| dfb432cb MN |
272 | /* |
| 273 | * Define what the VSX XX1 form instructions will look like, then add | |
| 274 | * the 128 bit load store instructions based on that. | |
| 275 | */ | |
| 276 | #define VSX_XX1(s, a, b) (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b)) | |
| 0016a4cf | 277 | #define VSX_XX3(t, a, b) (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b)) |
| dfb432cb | 278 | #define STXVD2X(s, a, b) stringify_in_c(.long PPC_INST_STXVD2X | \ |
| 178f2ae0 | 279 | VSX_XX1((s), a, b)) |
| dfb432cb | 280 | #define LXVD2X(s, a, b) stringify_in_c(.long PPC_INST_LXVD2X | \ |
| 178f2ae0 | 281 | VSX_XX1((s), a, b)) |
| 0016a4cf | 282 | #define XXLOR(t, a, b) stringify_in_c(.long PPC_INST_XXLOR | \ |
| 178f2ae0 | 283 | VSX_XX3((t), a, b)) |
| b92a66a6 MN |
284 | #define XVCPSGNDP(t, a, b) stringify_in_c(.long (PPC_INST_XVCPSGNDP | \ |
| 285 | VSX_XX3((t), (a), (b)))) | |
| dfb432cb | 286 | |
| 948cf67c BH |
287 | #define PPC_NAP stringify_in_c(.long PPC_INST_NAP) |
| 288 | #define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP) | |
| 289 | ||
| 16c57b36 | 290 | #endif /* _ASM_POWERPC_PPC_OPCODE_H */ |