[deliverable/linux.git] / arch / powerpc / include / asm / processor.h

#ifndef _ASM_POWERPC_PROCESSOR_H
#define _ASM_POWERPC_PROCESSOR_H

/*
 * Copyright (C) 2001 PPC 64 Team, IBM Corp
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <asm/reg.h>

#ifdef CONFIG_VSX
#define TS_FPRWIDTH 2
#else
#define TS_FPRWIDTH 1
#endif

#ifdef CONFIG_PPC64
/* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
#define PPR_PRIORITY 3
#ifdef __ASSEMBLY__
#define INIT_PPR (PPR_PRIORITY << 50)
#else
#define INIT_PPR ((u64)PPR_PRIORITY << 50)
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_PPC64 */

#ifndef __ASSEMBLY__
#include <linux/compiler.h>
#include <linux/cache.h>
#include <asm/ptrace.h>
#include <asm/types.h>
#include <asm/hw_breakpoint.h>

/* We do _not_ want to define new machine types at all, those must die
 * in favor of using the device-tree
 * -- BenH.
 */

/* PREP sub-platform types see residual.h for these */
#define _PREP_Motorola	0x01	/* motorola prep */
#define _PREP_Firm	0x02	/* firmworks prep */
#define _PREP_IBM	0x00	/* ibm prep */
#define _PREP_Bull	0x03	/* bull prep */

/* CHRP sub-platform types. These are arbitrary */
#define _CHRP_Motorola	0x04	/* motorola chrp, the cobra */
#define _CHRP_IBM	0x05	/* IBM chrp, the longtrail and longtrail 2 */
#define _CHRP_Pegasos	0x06	/* Genesi/bplan's Pegasos and Pegasos2 */
#define _CHRP_briq	0x07	/* TotalImpact's briQ */

#if defined(__KERNEL__) && defined(CONFIG_PPC32)

extern int _chrp_type;

#ifdef CONFIG_PPC_PREP

/* what kind of prep workstation we are */
extern int _prep_type;

#endif /* CONFIG_PPC_PREP */

#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */

/*
 * Default implementation of macro that returns current
 * instruction pointer ("program counter").
 */
#define current_text_addr() ({ __label__ _l; _l: &&_l;})

/* Macros for adjusting thread priority (hardware multi-threading) */
#define HMT_very_low()   asm volatile("or 31,31,31   # very low priority")
#define HMT_low()	 asm volatile("or 1,1,1	     # low priority")
#define HMT_medium_low() asm volatile("or 6,6,6      # medium low priority")
#define HMT_medium()	 asm volatile("or 2,2,2	     # medium priority")
#define HMT_medium_high() asm volatile("or 5,5,5      # medium high priority")
#define HMT_high()	 asm volatile("or 3,3,3	     # high priority")

#ifdef __KERNEL__

struct task_struct;
void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
void release_thread(struct task_struct *);

/* Lazy FPU handling on uni-processor */
extern struct task_struct *last_task_used_math;
extern struct task_struct *last_task_used_altivec;
extern struct task_struct *last_task_used_vsx;
extern struct task_struct *last_task_used_spe;

#ifdef CONFIG_PPC32

#if CONFIG_TASK_SIZE > CONFIG_KERNEL_START
#error User TASK_SIZE overlaps with KERNEL_START address
#endif
#define TASK_SIZE	(CONFIG_TASK_SIZE)

/* This decides where the kernel will search for a free chunk of vm
 * space during mmap's.
 */
#define TASK_UNMAPPED_BASE	(TASK_SIZE / 8 * 3)
#endif

#ifdef CONFIG_PPC64
/* 64-bit user address space is 46-bits (64TB user VM) */
#define TASK_SIZE_USER64 (0x0000400000000000UL)

/* 
 * 32-bit user address space is 4GB - 1 page 
 * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
 */
#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))

#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
		TASK_SIZE_USER32 : TASK_SIZE_USER64)
#define TASK_SIZE	  TASK_SIZE_OF(current)

/* This decides where the kernel will search for a free chunk of vm
 * space during mmap's.
 */
#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4))

#define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \
		TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
#endif

#ifdef __powerpc64__

#define STACK_TOP_USER64 TASK_SIZE_USER64
#define STACK_TOP_USER32 TASK_SIZE_USER32

#define STACK_TOP (is_32bit_task() ? \
		   STACK_TOP_USER32 : STACK_TOP_USER64)

#define STACK_TOP_MAX STACK_TOP_USER64

#else /* __powerpc64__ */

#define STACK_TOP TASK_SIZE
#define STACK_TOP_MAX	STACK_TOP

#endif /* __powerpc64__ */

typedef struct {
	unsigned long seg;
} mm_segment_t;

#define TS_FPROFFSET 0
#define TS_VSRLOWOFFSET 1
#define TS_FPR(i) fpr[i][TS_FPROFFSET]

struct thread_struct {
	unsigned long	ksp;		/* Kernel stack pointer */
	unsigned long	ksp_limit;	/* if ksp <= ksp_limit stack overflow */

#ifdef CONFIG_PPC64
	unsigned long	ksp_vsid;
#endif
	struct pt_regs	*regs;		/* Pointer to saved register state */
	mm_segment_t	fs;		/* for get_fs() validation */
#ifdef CONFIG_BOOKE
	/* BookE base exception scratch space; align on cacheline */
	unsigned long	normsave[8] ____cacheline_aligned;
#endif
#ifdef CONFIG_PPC32
	void		*pgdir;		/* root of page-table tree */
#endif
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
	/*
	 * The following help to manage the use of Debug Control Registers
	 * om the BookE platforms.
	 */
	unsigned long	dbcr0;
	unsigned long	dbcr1;
#ifdef CONFIG_BOOKE
	unsigned long	dbcr2;
#endif
	/*
	 * The stored value of the DBSR register will be the value at the
	 * last debug interrupt. This register can only be read from the
	 * user (will never be written to) and has value while helping to
	 * describe the reason for the last debug trap.  Torez
	 */
	unsigned long	dbsr;
	/*
	 * The following will contain addresses used by debug applications
	 * to help trace and trap on particular address locations.
	 * The bits in the Debug Control Registers above help define which
	 * of the following registers will contain valid data and/or addresses.
	 */
	unsigned long	iac1;
	unsigned long	iac2;
#if CONFIG_PPC_ADV_DEBUG_IACS > 2
	unsigned long	iac3;
	unsigned long	iac4;
#endif
	unsigned long	dac1;
	unsigned long	dac2;
#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
	unsigned long	dvc1;
	unsigned long	dvc2;
#endif
#endif
	/* FP and VSX 0-31 register set */
	double		fpr[32][TS_FPRWIDTH];
	struct {

		unsigned int pad;
		unsigned int val;	/* Floating point status */
	} fpscr;
	int		fpexc_mode;	/* floating-point exception mode */
	unsigned int	align_ctl;	/* alignment handling control */
#ifdef CONFIG_PPC64
	unsigned long	start_tb;	/* Start purr when proc switched in */
	unsigned long	accum_tb;	/* Total accumilated purr for process */
#ifdef CONFIG_HAVE_HW_BREAKPOINT
	struct perf_event *ptrace_bps[HBP_NUM];
	/*
	 * Helps identify source of single-step exception and subsequent
	 * hw-breakpoint enablement
	 */
	struct perf_event *last_hit_ubp;
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
#endif
	struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */
	unsigned long	trap_nr;	/* last trap # on this thread */
#ifdef CONFIG_ALTIVEC
	/* Complete AltiVec register set */
	vector128	vr[32] __attribute__((aligned(16)));
	/* AltiVec status */
	vector128	vscr __attribute__((aligned(16)));
	unsigned long	vrsave;
	int		used_vr;	/* set if process has used altivec */
#endif /* CONFIG_ALTIVEC */
#ifdef CONFIG_VSX
	/* VSR status */
	int		used_vsr;	/* set if process has used altivec */
#endif /* CONFIG_VSX */
#ifdef CONFIG_SPE
	unsigned long	evr[32];	/* upper 32-bits of SPE regs */
	u64		acc;		/* Accumulator */
	unsigned long	spefscr;	/* SPE & eFP status */
	int		used_spe;	/* set if process has used spe */
#endif /* CONFIG_SPE */
#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
	void*		kvm_shadow_vcpu; /* KVM internal data */
#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
	struct kvm_vcpu	*kvm_vcpu;
#endif
#ifdef CONFIG_PPC64
	unsigned long	dscr;
	int		dscr_inherit;
	unsigned long	ppr;	/* used to save/restore SMT priority */
#endif
};

#define ARCH_MIN_TASKALIGN 16

#define INIT_SP		(sizeof(init_stack) + (unsigned long) &init_stack)
#define INIT_SP_LIMIT \
	(_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)

#ifdef CONFIG_SPE
#define SPEFSCR_INIT .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
#else
#define SPEFSCR_INIT
#endif

#ifdef CONFIG_PPC32
#define INIT_THREAD { \
	.ksp = INIT_SP, \
	.ksp_limit = INIT_SP_LIMIT, \
	.fs = KERNEL_DS, \
	.pgdir = swapper_pg_dir, \
	.fpexc_mode = MSR_FE0 | MSR_FE1, \
	SPEFSCR_INIT \
}
#else
#define INIT_THREAD  { \
	.ksp = INIT_SP, \
	.ksp_limit = INIT_SP_LIMIT, \
	.regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
	.fs = KERNEL_DS, \
	.fpr = {{0}}, \
	.fpscr = { .val = 0, }, \
	.fpexc_mode = 0, \
	.ppr = INIT_PPR, \
}
#endif

/*
 * Return saved PC of a blocked thread. For now, this is the "user" PC
 */
#define thread_saved_pc(tsk)    \
        ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)

#define task_pt_regs(tsk)	((struct pt_regs *)(tsk)->thread.regs)

unsigned long get_wchan(struct task_struct *p);

#define KSTK_EIP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
#define KSTK_ESP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)

/* Get/set floating-point exception mode */
#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))

extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);

#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))

extern int get_endian(struct task_struct *tsk, unsigned long adr);
extern int set_endian(struct task_struct *tsk, unsigned int val);

#define GET_UNALIGN_CTL(tsk, adr)	get_unalign_ctl((tsk), (adr))
#define SET_UNALIGN_CTL(tsk, val)	set_unalign_ctl((tsk), (val))

extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);

static inline unsigned int __unpack_fe01(unsigned long msr_bits)
{
	return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
}

static inline unsigned long __pack_fe01(unsigned int fpmode)
{
	return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
}

#ifdef CONFIG_PPC64
#define cpu_relax()	do { HMT_low(); HMT_medium(); barrier(); } while (0)
#else
#define cpu_relax()	barrier()
#endif

/* Check that a certain kernel stack pointer is valid in task_struct p */
int validate_sp(unsigned long sp, struct task_struct *p,
                       unsigned long nbytes);

/*
 * Prefetch macros.
 */
#define ARCH_HAS_PREFETCH
#define ARCH_HAS_PREFETCHW
#define ARCH_HAS_SPINLOCK_PREFETCH

static inline void prefetch(const void *x)
{
	if (unlikely(!x))
		return;

	__asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
}

static inline void prefetchw(const void *x)
{
	if (unlikely(!x))
		return;

	__asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
}

#define spin_lock_prefetch(x)	prefetchw(x)

#ifdef CONFIG_PPC64
#define HAVE_ARCH_PICK_MMAP_LAYOUT
#endif

#ifdef CONFIG_PPC64
static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)
{
	unsigned long sp;

	if (is_32)
		sp = regs->gpr[1] & 0x0ffffffffUL;
	else
		sp = regs->gpr[1];

	return sp;
}
#else
static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)
{
	return regs->gpr[1];
}
#endif

extern unsigned long cpuidle_disable;
enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};

extern int powersave_nap;	/* set if nap mode can be used in idle loop */
extern void power7_nap(void);

#ifdef CONFIG_PSERIES_IDLE
extern void update_smt_snooze_delay(int cpu, int residency);
#else
static inline void update_smt_snooze_delay(int cpu, int residency) {}
#endif

extern void flush_instruction_cache(void);
extern void hard_reset_now(void);
extern void poweroff_now(void);
extern int fix_alignment(struct pt_regs *);
extern void cvt_fd(float *from, double *to);
extern void cvt_df(double *from, float *to);
extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);

#ifdef CONFIG_PPC64
/*
 * We handle most unaligned accesses in hardware. On the other hand 
 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
 * powers of 2 writes until it reaches sufficient alignment).
 *
 * Based on this we disable the IP header alignment in network drivers.
 */
#define NET_IP_ALIGN	0
#endif

#endif /* __KERNEL__ */
#endif /* __ASSEMBLY__ */
#endif /* _ASM_POWERPC_PROCESSOR_H */
Commit	Line	Data
9f04b9e3 PM	1	#ifndef _ASM_POWERPC_PROCESSOR_H
9f04b9e3 PM	2	#define _ASM_POWERPC_PROCESSOR_H
1da177e4 LT	3
1da177e4 LT	4	/*
9f04b9e3 PM	5	* Copyright (C) 2001 PPC 64 Team, IBM Corp
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* as published by the Free Software Foundation; either version
	10	* 2 of the License, or (at your option) any later version.
1da177e4	11	*/
1da177e4	12
9f04b9e3	13	#include <asm/reg.h>
1da177e4	14
c6e6771b MN	15	#ifdef CONFIG_VSX
	16	#define TS_FPRWIDTH 2
	17	#else
9c75a31c	18	#define TS_FPRWIDTH 1
c6e6771b	19	#endif
9c75a31c	20
92779245 HM	21	#ifdef CONFIG_PPC64
	22	/* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
	23	#define PPR_PRIORITY 3
	24	#ifdef __ASSEMBLY__
	25	#define INIT_PPR (PPR_PRIORITY << 50)
	26	#else
	27	#define INIT_PPR ((u64)PPR_PRIORITY << 50)
	28	#endif /* __ASSEMBLY__ */
	29	#endif /* CONFIG_PPC64 */
	30
9f04b9e3 PM	31	#ifndef __ASSEMBLY__
9f04b9e3 PM	32	#include <linux/compiler.h>
1325a684	33	#include <linux/cache.h>
1da177e4 LT	34	#include <asm/ptrace.h>
1da177e4 LT	35	#include <asm/types.h>
9422de3e	36	#include <asm/hw_breakpoint.h>
1da177e4	37
799d6046 PM	38	/* We do _not_ want to define new machine types at all, those must die
	39	* in favor of using the device-tree
	40	* -- BenH.
1da177e4	41	*/
1da177e4	42
799d6046	43	/* PREP sub-platform types see residual.h for these */
1da177e4 LT	44	#define _PREP_Motorola 0x01 /* motorola prep */
	45	#define _PREP_Firm 0x02 /* firmworks prep */
	46	#define _PREP_IBM 0x00 /* ibm prep */
	47	#define _PREP_Bull 0x03 /* bull prep */
	48
799d6046	49	/* CHRP sub-platform types. These are arbitrary */
1da177e4 LT	50	#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
	51	#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
	52	#define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */
26c5032e	53	#define _CHRP_briq 0x07 /* TotalImpact's briQ */
1da177e4	54
e8222502 BH	55	#if defined(__KERNEL__) && defined(CONFIG_PPC32)
	56
	57	extern int _chrp_type;
799d6046	58
0a26b136	59	#ifdef CONFIG_PPC_PREP
799d6046	60
1da177e4 LT	61	/* what kind of prep workstation we are */
1da177e4 LT	62	extern int _prep_type;
1da177e4	63
0a26b136 PM	64	#endif /* CONFIG_PPC_PREP */
0a26b136 PM	65
e8222502 BH	66	#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
e8222502 BH	67
9f04b9e3 PM	68	/*
	69	* Default implementation of macro that returns current
	70	* instruction pointer ("program counter").
	71	*/
	72	#define current_text_addr() ({ __label__ _l; _l: &&_l;})
	73
	74	/* Macros for adjusting thread priority (hardware multi-threading) */
	75	#define HMT_very_low() asm volatile("or 31,31,31 # very low priority")
	76	#define HMT_low() asm volatile("or 1,1,1 # low priority")
	77	#define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority")
	78	#define HMT_medium() asm volatile("or 2,2,2 # medium priority")
	79	#define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority")
	80	#define HMT_high() asm volatile("or 3,3,3 # high priority")
	81
	82	#ifdef __KERNEL__
	83
1da177e4	84	struct task_struct;
9f04b9e3	85	void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
1da177e4 LT	86	void release_thread(struct task_struct *);
1da177e4 LT	87
1da177e4 LT	88	/* Lazy FPU handling on uni-processor */
	89	extern struct task_struct *last_task_used_math;
	90	extern struct task_struct *last_task_used_altivec;
c6e6771b	91	extern struct task_struct *last_task_used_vsx;
1da177e4 LT	92	extern struct task_struct *last_task_used_spe;
1da177e4 LT	93
9f04b9e3	94	#ifdef CONFIG_PPC32
7c4f10b9 RT	95
	96	#if CONFIG_TASK_SIZE > CONFIG_KERNEL_START
	97	#error User TASK_SIZE overlaps with KERNEL_START address
	98	#endif
9f04b9e3 PM	99	#define TASK_SIZE (CONFIG_TASK_SIZE)
9f04b9e3 PM	100
1da177e4 LT	101	/* This decides where the kernel will search for a free chunk of vm
	102	* space during mmap's.
	103	*/
	104	#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
9f04b9e3 PM	105	#endif
	106
	107	#ifdef CONFIG_PPC64
048ee099 AK	108	/* 64-bit user address space is 46-bits (64TB user VM) */
048ee099 AK	109	#define TASK_SIZE_USER64 (0x0000400000000000UL)
9f04b9e3 PM	110
	111	/*
	112	* 32-bit user address space is 4GB - 1 page
	113	* (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
	114	*/
	115	#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
	116
82455257	117	#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
9f04b9e3	118	TASK_SIZE_USER32 : TASK_SIZE_USER64)
82455257	119	#define TASK_SIZE TASK_SIZE_OF(current)
9f04b9e3 PM	120
	121	/* This decides where the kernel will search for a free chunk of vm
	122	* space during mmap's.
	123	*/
	124	#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
	125	#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4))
	126
cab175f9	127	#define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \
9f04b9e3 PM	128	TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
9f04b9e3 PM	129	#endif
1da177e4	130
922a70d3 DH	131	#ifdef __powerpc64__
	132
	133	#define STACK_TOP_USER64 TASK_SIZE_USER64
	134	#define STACK_TOP_USER32 TASK_SIZE_USER32
	135
cab175f9	136	#define STACK_TOP (is_32bit_task() ? \
922a70d3 DH	137	STACK_TOP_USER32 : STACK_TOP_USER64)
	138
	139	#define STACK_TOP_MAX STACK_TOP_USER64
	140
	141	#else /* __powerpc64__ */
	142
	143	#define STACK_TOP TASK_SIZE
	144	#define STACK_TOP_MAX STACK_TOP
	145
	146	#endif /* __powerpc64__ */
922a70d3	147
1da177e4 LT	148	typedef struct {
	149	unsigned long seg;
	150	} mm_segment_t;
	151
c6e6771b MN	152	#define TS_FPROFFSET 0
	153	#define TS_VSRLOWOFFSET 1
	154	#define TS_FPR(i) fpr[i][TS_FPROFFSET]
9c75a31c	155
1da177e4 LT	156	struct thread_struct {
1da177e4 LT	157	unsigned long ksp; /* Kernel stack pointer */
85218827 KG	158	unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */
85218827 KG	159
9f04b9e3 PM	160	#ifdef CONFIG_PPC64
	161	unsigned long ksp_vsid;
	162	#endif
1da177e4 LT	163	struct pt_regs regs; / Pointer to saved register state */
1da177e4 LT	164	mm_segment_t fs; /* for get_fs() validation */
1325a684 AK	165	#ifdef CONFIG_BOOKE
	166	/* BookE base exception scratch space; align on cacheline */
	167	unsigned long normsave[8] ____cacheline_aligned;
	168	#endif
9f04b9e3	169	#ifdef CONFIG_PPC32
1da177e4	170	void pgdir; / root of page-table tree */
9f04b9e3	171	#endif
99396ac1 DK	172	#ifdef CONFIG_PPC_ADV_DEBUG_REGS
	173	/*
	174	* The following help to manage the use of Debug Control Registers
	175	* om the BookE platforms.
	176	*/
	177	unsigned long dbcr0;
1da177e4	178	unsigned long dbcr1;
99396ac1 DK	179	#ifdef CONFIG_BOOKE
	180	unsigned long dbcr2;
	181	#endif
	182	/*
	183	* The stored value of the DBSR register will be the value at the
	184	* last debug interrupt. This register can only be read from the
	185	* user (will never be written to) and has value while helping to
	186	* describe the reason for the last debug trap. Torez
	187	*/
	188	unsigned long dbsr;
	189	/*
	190	* The following will contain addresses used by debug applications
	191	* to help trace and trap on particular address locations.
	192	* The bits in the Debug Control Registers above help define which
	193	* of the following registers will contain valid data and/or addresses.
	194	*/
	195	unsigned long iac1;
	196	unsigned long iac2;
	197	#if CONFIG_PPC_ADV_DEBUG_IACS > 2
	198	unsigned long iac3;
	199	unsigned long iac4;
	200	#endif
	201	unsigned long dac1;
	202	unsigned long dac2;
	203	#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
	204	unsigned long dvc1;
	205	unsigned long dvc2;
	206	#endif
1da177e4	207	#endif
c6e6771b MN	208	/* FP and VSX 0-31 register set */
	209	double fpr[32][TS_FPRWIDTH];
	210	struct {
25c8a78b DG	211
	212	unsigned int pad;
	213	unsigned int val; /* Floating point status */
	214	} fpscr;
9f04b9e3	215	int fpexc_mode; /* floating-point exception mode */
e9370ae1	216	unsigned int align_ctl; /* alignment handling control */
9f04b9e3 PM	217	#ifdef CONFIG_PPC64
	218	unsigned long start_tb; /* Start purr when proc switched in */
	219	unsigned long accum_tb; /* Total accumilated purr for process */
5aae8a53 P	220	#ifdef CONFIG_HAVE_HW_BREAKPOINT
	221	struct perf_event *ptrace_bps[HBP_NUM];
	222	/*
	223	* Helps identify source of single-step exception and subsequent
	224	* hw-breakpoint enablement
	225	*/
	226	struct perf_event *last_hit_ubp;
	227	#endif /* CONFIG_HAVE_HW_BREAKPOINT */
9f04b9e3	228	#endif
9422de3e	229	struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */
41ab5266	230	unsigned long trap_nr; /* last trap # on this thread */
1da177e4 LT	231	#ifdef CONFIG_ALTIVEC
1da177e4 LT	232	/* Complete AltiVec register set */
fc624eae	233	vector128 vr[32] __attribute__((aligned(16)));
1da177e4	234	/* AltiVec status */
fc624eae	235	vector128 vscr __attribute__((aligned(16)));
1da177e4 LT	236	unsigned long vrsave;
	237	int used_vr; /* set if process has used altivec */
	238	#endif /* CONFIG_ALTIVEC */
c6e6771b MN	239	#ifdef CONFIG_VSX
	240	/* VSR status */
	241	int used_vsr; /* set if process has used altivec */
	242	#endif /* CONFIG_VSX */
1da177e4 LT	243	#ifdef CONFIG_SPE
	244	unsigned long evr[32]; /* upper 32-bits of SPE regs */
	245	u64 acc; /* Accumulator */
	246	unsigned long spefscr; /* SPE & eFP status */
	247	int used_spe; /* set if process has used spe */
	248	#endif /* CONFIG_SPE */
97e49255 AG	249	#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
	250	void* kvm_shadow_vcpu; /* KVM internal data */
	251	#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
d30f6e48 SW	252	#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
	253	struct kvm_vcpu *kvm_vcpu;
	254	#endif
efcac658 AK	255	#ifdef CONFIG_PPC64
	256	unsigned long dscr;
	257	int dscr_inherit;
92779245	258	unsigned long ppr; /* used to save/restore SMT priority */
efcac658	259	#endif
1da177e4 LT	260	};
	261
	262	#define ARCH_MIN_TASKALIGN 16
	263
	264	#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
85218827 KG	265	#define INIT_SP_LIMIT \
85218827 KG	266	(_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)
1da177e4	267
6a800f36 LY	268	#ifdef CONFIG_SPE
	269	#define SPEFSCR_INIT .spefscr = SPEFSCR_FINVE \| SPEFSCR_FDBZE \| SPEFSCR_FUNFE \| SPEFSCR_FOVFE,
	270	#else
	271	#define SPEFSCR_INIT
	272	#endif
9f04b9e3 PM	273
9f04b9e3 PM	274	#ifdef CONFIG_PPC32
1da177e4 LT	275	#define INIT_THREAD { \
1da177e4 LT	276	.ksp = INIT_SP, \
85218827	277	.ksp_limit = INIT_SP_LIMIT, \
1da177e4 LT	278	.fs = KERNEL_DS, \
	279	.pgdir = swapper_pg_dir, \
	280	.fpexc_mode = MSR_FE0 \| MSR_FE1, \
6a800f36	281	SPEFSCR_INIT \
1da177e4	282	}
9f04b9e3 PM	283	#else
	284	#define INIT_THREAD { \
	285	.ksp = INIT_SP, \
85218827	286	.ksp_limit = INIT_SP_LIMIT, \
9f04b9e3 PM	287	.regs = (struct pt_regs )INIT_SP - 1, / XXX bogus, I think */ \
9f04b9e3 PM	288	.fs = KERNEL_DS, \
e17a2565	289	.fpr = {{0}}, \
25c8a78b	290	.fpscr = { .val = 0, }, \
ddf5f75a	291	.fpexc_mode = 0, \
92779245	292	.ppr = INIT_PPR, \
9f04b9e3 PM	293	}
9f04b9e3 PM	294	#endif
1da177e4 LT	295
	296	/*
	297	* Return saved PC of a blocked thread. For now, this is the "user" PC
	298	*/
9f04b9e3 PM	299	#define thread_saved_pc(tsk) \
9f04b9e3 PM	300	((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
1da177e4	301
e5093ff0 SD	302	#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.regs)
e5093ff0 SD	303
1da177e4 LT	304	unsigned long get_wchan(struct task_struct *p);
1da177e4 LT	305
9f04b9e3 PM	306	#define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
9f04b9e3 PM	307	#define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
1da177e4 LT	308
1da177e4 LT	309	/* Get/set floating-point exception mode */
9f04b9e3 PM	310	#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
9f04b9e3 PM	311	#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
1da177e4 LT	312
	313	extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
	314	extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
	315
fab5db97 PM	316	#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
	317	#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
	318
	319	extern int get_endian(struct task_struct *tsk, unsigned long adr);
	320	extern int set_endian(struct task_struct *tsk, unsigned int val);
	321
e9370ae1 PM	322	#define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr))
	323	#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
	324
	325	extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
	326	extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
	327
9f04b9e3	328	static inline unsigned int __unpack_fe01(unsigned long msr_bits)
1da177e4 LT	329	{
	330	return ((msr_bits & MSR_FE0) >> 10) \| ((msr_bits & MSR_FE1) >> 8);
	331	}
	332
9f04b9e3	333	static inline unsigned long __pack_fe01(unsigned int fpmode)
1da177e4 LT	334	{
	335	return ((fpmode << 10) & MSR_FE0) \| ((fpmode << 8) & MSR_FE1);
	336	}
	337
9f04b9e3 PM	338	#ifdef CONFIG_PPC64
	339	#define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0)
	340	#else
1da177e4	341	#define cpu_relax() barrier()
9f04b9e3	342	#endif
1da177e4	343
2f25194d AB	344	/* Check that a certain kernel stack pointer is valid in task_struct p */
	345	int validate_sp(unsigned long sp, struct task_struct *p,
	346	unsigned long nbytes);
	347
1da177e4 LT	348	/*
	349	* Prefetch macros.
	350	*/
	351	#define ARCH_HAS_PREFETCH
	352	#define ARCH_HAS_PREFETCHW
	353	#define ARCH_HAS_SPINLOCK_PREFETCH
	354
9f04b9e3	355	static inline void prefetch(const void *x)
1da177e4	356	{
9f04b9e3 PM	357	if (unlikely(!x))
	358	return;
	359
	360	__asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
1da177e4 LT	361	}
1da177e4 LT	362
9f04b9e3	363	static inline void prefetchw(const void *x)
1da177e4	364	{
9f04b9e3 PM	365	if (unlikely(!x))
	366	return;
	367
	368	__asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
1da177e4 LT	369	}
	370
	371	#define spin_lock_prefetch(x) prefetchw(x)
	372
9f04b9e3 PM	373	#ifdef CONFIG_PPC64
	374	#define HAVE_ARCH_PICK_MMAP_LAYOUT
	375	#endif
1da177e4	376
efbda860 JB	377	#ifdef CONFIG_PPC64
	378	static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)
	379	{
	380	unsigned long sp;
	381
	382	if (is_32)
	383	sp = regs->gpr[1] & 0x0ffffffffUL;
	384	else
	385	sp = regs->gpr[1];
	386
	387	return sp;
	388	}
	389	#else
	390	static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)
	391	{
	392	return regs->gpr[1];
	393	}
	394	#endif
	395
e8bb3e00	396	extern unsigned long cpuidle_disable;
771dae81 DD	397	enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
771dae81 DD	398
ae3a197e	399	extern int powersave_nap; /* set if nap mode can be used in idle loop */
375f561a	400	extern void power7_nap(void);
ae3a197e DH	401
ae3a197e DH	402	#ifdef CONFIG_PSERIES_IDLE
8ea959a1	403	extern void update_smt_snooze_delay(int cpu, int residency);
ae3a197e	404	#else
8ea959a1	405	static inline void update_smt_snooze_delay(int cpu, int residency) {}
ae3a197e DH	406	#endif
	407
	408	extern void flush_instruction_cache(void);
	409	extern void hard_reset_now(void);
	410	extern void poweroff_now(void);
	411	extern int fix_alignment(struct pt_regs *);
	412	extern void cvt_fd(float from, double to);
	413	extern void cvt_df(double from, float to);
	414	extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
	415
	416	#ifdef CONFIG_PPC64
	417	/*
	418	* We handle most unaligned accesses in hardware. On the other hand
	419	* unaligned DMA can be very expensive on some ppc64 IO chips (it does
	420	* powers of 2 writes until it reaches sufficient alignment).
	421	*
	422	* Based on this we disable the IP header alignment in network drivers.
	423	*/
	424	#define NET_IP_ALIGN 0
	425	#endif
	426
1da177e4	427	#endif /* __KERNEL__ */
9f04b9e3 PM	428	#endif /* __ASSEMBLY__ */
9f04b9e3 PM	429	#endif /* _ASM_POWERPC_PROCESSOR_H */