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1 | #ifndef _ASM_POWERPC_PTE_44x_H |
2 | #define _ASM_POWERPC_PTE_44x_H | |
3 | #ifdef __KERNEL__ | |
4 | ||
5 | /* | |
6 | * Definitions for PPC440 | |
7 | * | |
8 | * Because of the 3 word TLB entries to support 36-bit addressing, | |
9 | * the attribute are difficult to map in such a fashion that they | |
10 | * are easily loaded during exception processing. I decided to | |
11 | * organize the entry so the ERPN is the only portion in the | |
12 | * upper word of the PTE and the attribute bits below are packed | |
13 | * in as sensibly as they can be in the area below a 4KB page size | |
14 | * oriented RPN. This at least makes it easy to load the RPN and | |
15 | * ERPN fields in the TLB. -Matt | |
16 | * | |
17 | * This isn't entirely true anymore, at least some bits are now | |
18 | * easier to move into the TLB from the PTE. -BenH. | |
19 | * | |
20 | * Note that these bits preclude future use of a page size | |
21 | * less than 4KB. | |
22 | * | |
23 | * | |
24 | * PPC 440 core has following TLB attribute fields; | |
25 | * | |
26 | * TLB1: | |
27 | * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 | |
28 | * RPN................................. - - - - - - ERPN....... | |
29 | * | |
30 | * TLB2: | |
31 | * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 | |
32 | * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR | |
33 | * | |
34 | * Newer 440 cores (440x6 as used on AMCC 460EX/460GT) have additional | |
35 | * TLB2 storage attibute fields. Those are: | |
36 | * | |
37 | * TLB2: | |
38 | * 0...10 11 12 13 14 15 16...31 | |
39 | * no change WL1 IL1I IL1D IL2I IL2D no change | |
40 | * | |
41 | * There are some constrains and options, to decide mapping software bits | |
42 | * into TLB entry. | |
43 | * | |
44 | * - PRESENT *must* be in the bottom three bits because swap cache | |
45 | * entries use the top 29 bits for TLB2. | |
46 | * | |
47 | * - FILE *must* be in the bottom three bits because swap cache | |
48 | * entries use the top 29 bits for TLB2. | |
49 | * | |
50 | * - CACHE COHERENT bit (M) has no effect on original PPC440 cores, | |
51 | * because it doesn't support SMP. However, some later 460 variants | |
52 | * have -some- form of SMP support and so I keep the bit there for | |
53 | * future use | |
54 | * | |
55 | * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used | |
56 | * for memory protection related functions (see PTE structure in | |
57 | * include/asm-ppc/mmu.h). The _PAGE_XXX definitions in this file map to the | |
58 | * above bits. Note that the bit values are CPU specific, not architecture | |
59 | * specific. | |
60 | * | |
61 | * The kernel PTE entry holds an arch-dependent swp_entry structure under | |
62 | * certain situations. In other words, in such situations some portion of | |
63 | * the PTE bits are used as a swp_entry. In the PPC implementation, the | |
64 | * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still | |
65 | * hold protection values. That means the three protection bits are | |
66 | * reserved for both PTE and SWAP entry at the most significant three | |
67 | * LSBs. | |
68 | * | |
69 | * There are three protection bits available for SWAP entry: | |
70 | * _PAGE_PRESENT | |
71 | * _PAGE_FILE | |
72 | * _PAGE_HASHPTE (if HW has) | |
73 | * | |
74 | * So those three bits have to be inside of 0-2nd LSB of PTE. | |
75 | * | |
76 | */ | |
77 | ||
78 | #define _PAGE_PRESENT 0x00000001 /* S: PTE valid */ | |
79 | #define _PAGE_RW 0x00000002 /* S: Write permission */ | |
80 | #define _PAGE_FILE 0x00000004 /* S: nonlinear file mapping */ | |
ea3cc330 | 81 | #define _PAGE_EXEC 0x00000004 /* H: Execute permission */ |
c605782b BH |
82 | #define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */ |
83 | #define _PAGE_DIRTY 0x00000010 /* S: Page dirty */ | |
84 | #define _PAGE_SPECIAL 0x00000020 /* S: Special page */ | |
85 | #define _PAGE_USER 0x00000040 /* S: User page */ | |
86 | #define _PAGE_ENDIAN 0x00000080 /* H: E bit */ | |
87 | #define _PAGE_GUARDED 0x00000100 /* H: G bit */ | |
88 | #define _PAGE_COHERENT 0x00000200 /* H: M bit */ | |
89 | #define _PAGE_NO_CACHE 0x00000400 /* H: I bit */ | |
90 | #define _PAGE_WRITETHRU 0x00000800 /* H: W bit */ | |
91 | ||
92 | /* TODO: Add large page lowmem mapping support */ | |
93 | #define _PMD_PRESENT 0 | |
94 | #define _PMD_PRESENT_MASK (PAGE_MASK) | |
95 | #define _PMD_BAD (~PAGE_MASK) | |
96 | ||
97 | /* ERPN in a PTE never gets cleared, ignore it */ | |
98 | #define _PTE_NONE_MASK 0xffffffff00000000ULL | |
99 | ||
100 | ||
101 | #endif /* __KERNEL__ */ | |
102 | #endif /* _ASM_POWERPC_PTE_44x_H */ |