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1 | #ifndef _ASM_POWERPC_PTE_8xx_H |
2 | #define _ASM_POWERPC_PTE_8xx_H | |
3 | #ifdef __KERNEL__ | |
4 | ||
5 | /* | |
6 | * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk. | |
7 | * We also use the two level tables, but we can put the real bits in them | |
8 | * needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0, | |
9 | * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has | |
10 | * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit | |
11 | * based upon user/super access. The TLB does not have accessed nor write | |
12 | * protect. We assume that if the TLB get loaded with an entry it is | |
13 | * accessed, and overload the changed bit for write protect. We use | |
14 | * two bits in the software pte that are supposed to be set to zero in | |
15 | * the TLB entry (24 and 25) for these indicators. Although the level 1 | |
16 | * descriptor contains the guarded and writethrough/copyback bits, we can | |
17 | * set these at the page level since they get copied from the Mx_TWC | |
18 | * register when the TLB entry is loaded. We will use bit 27 for guard, since | |
19 | * that is where it exists in the MD_TWC, and bit 26 for writethrough. | |
20 | * These will get masked from the level 2 descriptor at TLB load time, and | |
21 | * copied to the MD_TWC before it gets loaded. | |
22 | * Large page sizes added. We currently support two sizes, 4K and 8M. | |
23 | * This also allows a TLB hander optimization because we can directly | |
24 | * load the PMD into MD_TWC. The 8M pages are only used for kernel | |
25 | * mapping of well known areas. The PMD (PGD) entries contain control | |
26 | * flags in addition to the address, so care must be taken that the | |
27 | * software no longer assumes these are only pointers. | |
28 | */ | |
29 | ||
30 | /* Definitions for 8xx embedded chips. */ | |
31 | #define _PAGE_PRESENT 0x0001 /* Page is valid */ | |
32 | #define _PAGE_FILE 0x0002 /* when !present: nonlinear file mapping */ | |
33 | #define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */ | |
34 | #define _PAGE_SHARED 0x0004 /* No ASID (context) compare */ | |
35 | ||
36 | /* These five software bits must be masked out when the entry is loaded | |
37 | * into the TLB. | |
38 | */ | |
39 | #define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */ | |
40 | #define _PAGE_GUARDED 0x0010 /* software: guarded access */ | |
41 | #define _PAGE_DIRTY 0x0020 /* software: page changed */ | |
42 | #define _PAGE_RW 0x0040 /* software: user write access allowed */ | |
43 | #define _PAGE_ACCESSED 0x0080 /* software: page referenced */ | |
44 | ||
45 | /* Setting any bits in the nibble with the follow two controls will | |
46 | * require a TLB exception handler change. It is assumed unused bits | |
47 | * are always zero. | |
48 | */ | |
49 | #define _PAGE_HWWRITE 0x0100 /* h/w write enable: never set in Linux PTE */ | |
50 | #define _PAGE_USER 0x0800 /* One of the PP bits, the other is USER&~RW */ | |
51 | ||
52 | #define _PMD_PRESENT 0x0001 | |
53 | #define _PMD_BAD 0x0ff0 | |
54 | #define _PMD_PAGE_MASK 0x000c | |
55 | #define _PMD_PAGE_8M 0x000c | |
56 | ||
57 | #define _PTE_NONE_MASK _PAGE_ACCESSED | |
58 | ||
59 | /* Until my rework is finished, 8xx still needs atomic PTE updates */ | |
60 | #define PTE_ATOMIC_UPDATES 1 | |
61 | ||
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62 | /* We need to add _PAGE_SHARED to kernel pages */ |
63 | #define _PAGE_KERNEL_RO (_PAGE_SHARED) | |
64 | #define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW | _PAGE_HWWRITE) | |
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65 | |
66 | #endif /* __KERNEL__ */ | |
67 | #endif /* _ASM_POWERPC_PTE_8xx_H */ |