[deliverable/linux.git] / arch / powerpc / include / asm / pte-fsl-booke.h

#ifndef _ASM_POWERPC_PTE_FSL_BOOKE_H
#define _ASM_POWERPC_PTE_FSL_BOOKE_H
#ifdef __KERNEL__

/* PTE bit definitions for Freescale BookE SW loaded TLB MMU based
 * processors
 *
   MMU Assist Register 3:

   32 33 34 35 36  ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
   RPN......................  0  0 U0 U1 U2 U3 UX SX UW SW UR SR

   - PRESENT *must* be in the bottom three bits because swap cache
     entries use the top 29 bits.

   - FILE *must* be in the bottom three bits because swap cache
     entries use the top 29 bits.
*/

/* Definitions for FSL Book-E Cores */
#define _PAGE_PRESENT	0x00001	/* S: PTE contains a translation */
#define _PAGE_USER	0x00002	/* S: User page (maps to UR) */
#define _PAGE_FILE	0x00002	/* S: when !present: nonlinear file mapping */
#define _PAGE_RW	0x00004	/* S: Write permission (SW) */
#define _PAGE_DIRTY	0x00008	/* S: Page dirty */
#define _PAGE_EXEC	0x00010	/* H: SX permission */
#define _PAGE_ACCESSED	0x00020	/* S: Page referenced */

#define _PAGE_ENDIAN	0x00040	/* H: E bit */
#define _PAGE_GUARDED	0x00080	/* H: G bit */
#define _PAGE_COHERENT	0x00100	/* H: M bit */
#define _PAGE_NO_CACHE	0x00200	/* H: I bit */
#define _PAGE_WRITETHRU	0x00400	/* H: W bit */
#define _PAGE_SPECIAL	0x00800 /* S: Special page */

#define _PMD_PRESENT	0
#define _PMD_PRESENT_MASK (PAGE_MASK)
#define _PMD_BAD	(~PAGE_MASK)

#endif /* __KERNEL__ */
#endif /*  _ASM_POWERPC_PTE_FSL_BOOKE_H */
Commit	Line	Data
c605782b BH	1	#ifndef _ASM_POWERPC_PTE_FSL_BOOKE_H
	2	#define _ASM_POWERPC_PTE_FSL_BOOKE_H
	3	#ifdef __KERNEL__
	4
	5	/* PTE bit definitions for Freescale BookE SW loaded TLB MMU based
	6	* processors
	7	*
	8	MMU Assist Register 3:
	9
	10	32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
	11	RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR
	12
	13	- PRESENT must be in the bottom three bits because swap cache
	14	entries use the top 29 bits.
	15
	16	- FILE must be in the bottom three bits because swap cache
	17	entries use the top 29 bits.
	18	*/
	19
	20	/* Definitions for FSL Book-E Cores */
	21	#define _PAGE_PRESENT 0x00001 /* S: PTE contains a translation */
	22	#define _PAGE_USER 0x00002 /* S: User page (maps to UR) */
	23	#define _PAGE_FILE 0x00002 /* S: when !present: nonlinear file mapping */
	24	#define _PAGE_RW 0x00004 /* S: Write permission (SW) */
	25	#define _PAGE_DIRTY 0x00008 /* S: Page dirty */
ea3cc330	26	#define _PAGE_EXEC 0x00010 /* H: SX permission */
c605782b BH	27	#define _PAGE_ACCESSED 0x00020 /* S: Page referenced */
	28
	29	#define _PAGE_ENDIAN 0x00040 /* H: E bit */
	30	#define _PAGE_GUARDED 0x00080 /* H: G bit */
	31	#define _PAGE_COHERENT 0x00100 /* H: M bit */
	32	#define _PAGE_NO_CACHE 0x00200 /* H: I bit */
	33	#define _PAGE_WRITETHRU 0x00400 /* H: W bit */
	34	#define _PAGE_SPECIAL 0x00800 /* S: Special page */
	35
c605782b BH	36	#define _PMD_PRESENT 0
	37	#define _PMD_PRESENT_MASK (PAGE_MASK)
	38	#define _PMD_BAD (~PAGE_MASK)
	39
	40	#endif /* __KERNEL__ */
	41	#endif /* _ASM_POWERPC_PTE_FSL_BOOKE_H */