Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
5ad57078 | 2 | * smp.h: PowerPC-specific SMP code. |
1da177e4 LT |
3 | * |
4 | * Original was a copy of sparc smp.h. Now heavily modified | |
5 | * for PPC. | |
6 | * | |
7 | * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) | |
8 | * Copyright (C) 1996-2001 Cort Dougan <cort@fsmlabs.com> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License | |
12 | * as published by the Free Software Foundation; either version | |
13 | * 2 of the License, or (at your option) any later version. | |
14 | */ | |
15 | ||
5ad57078 PM |
16 | #ifndef _ASM_POWERPC_SMP_H |
17 | #define _ASM_POWERPC_SMP_H | |
1da177e4 | 18 | #ifdef __KERNEL__ |
1da177e4 | 19 | |
1da177e4 LT |
20 | #include <linux/threads.h> |
21 | #include <linux/cpumask.h> | |
22 | #include <linux/kernel.h> | |
23d72bfd | 23 | #include <linux/irqreturn.h> |
1da177e4 LT |
24 | |
25 | #ifndef __ASSEMBLY__ | |
26 | ||
5ad57078 | 27 | #ifdef CONFIG_PPC64 |
1da177e4 | 28 | #include <asm/paca.h> |
5ad57078 | 29 | #endif |
d5a7430d | 30 | #include <asm/percpu.h> |
1da177e4 LT |
31 | |
32 | extern int boot_cpuid; | |
7ac87abb | 33 | extern int spinning_secondaries; |
1da177e4 LT |
34 | |
35 | extern void cpu_die(void); | |
36 | ||
37 | #ifdef CONFIG_SMP | |
38 | ||
17f9c8a7 MM |
39 | struct smp_ops_t { |
40 | void (*message_pass)(int cpu, int msg); | |
1ece355b | 41 | #ifdef CONFIG_PPC_SMP_MUXED_IPI |
23d72bfd | 42 | void (*cause_ipi)(int cpu, unsigned long data); |
1ece355b | 43 | #endif |
17f9c8a7 MM |
44 | int (*probe)(void); |
45 | int (*kick_cpu)(int nr); | |
46 | void (*setup_cpu)(int nr); | |
47 | void (*bringup_done)(void); | |
48 | void (*take_timebase)(void); | |
49 | void (*give_timebase)(void); | |
50 | int (*cpu_disable)(void); | |
51 | void (*cpu_die)(unsigned int nr); | |
52 | int (*cpu_bootable)(unsigned int nr); | |
53 | }; | |
54 | ||
e0476371 | 55 | extern void smp_send_debugger_break(void); |
fa3f82c8 | 56 | extern void start_secondary_resume(void); |
17f9c8a7 MM |
57 | extern void __devinit smp_generic_give_timebase(void); |
58 | extern void __devinit smp_generic_take_timebase(void); | |
1da177e4 | 59 | |
6b7487fc | 60 | DECLARE_PER_CPU(unsigned int, cpu_pvr); |
1c21a293 | 61 | |
1da177e4 | 62 | #ifdef CONFIG_HOTPLUG_CPU |
1c91cc57 | 63 | extern void migrate_irqs(void); |
1da177e4 | 64 | int generic_cpu_disable(void); |
1da177e4 LT |
65 | void generic_cpu_die(unsigned int cpu); |
66 | void generic_mach_cpu_die(void); | |
105765f4 | 67 | void generic_set_cpu_dead(unsigned int cpu); |
ae5cab47 | 68 | void generic_set_cpu_up(unsigned int cpu); |
fb82b839 | 69 | int generic_check_cpu_restart(unsigned int cpu); |
512691d4 PM |
70 | |
71 | extern void inhibit_secondary_onlining(void); | |
72 | extern void uninhibit_secondary_onlining(void); | |
73 | ||
74 | #else /* HOTPLUG_CPU */ | |
75 | static inline void inhibit_secondary_onlining(void) {} | |
76 | static inline void uninhibit_secondary_onlining(void) {} | |
77 | ||
1da177e4 LT |
78 | #endif |
79 | ||
5ad57078 | 80 | #ifdef CONFIG_PPC64 |
048c8bc9 | 81 | #define raw_smp_processor_id() (local_paca->paca_index) |
1da177e4 | 82 | #define hard_smp_processor_id() (get_paca()->hw_cpu_id) |
5ad57078 PM |
83 | #else |
84 | /* 32-bit */ | |
85 | extern int smp_hw_index[]; | |
86 | ||
87 | #define raw_smp_processor_id() (current_thread_info()->cpu) | |
88 | #define hard_smp_processor_id() (smp_hw_index[smp_processor_id()]) | |
41eba0ad BH |
89 | |
90 | static inline int get_hard_smp_processor_id(int cpu) | |
91 | { | |
92 | return smp_hw_index[cpu]; | |
93 | } | |
94 | ||
95 | static inline void set_hard_smp_processor_id(int cpu, int phys) | |
96 | { | |
97 | smp_hw_index[cpu] = phys; | |
98 | } | |
5ad57078 | 99 | #endif |
1da177e4 | 100 | |
cc1ba8ea AB |
101 | DECLARE_PER_CPU(cpumask_var_t, cpu_sibling_map); |
102 | DECLARE_PER_CPU(cpumask_var_t, cpu_core_map); | |
103 | ||
104 | static inline struct cpumask *cpu_sibling_mask(int cpu) | |
105 | { | |
106 | return per_cpu(cpu_sibling_map, cpu); | |
107 | } | |
108 | ||
109 | static inline struct cpumask *cpu_core_mask(int cpu) | |
110 | { | |
111 | return per_cpu(cpu_core_map, cpu); | |
112 | } | |
113 | ||
e9efed3b | 114 | extern int cpu_to_core_id(int cpu); |
1da177e4 LT |
115 | |
116 | /* Since OpenPIC has only 4 IPIs, we use slightly different message numbers. | |
117 | * | |
118 | * Make sure this matches openpic_request_IPIs in open_pic.c, or what shows up | |
119 | * in /proc/interrupts will be wrong!!! --Troy */ | |
120 | #define PPC_MSG_CALL_FUNCTION 0 | |
121 | #define PPC_MSG_RESCHEDULE 1 | |
b7d7a240 | 122 | #define PPC_MSG_CALL_FUNC_SINGLE 2 |
1da177e4 LT |
123 | #define PPC_MSG_DEBUGGER_BREAK 3 |
124 | ||
23d72bfd | 125 | /* for irq controllers that have dedicated ipis per message (4) */ |
25ddd738 MM |
126 | extern int smp_request_message_ipi(int virq, int message); |
127 | extern const char *smp_ipi_name[]; | |
128 | ||
23d72bfd MM |
129 | /* for irq controllers with only a single ipi */ |
130 | extern void smp_muxed_ipi_set_data(int cpu, unsigned long data); | |
131 | extern void smp_muxed_ipi_message_pass(int cpu, int msg); | |
23d72bfd MM |
132 | extern irqreturn_t smp_ipi_demux(void); |
133 | ||
1da177e4 | 134 | void smp_init_pSeries(void); |
19fe0475 | 135 | void smp_init_cell(void); |
c347b798 | 136 | void smp_init_celleb(void); |
5ad57078 | 137 | void smp_setup_cpu_maps(void); |
1da177e4 LT |
138 | |
139 | extern int __cpu_disable(void); | |
140 | extern void __cpu_die(unsigned int cpu); | |
5ad57078 PM |
141 | |
142 | #else | |
143 | /* for UP */ | |
78b5b626 | 144 | #define hard_smp_processor_id() get_hard_smp_processor_id(0) |
5ad57078 | 145 | #define smp_setup_cpu_maps() |
5ad57078 | 146 | |
1da177e4 LT |
147 | #endif /* CONFIG_SMP */ |
148 | ||
5ad57078 | 149 | #ifdef CONFIG_PPC64 |
41eba0ad BH |
150 | static inline int get_hard_smp_processor_id(int cpu) |
151 | { | |
152 | return paca[cpu].hw_cpu_id; | |
153 | } | |
154 | ||
155 | static inline void set_hard_smp_processor_id(int cpu, int phys) | |
156 | { | |
157 | paca[cpu].hw_cpu_id = phys; | |
158 | } | |
2249ca9d PM |
159 | |
160 | extern void smp_release_cpus(void); | |
161 | ||
5ad57078 PM |
162 | #else |
163 | /* 32-bit */ | |
164 | #ifndef CONFIG_SMP | |
4df20460 | 165 | extern int boot_cpuid_phys; |
41eba0ad BH |
166 | static inline int get_hard_smp_processor_id(int cpu) |
167 | { | |
168 | return boot_cpuid_phys; | |
169 | } | |
170 | ||
171 | static inline void set_hard_smp_processor_id(int cpu, int phys) | |
172 | { | |
78b5b626 | 173 | boot_cpuid_phys = phys; |
41eba0ad BH |
174 | } |
175 | #endif /* !CONFIG_SMP */ | |
176 | #endif /* !CONFIG_PPC64 */ | |
1da177e4 LT |
177 | |
178 | extern int smt_enabled_at_boot; | |
179 | ||
180 | extern int smp_mpic_probe(void); | |
181 | extern void smp_mpic_setup_cpu(int cpu); | |
de300974 | 182 | extern int smp_generic_kick_cpu(int nr); |
1da177e4 LT |
183 | |
184 | extern void smp_generic_give_timebase(void); | |
185 | extern void smp_generic_take_timebase(void); | |
186 | ||
187 | extern struct smp_ops_t *smp_ops; | |
188 | ||
b7d7a240 | 189 | extern void arch_send_call_function_single_ipi(int cpu); |
f063ea02 | 190 | extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); |
b7d7a240 | 191 | |
cf54dc7c BH |
192 | /* Definitions relative to the secondary CPU spin loop |
193 | * and entry point. Not all of them exist on both 32 and | |
194 | * 64-bit but defining them all here doesn't harm | |
195 | */ | |
196 | extern void generic_secondary_smp_init(void); | |
2d27cfd3 | 197 | extern void generic_secondary_thread_init(void); |
cf54dc7c BH |
198 | extern unsigned long __secondary_hold_spinloop; |
199 | extern unsigned long __secondary_hold_acknowledge; | |
200 | extern char __secondary_hold; | |
201 | ||
d0832a75 | 202 | extern void __early_start(void); |
1da177e4 LT |
203 | #endif /* __ASSEMBLY__ */ |
204 | ||
1da177e4 | 205 | #endif /* __KERNEL__ */ |
5ad57078 | 206 | #endif /* _ASM_POWERPC_SMP_H) */ |