Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
5ad57078 | 2 | * smp.h: PowerPC-specific SMP code. |
1da177e4 LT |
3 | * |
4 | * Original was a copy of sparc smp.h. Now heavily modified | |
5 | * for PPC. | |
6 | * | |
7 | * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) | |
8 | * Copyright (C) 1996-2001 Cort Dougan <cort@fsmlabs.com> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License | |
12 | * as published by the Free Software Foundation; either version | |
13 | * 2 of the License, or (at your option) any later version. | |
14 | */ | |
15 | ||
5ad57078 PM |
16 | #ifndef _ASM_POWERPC_SMP_H |
17 | #define _ASM_POWERPC_SMP_H | |
1da177e4 | 18 | #ifdef __KERNEL__ |
1da177e4 | 19 | |
1da177e4 LT |
20 | #include <linux/threads.h> |
21 | #include <linux/cpumask.h> | |
22 | #include <linux/kernel.h> | |
23d72bfd | 23 | #include <linux/irqreturn.h> |
1da177e4 LT |
24 | |
25 | #ifndef __ASSEMBLY__ | |
26 | ||
5ad57078 | 27 | #ifdef CONFIG_PPC64 |
1da177e4 | 28 | #include <asm/paca.h> |
5ad57078 | 29 | #endif |
d5a7430d | 30 | #include <asm/percpu.h> |
1da177e4 LT |
31 | |
32 | extern int boot_cpuid; | |
7ac87abb | 33 | extern int spinning_secondaries; |
1da177e4 LT |
34 | |
35 | extern void cpu_die(void); | |
36 | ||
37 | #ifdef CONFIG_SMP | |
38 | ||
17f9c8a7 MM |
39 | struct smp_ops_t { |
40 | void (*message_pass)(int cpu, int msg); | |
1ece355b | 41 | #ifdef CONFIG_PPC_SMP_MUXED_IPI |
23d72bfd | 42 | void (*cause_ipi)(int cpu, unsigned long data); |
1ece355b | 43 | #endif |
17f9c8a7 MM |
44 | int (*probe)(void); |
45 | int (*kick_cpu)(int nr); | |
46 | void (*setup_cpu)(int nr); | |
47 | void (*bringup_done)(void); | |
48 | void (*take_timebase)(void); | |
49 | void (*give_timebase)(void); | |
50 | int (*cpu_disable)(void); | |
51 | void (*cpu_die)(unsigned int nr); | |
52 | int (*cpu_bootable)(unsigned int nr); | |
53 | }; | |
54 | ||
e0476371 | 55 | extern void smp_send_debugger_break(void); |
fa3f82c8 | 56 | extern void start_secondary_resume(void); |
17f9c8a7 MM |
57 | extern void __devinit smp_generic_give_timebase(void); |
58 | extern void __devinit smp_generic_take_timebase(void); | |
1da177e4 | 59 | |
6b7487fc | 60 | DECLARE_PER_CPU(unsigned int, cpu_pvr); |
1c21a293 | 61 | |
1da177e4 | 62 | #ifdef CONFIG_HOTPLUG_CPU |
1c91cc57 | 63 | extern void migrate_irqs(void); |
1da177e4 | 64 | int generic_cpu_disable(void); |
1da177e4 LT |
65 | void generic_cpu_die(unsigned int cpu); |
66 | void generic_mach_cpu_die(void); | |
105765f4 | 67 | void generic_set_cpu_dead(unsigned int cpu); |
fb82b839 | 68 | int generic_check_cpu_restart(unsigned int cpu); |
1da177e4 LT |
69 | #endif |
70 | ||
5ad57078 | 71 | #ifdef CONFIG_PPC64 |
048c8bc9 | 72 | #define raw_smp_processor_id() (local_paca->paca_index) |
1da177e4 | 73 | #define hard_smp_processor_id() (get_paca()->hw_cpu_id) |
5ad57078 PM |
74 | #else |
75 | /* 32-bit */ | |
76 | extern int smp_hw_index[]; | |
77 | ||
78 | #define raw_smp_processor_id() (current_thread_info()->cpu) | |
79 | #define hard_smp_processor_id() (smp_hw_index[smp_processor_id()]) | |
41eba0ad BH |
80 | |
81 | static inline int get_hard_smp_processor_id(int cpu) | |
82 | { | |
83 | return smp_hw_index[cpu]; | |
84 | } | |
85 | ||
86 | static inline void set_hard_smp_processor_id(int cpu, int phys) | |
87 | { | |
88 | smp_hw_index[cpu] = phys; | |
89 | } | |
5ad57078 | 90 | #endif |
1da177e4 | 91 | |
cc1ba8ea AB |
92 | DECLARE_PER_CPU(cpumask_var_t, cpu_sibling_map); |
93 | DECLARE_PER_CPU(cpumask_var_t, cpu_core_map); | |
94 | ||
95 | static inline struct cpumask *cpu_sibling_mask(int cpu) | |
96 | { | |
97 | return per_cpu(cpu_sibling_map, cpu); | |
98 | } | |
99 | ||
100 | static inline struct cpumask *cpu_core_mask(int cpu) | |
101 | { | |
102 | return per_cpu(cpu_core_map, cpu); | |
103 | } | |
104 | ||
e9efed3b | 105 | extern int cpu_to_core_id(int cpu); |
1da177e4 LT |
106 | |
107 | /* Since OpenPIC has only 4 IPIs, we use slightly different message numbers. | |
108 | * | |
109 | * Make sure this matches openpic_request_IPIs in open_pic.c, or what shows up | |
110 | * in /proc/interrupts will be wrong!!! --Troy */ | |
111 | #define PPC_MSG_CALL_FUNCTION 0 | |
112 | #define PPC_MSG_RESCHEDULE 1 | |
b7d7a240 | 113 | #define PPC_MSG_CALL_FUNC_SINGLE 2 |
1da177e4 LT |
114 | #define PPC_MSG_DEBUGGER_BREAK 3 |
115 | ||
23d72bfd | 116 | /* for irq controllers that have dedicated ipis per message (4) */ |
25ddd738 MM |
117 | extern int smp_request_message_ipi(int virq, int message); |
118 | extern const char *smp_ipi_name[]; | |
119 | ||
23d72bfd MM |
120 | /* for irq controllers with only a single ipi */ |
121 | extern void smp_muxed_ipi_set_data(int cpu, unsigned long data); | |
122 | extern void smp_muxed_ipi_message_pass(int cpu, int msg); | |
23d72bfd MM |
123 | extern irqreturn_t smp_ipi_demux(void); |
124 | ||
1da177e4 LT |
125 | void smp_init_iSeries(void); |
126 | void smp_init_pSeries(void); | |
19fe0475 | 127 | void smp_init_cell(void); |
c347b798 | 128 | void smp_init_celleb(void); |
5ad57078 | 129 | void smp_setup_cpu_maps(void); |
1da177e4 LT |
130 | |
131 | extern int __cpu_disable(void); | |
132 | extern void __cpu_die(unsigned int cpu); | |
5ad57078 PM |
133 | |
134 | #else | |
135 | /* for UP */ | |
78b5b626 | 136 | #define hard_smp_processor_id() get_hard_smp_processor_id(0) |
5ad57078 | 137 | #define smp_setup_cpu_maps() |
5ad57078 | 138 | |
1da177e4 LT |
139 | #endif /* CONFIG_SMP */ |
140 | ||
5ad57078 | 141 | #ifdef CONFIG_PPC64 |
41eba0ad BH |
142 | static inline int get_hard_smp_processor_id(int cpu) |
143 | { | |
144 | return paca[cpu].hw_cpu_id; | |
145 | } | |
146 | ||
147 | static inline void set_hard_smp_processor_id(int cpu, int phys) | |
148 | { | |
149 | paca[cpu].hw_cpu_id = phys; | |
150 | } | |
2249ca9d PM |
151 | |
152 | extern void smp_release_cpus(void); | |
153 | ||
5ad57078 PM |
154 | #else |
155 | /* 32-bit */ | |
156 | #ifndef CONFIG_SMP | |
4df20460 | 157 | extern int boot_cpuid_phys; |
41eba0ad BH |
158 | static inline int get_hard_smp_processor_id(int cpu) |
159 | { | |
160 | return boot_cpuid_phys; | |
161 | } | |
162 | ||
163 | static inline void set_hard_smp_processor_id(int cpu, int phys) | |
164 | { | |
78b5b626 | 165 | boot_cpuid_phys = phys; |
41eba0ad BH |
166 | } |
167 | #endif /* !CONFIG_SMP */ | |
168 | #endif /* !CONFIG_PPC64 */ | |
1da177e4 LT |
169 | |
170 | extern int smt_enabled_at_boot; | |
171 | ||
172 | extern int smp_mpic_probe(void); | |
173 | extern void smp_mpic_setup_cpu(int cpu); | |
de300974 | 174 | extern int smp_generic_kick_cpu(int nr); |
1da177e4 LT |
175 | |
176 | extern void smp_generic_give_timebase(void); | |
177 | extern void smp_generic_take_timebase(void); | |
178 | ||
179 | extern struct smp_ops_t *smp_ops; | |
180 | ||
b7d7a240 | 181 | extern void arch_send_call_function_single_ipi(int cpu); |
f063ea02 | 182 | extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); |
b7d7a240 | 183 | |
cf54dc7c BH |
184 | /* Definitions relative to the secondary CPU spin loop |
185 | * and entry point. Not all of them exist on both 32 and | |
186 | * 64-bit but defining them all here doesn't harm | |
187 | */ | |
188 | extern void generic_secondary_smp_init(void); | |
2d27cfd3 | 189 | extern void generic_secondary_thread_init(void); |
cf54dc7c BH |
190 | extern unsigned long __secondary_hold_spinloop; |
191 | extern unsigned long __secondary_hold_acknowledge; | |
192 | extern char __secondary_hold; | |
193 | ||
1da177e4 LT |
194 | #endif /* __ASSEMBLY__ */ |
195 | ||
1da177e4 | 196 | #endif /* __KERNEL__ */ |
5ad57078 | 197 | #endif /* _ASM_POWERPC_SMP_H) */ |