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67207b96 AB |
1 | /* |
2 | * SPU core / file system interface and HW structures | |
3 | * | |
4 | * (C) Copyright IBM Deutschland Entwicklung GmbH 2005 | |
5 | * | |
6 | * Author: Arnd Bergmann <arndb@de.ibm.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #ifndef _SPU_H | |
24 | #define _SPU_H | |
88ced031 AB |
25 | #ifdef __KERNEL__ |
26 | ||
67207b96 | 27 | #include <linux/workqueue.h> |
8a25a2fd | 28 | #include <linux/device.h> |
e415372a | 29 | #include <linux/mutex.h> |
67207b96 | 30 | |
aeb01377 | 31 | #define LS_SIZE (256 * 1024) |
5473af04 MN |
32 | #define LS_ADDR_MASK (LS_SIZE - 1) |
33 | ||
34 | #define MFC_PUT_CMD 0x20 | |
35 | #define MFC_PUTS_CMD 0x28 | |
36 | #define MFC_PUTR_CMD 0x30 | |
37 | #define MFC_PUTF_CMD 0x22 | |
38 | #define MFC_PUTB_CMD 0x21 | |
39 | #define MFC_PUTFS_CMD 0x2A | |
40 | #define MFC_PUTBS_CMD 0x29 | |
41 | #define MFC_PUTRF_CMD 0x32 | |
42 | #define MFC_PUTRB_CMD 0x31 | |
43 | #define MFC_PUTL_CMD 0x24 | |
44 | #define MFC_PUTRL_CMD 0x34 | |
45 | #define MFC_PUTLF_CMD 0x26 | |
46 | #define MFC_PUTLB_CMD 0x25 | |
47 | #define MFC_PUTRLF_CMD 0x36 | |
48 | #define MFC_PUTRLB_CMD 0x35 | |
49 | ||
50 | #define MFC_GET_CMD 0x40 | |
51 | #define MFC_GETS_CMD 0x48 | |
52 | #define MFC_GETF_CMD 0x42 | |
53 | #define MFC_GETB_CMD 0x41 | |
54 | #define MFC_GETFS_CMD 0x4A | |
55 | #define MFC_GETBS_CMD 0x49 | |
56 | #define MFC_GETL_CMD 0x44 | |
57 | #define MFC_GETLF_CMD 0x46 | |
58 | #define MFC_GETLB_CMD 0x45 | |
59 | ||
60 | #define MFC_SDCRT_CMD 0x80 | |
61 | #define MFC_SDCRTST_CMD 0x81 | |
62 | #define MFC_SDCRZ_CMD 0x89 | |
63 | #define MFC_SDCRS_CMD 0x8D | |
64 | #define MFC_SDCRF_CMD 0x8F | |
65 | ||
66 | #define MFC_GETLLAR_CMD 0xD0 | |
67 | #define MFC_PUTLLC_CMD 0xB4 | |
68 | #define MFC_PUTLLUC_CMD 0xB0 | |
69 | #define MFC_PUTQLLUC_CMD 0xB8 | |
70 | #define MFC_SNDSIG_CMD 0xA0 | |
71 | #define MFC_SNDSIGB_CMD 0xA1 | |
72 | #define MFC_SNDSIGF_CMD 0xA2 | |
73 | #define MFC_BARRIER_CMD 0xC0 | |
74 | #define MFC_EIEIO_CMD 0xC8 | |
75 | #define MFC_SYNC_CMD 0xCC | |
76 | ||
77 | #define MFC_MIN_DMA_SIZE_SHIFT 4 /* 16 bytes */ | |
78 | #define MFC_MAX_DMA_SIZE_SHIFT 14 /* 16384 bytes */ | |
79 | #define MFC_MIN_DMA_SIZE (1 << MFC_MIN_DMA_SIZE_SHIFT) | |
80 | #define MFC_MAX_DMA_SIZE (1 << MFC_MAX_DMA_SIZE_SHIFT) | |
81 | #define MFC_MIN_DMA_SIZE_MASK (MFC_MIN_DMA_SIZE - 1) | |
82 | #define MFC_MAX_DMA_SIZE_MASK (MFC_MAX_DMA_SIZE - 1) | |
83 | #define MFC_MIN_DMA_LIST_SIZE 0x0008 /* 8 bytes */ | |
84 | #define MFC_MAX_DMA_LIST_SIZE 0x4000 /* 16K bytes */ | |
85 | ||
86 | #define MFC_TAGID_TO_TAGMASK(tag_id) (1 << (tag_id & 0x1F)) | |
87 | ||
88 | /* Events for Channels 0-2 */ | |
89 | #define MFC_DMA_TAG_STATUS_UPDATE_EVENT 0x00000001 | |
90 | #define MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT 0x00000002 | |
91 | #define MFC_DMA_QUEUE_AVAILABLE_EVENT 0x00000008 | |
92 | #define MFC_SPU_MAILBOX_WRITTEN_EVENT 0x00000010 | |
93 | #define MFC_DECREMENTER_EVENT 0x00000020 | |
94 | #define MFC_PU_INT_MAILBOX_AVAILABLE_EVENT 0x00000040 | |
95 | #define MFC_PU_MAILBOX_AVAILABLE_EVENT 0x00000080 | |
96 | #define MFC_SIGNAL_2_EVENT 0x00000100 | |
97 | #define MFC_SIGNAL_1_EVENT 0x00000200 | |
98 | #define MFC_LLR_LOST_EVENT 0x00000400 | |
99 | #define MFC_PRIV_ATTN_EVENT 0x00000800 | |
100 | #define MFC_MULTI_SRC_EVENT 0x00001000 | |
101 | ||
61b36fc1 | 102 | /* Flag indicating progress during context switch. */ |
8837d921 | 103 | #define SPU_CONTEXT_SWITCH_PENDING 0UL |
de102892 | 104 | #define SPU_CONTEXT_FAULT_PENDING 1UL |
67207b96 | 105 | |
8b3d6663 AB |
106 | struct spu_context; |
107 | struct spu_runqueue; | |
58bd403c | 108 | struct spu_lscsa; |
c9868fe0 | 109 | struct device_node; |
8b3d6663 | 110 | |
fe2f896d | 111 | enum spu_utilization_state { |
fe2f896d | 112 | SPU_UTIL_USER, |
27ec41d3 | 113 | SPU_UTIL_SYSTEM, |
fe2f896d | 114 | SPU_UTIL_IOWAIT, |
27ec41d3 | 115 | SPU_UTIL_IDLE_LOADED, |
fe2f896d CH |
116 | SPU_UTIL_MAX |
117 | }; | |
118 | ||
67207b96 | 119 | struct spu { |
c61c27d5 | 120 | const char *name; |
67207b96 AB |
121 | unsigned long local_store_phys; |
122 | u8 *local_store; | |
6df10a82 | 123 | unsigned long problem_phys; |
67207b96 | 124 | struct spu_problem __iomem *problem; |
67207b96 | 125 | struct spu_priv2 __iomem *priv2; |
aa6d5b20 | 126 | struct list_head cbe_list; |
e570beb6 | 127 | struct list_head full_list; |
486acd48 | 128 | enum { SPU_FREE, SPU_USED } alloc_state; |
67207b96 | 129 | int number; |
0ebfff14 | 130 | unsigned int irqs[3]; |
67207b96 | 131 | u32 node; |
ee418b86 | 132 | unsigned long flags; |
b7f90a40 | 133 | u64 class_0_pending; |
f3d69e05 | 134 | u64 class_0_dar; |
f3d69e05 LB |
135 | u64 class_1_dar; |
136 | u64 class_1_dsisr; | |
67207b96 AB |
137 | size_t ls_size; |
138 | unsigned int slb_replace; | |
139 | struct mm_struct *mm; | |
8b3d6663 AB |
140 | struct spu_context *ctx; |
141 | struct spu_runqueue *rq; | |
2a911f0b | 142 | unsigned long long timestamp; |
8b3d6663 | 143 | pid_t pid; |
1474855d | 144 | pid_t tgid; |
67207b96 AB |
145 | spinlock_t register_lock; |
146 | ||
8b3d6663 AB |
147 | void (* wbox_callback)(struct spu *spu); |
148 | void (* ibox_callback)(struct spu *spu); | |
f3d69e05 | 149 | void (* stop_callback)(struct spu *spu, int irq); |
a33a7d73 | 150 | void (* mfc_callback)(struct spu *spu); |
67207b96 AB |
151 | |
152 | char irq_c0[8]; | |
153 | char irq_c1[8]; | |
154 | char irq_c2[8]; | |
1d64093f | 155 | |
c9868fe0 IK |
156 | u64 spe_id; |
157 | ||
e28b0031 | 158 | void* pdata; /* platform private data */ |
c9868fe0 IK |
159 | |
160 | /* of based platforms only */ | |
161 | struct device_node *devnode; | |
162 | ||
163 | /* native only */ | |
164 | struct spu_priv1 __iomem *priv1; | |
165 | ||
166 | /* beat only */ | |
167 | u64 shadow_int_mask_RW[3]; | |
168 | ||
8a25a2fd | 169 | struct device dev; |
e9f8a0b6 | 170 | |
9d92af62 AB |
171 | int has_mem_affinity; |
172 | struct list_head aff_list; | |
173 | ||
e9f8a0b6 CH |
174 | struct { |
175 | /* protected by interrupt reentrancy */ | |
27ec41d3 AD |
176 | enum spu_utilization_state util_state; |
177 | unsigned long long tstamp; | |
178 | unsigned long long times[SPU_UTIL_MAX]; | |
fe2f896d CH |
179 | unsigned long long vol_ctx_switch; |
180 | unsigned long long invol_ctx_switch; | |
181 | unsigned long long min_flt; | |
182 | unsigned long long maj_flt; | |
183 | unsigned long long hash_flt; | |
e9f8a0b6 CH |
184 | unsigned long long slb_flt; |
185 | unsigned long long class2_intr; | |
fe2f896d | 186 | unsigned long long libassist; |
e9f8a0b6 | 187 | } stats; |
67207b96 AB |
188 | }; |
189 | ||
aa6d5b20 | 190 | struct cbe_spu_info { |
486acd48 | 191 | struct mutex list_mutex; |
aa6d5b20 | 192 | struct list_head spus; |
aa6d5b20 | 193 | int n_spus; |
486acd48 | 194 | int nr_active; |
fabb6570 | 195 | atomic_t busy_spus; |
aa6d5b20 AB |
196 | atomic_t reserved_spus; |
197 | }; | |
198 | ||
199 | extern struct cbe_spu_info cbe_spu_info[]; | |
200 | ||
486acd48 | 201 | void spu_init_channels(struct spu *spu); |
2fb9d206 | 202 | void spu_irq_setaffinity(struct spu *spu, int cpu); |
67207b96 | 203 | |
684bd614 JK |
204 | void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa, |
205 | void *code, int code_size); | |
58bd403c | 206 | |
94b2a439 BH |
207 | extern void spu_invalidate_slbs(struct spu *spu); |
208 | extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm); | |
f6eb7d7f | 209 | int spu_64k_pages_available(void); |
94b2a439 BH |
210 | |
211 | /* Calls from the memory management to the SPU */ | |
212 | struct mm_struct; | |
213 | extern void spu_flush_all_slbs(struct mm_struct *mm); | |
214 | ||
1474855d BN |
215 | /* This interface allows a profiler (e.g., OProfile) to store a ref |
216 | * to spu context information that it creates. This caching technique | |
217 | * avoids the need to recreate this information after a save/restore operation. | |
218 | * | |
219 | * Assumes the caller has already incremented the ref count to | |
220 | * profile_info; then spu_context_destroy must call kref_put | |
221 | * on prof_info_kref. | |
222 | */ | |
223 | void spu_set_profile_private_kref(struct spu_context *ctx, | |
224 | struct kref *prof_info_kref, | |
225 | void ( * prof_info_release) (struct kref *kref)); | |
226 | ||
227 | void *spu_get_profile_private_kref(struct spu_context *ctx); | |
228 | ||
2dd14934 AB |
229 | /* system callbacks from the SPU */ |
230 | struct spu_syscall_block { | |
231 | u64 nr_ret; | |
232 | u64 parm[6]; | |
233 | }; | |
234 | extern long spu_sys_callback(struct spu_syscall_block *s); | |
235 | ||
236 | /* syscalls implemented in spufs */ | |
f1fa16e8 | 237 | struct file; |
cdc3d562 | 238 | struct coredump_params; |
98f06978 | 239 | struct spufs_calls { |
4ec3c3d0 | 240 | long (*create_thread)(const char __user *name, |
c6684b26 | 241 | unsigned int flags, umode_t mode, |
8e68e2f2 | 242 | struct file *neighbor); |
4ec3c3d0 | 243 | long (*spu_run)(struct file *filp, __u32 __user *unpc, |
67207b96 | 244 | __u32 __user *ustatus); |
48cad41f | 245 | int (*coredump_extra_notes_size)(void); |
cdc3d562 | 246 | int (*coredump_extra_notes_write)(struct coredump_params *cprm); |
aed3a8c9 | 247 | void (*notify_spus_active)(void); |
bf1ab978 DGM |
248 | struct module *owner; |
249 | }; | |
250 | ||
9add11da AB |
251 | /* return status from spu_run, same as in libspe */ |
252 | #define SPE_EVENT_DMA_ALIGNMENT 0x0008 /*A DMA alignment error */ | |
253 | #define SPE_EVENT_SPE_ERROR 0x0010 /*An illegal instruction error*/ | |
254 | #define SPE_EVENT_SPE_DATA_SEGMENT 0x0020 /*A DMA segmentation error */ | |
255 | #define SPE_EVENT_SPE_DATA_STORAGE 0x0040 /*A DMA storage error */ | |
256 | #define SPE_EVENT_INVALID_DMA 0x0800 /* Invalid MFC DMA */ | |
257 | ||
258 | /* | |
259 | * Flags for sys_spu_create. | |
260 | */ | |
261 | #define SPU_CREATE_EVENTS_ENABLED 0x0001 | |
6263203e | 262 | #define SPU_CREATE_GANG 0x0002 |
5737edd1 MN |
263 | #define SPU_CREATE_NOSCHED 0x0004 |
264 | #define SPU_CREATE_ISOLATE 0x0008 | |
8e68e2f2 AB |
265 | #define SPU_CREATE_AFFINITY_SPU 0x0010 |
266 | #define SPU_CREATE_AFFINITY_MEM 0x0020 | |
6263203e | 267 | |
8e68e2f2 | 268 | #define SPU_CREATE_FLAG_ALL 0x003f /* mask of all valid flags */ |
6263203e | 269 | |
9add11da | 270 | |
67207b96 AB |
271 | int register_spu_syscalls(struct spufs_calls *calls); |
272 | void unregister_spu_syscalls(struct spufs_calls *calls); | |
67207b96 | 273 | |
8a25a2fd KS |
274 | int spu_add_dev_attr(struct device_attribute *attr); |
275 | void spu_remove_dev_attr(struct device_attribute *attr); | |
e570beb6 | 276 | |
8a25a2fd KS |
277 | int spu_add_dev_attr_group(struct attribute_group *attrs); |
278 | void spu_remove_dev_attr_group(struct attribute_group *attrs); | |
e570beb6 | 279 | |
7cd58e43 JK |
280 | int spu_handle_mm_fault(struct mm_struct *mm, unsigned long ea, |
281 | unsigned long dsisr, unsigned *flt); | |
67207b96 | 282 | |
86767277 AB |
283 | /* |
284 | * Notifier blocks: | |
285 | * | |
286 | * oprofile can get notified when a context switch is performed | |
287 | * on an spe. The notifer function that gets called is passed | |
288 | * a pointer to the SPU structure as well as the object-id that | |
289 | * identifies the binary running on that SPU now. | |
290 | * | |
291 | * For a context save, the object-id that is passed is zero, | |
292 | * identifying that the kernel will run from that moment on. | |
293 | * | |
294 | * For a context restore, the object-id is the value written | |
295 | * to object-id spufs file from user space and the notifer | |
296 | * function can assume that spu->ctx is valid. | |
297 | */ | |
f1fa16e8 | 298 | struct notifier_block; |
86767277 AB |
299 | int spu_switch_event_register(struct notifier_block * n); |
300 | int spu_switch_event_unregister(struct notifier_block * n); | |
301 | ||
aed3a8c9 BN |
302 | extern void notify_spus_active(void); |
303 | extern void do_notify_spus_active(void); | |
304 | ||
67207b96 | 305 | /* |
567e9fdd | 306 | * This defines the Local Store, Problem Area and Privilege Area of an SPU. |
67207b96 AB |
307 | */ |
308 | ||
309 | union mfc_tag_size_class_cmd { | |
310 | struct { | |
311 | u16 mfc_size; | |
312 | u16 mfc_tag; | |
313 | u8 pad; | |
314 | u8 mfc_rclassid; | |
315 | u16 mfc_cmd; | |
316 | } u; | |
317 | struct { | |
318 | u32 mfc_size_tag32; | |
319 | u32 mfc_class_cmd32; | |
320 | } by32; | |
321 | u64 all64; | |
322 | }; | |
323 | ||
324 | struct mfc_cq_sr { | |
325 | u64 mfc_cq_data0_RW; | |
326 | u64 mfc_cq_data1_RW; | |
327 | u64 mfc_cq_data2_RW; | |
328 | u64 mfc_cq_data3_RW; | |
329 | }; | |
330 | ||
331 | struct spu_problem { | |
332 | #define MS_SYNC_PENDING 1L | |
333 | u64 spc_mssync_RW; /* 0x0000 */ | |
334 | u8 pad_0x0008_0x3000[0x3000 - 0x0008]; | |
335 | ||
336 | /* DMA Area */ | |
337 | u8 pad_0x3000_0x3004[0x4]; /* 0x3000 */ | |
338 | u32 mfc_lsa_W; /* 0x3004 */ | |
339 | u64 mfc_ea_W; /* 0x3008 */ | |
340 | union mfc_tag_size_class_cmd mfc_union_W; /* 0x3010 */ | |
341 | u8 pad_0x3018_0x3104[0xec]; /* 0x3018 */ | |
342 | u32 dma_qstatus_R; /* 0x3104 */ | |
343 | u8 pad_0x3108_0x3204[0xfc]; /* 0x3108 */ | |
344 | u32 dma_querytype_RW; /* 0x3204 */ | |
345 | u8 pad_0x3208_0x321c[0x14]; /* 0x3208 */ | |
346 | u32 dma_querymask_RW; /* 0x321c */ | |
347 | u8 pad_0x3220_0x322c[0xc]; /* 0x3220 */ | |
348 | u32 dma_tagstatus_R; /* 0x322c */ | |
349 | #define DMA_TAGSTATUS_INTR_ANY 1u | |
350 | #define DMA_TAGSTATUS_INTR_ALL 2u | |
351 | u8 pad_0x3230_0x4000[0x4000 - 0x3230]; /* 0x3230 */ | |
352 | ||
353 | /* SPU Control Area */ | |
354 | u8 pad_0x4000_0x4004[0x4]; /* 0x4000 */ | |
355 | u32 pu_mb_R; /* 0x4004 */ | |
356 | u8 pad_0x4008_0x400c[0x4]; /* 0x4008 */ | |
357 | u32 spu_mb_W; /* 0x400c */ | |
358 | u8 pad_0x4010_0x4014[0x4]; /* 0x4010 */ | |
359 | u32 mb_stat_R; /* 0x4014 */ | |
360 | u8 pad_0x4018_0x401c[0x4]; /* 0x4018 */ | |
361 | u32 spu_runcntl_RW; /* 0x401c */ | |
362 | #define SPU_RUNCNTL_STOP 0L | |
363 | #define SPU_RUNCNTL_RUNNABLE 1L | |
5737edd1 | 364 | #define SPU_RUNCNTL_ISOLATE 2L |
67207b96 AB |
365 | u8 pad_0x4020_0x4024[0x4]; /* 0x4020 */ |
366 | u32 spu_status_R; /* 0x4024 */ | |
367 | #define SPU_STOP_STATUS_SHIFT 16 | |
368 | #define SPU_STATUS_STOPPED 0x0 | |
369 | #define SPU_STATUS_RUNNING 0x1 | |
370 | #define SPU_STATUS_STOPPED_BY_STOP 0x2 | |
371 | #define SPU_STATUS_STOPPED_BY_HALT 0x4 | |
372 | #define SPU_STATUS_WAITING_FOR_CHANNEL 0x8 | |
373 | #define SPU_STATUS_SINGLE_STEP 0x10 | |
374 | #define SPU_STATUS_INVALID_INSTR 0x20 | |
375 | #define SPU_STATUS_INVALID_CH 0x40 | |
376 | #define SPU_STATUS_ISOLATED_STATE 0x80 | |
eb758ce5 | 377 | #define SPU_STATUS_ISOLATED_LOAD_STATUS 0x200 |
378 | #define SPU_STATUS_ISOLATED_EXIT_STATUS 0x400 | |
67207b96 AB |
379 | u8 pad_0x4028_0x402c[0x4]; /* 0x4028 */ |
380 | u32 spu_spe_R; /* 0x402c */ | |
381 | u8 pad_0x4030_0x4034[0x4]; /* 0x4030 */ | |
382 | u32 spu_npc_RW; /* 0x4034 */ | |
383 | u8 pad_0x4038_0x14000[0x14000 - 0x4038]; /* 0x4038 */ | |
384 | ||
385 | /* Signal Notification Area */ | |
386 | u8 pad_0x14000_0x1400c[0xc]; /* 0x14000 */ | |
387 | u32 signal_notify1; /* 0x1400c */ | |
388 | u8 pad_0x14010_0x1c00c[0x7ffc]; /* 0x14010 */ | |
389 | u32 signal_notify2; /* 0x1c00c */ | |
390 | } __attribute__ ((aligned(0x20000))); | |
391 | ||
392 | /* SPU Privilege 2 State Area */ | |
393 | struct spu_priv2 { | |
394 | /* MFC Registers */ | |
395 | u8 pad_0x0000_0x1100[0x1100 - 0x0000]; /* 0x0000 */ | |
396 | ||
397 | /* SLB Management Registers */ | |
398 | u8 pad_0x1100_0x1108[0x8]; /* 0x1100 */ | |
399 | u64 slb_index_W; /* 0x1108 */ | |
400 | #define SLB_INDEX_MASK 0x7L | |
401 | u64 slb_esid_RW; /* 0x1110 */ | |
402 | u64 slb_vsid_RW; /* 0x1118 */ | |
403 | #define SLB_VSID_SUPERVISOR_STATE (0x1ull << 11) | |
404 | #define SLB_VSID_SUPERVISOR_STATE_MASK (0x1ull << 11) | |
405 | #define SLB_VSID_PROBLEM_STATE (0x1ull << 10) | |
406 | #define SLB_VSID_PROBLEM_STATE_MASK (0x1ull << 10) | |
407 | #define SLB_VSID_EXECUTE_SEGMENT (0x1ull << 9) | |
408 | #define SLB_VSID_NO_EXECUTE_SEGMENT (0x1ull << 9) | |
409 | #define SLB_VSID_EXECUTE_SEGMENT_MASK (0x1ull << 9) | |
410 | #define SLB_VSID_4K_PAGE (0x0 << 8) | |
411 | #define SLB_VSID_LARGE_PAGE (0x1ull << 8) | |
412 | #define SLB_VSID_PAGE_SIZE_MASK (0x1ull << 8) | |
413 | #define SLB_VSID_CLASS_MASK (0x1ull << 7) | |
414 | #define SLB_VSID_VIRTUAL_PAGE_SIZE_MASK (0x1ull << 6) | |
415 | u64 slb_invalidate_entry_W; /* 0x1120 */ | |
416 | u64 slb_invalidate_all_W; /* 0x1128 */ | |
417 | u8 pad_0x1130_0x2000[0x2000 - 0x1130]; /* 0x1130 */ | |
418 | ||
419 | /* Context Save / Restore Area */ | |
420 | struct mfc_cq_sr spuq[16]; /* 0x2000 */ | |
421 | struct mfc_cq_sr puq[8]; /* 0x2200 */ | |
422 | u8 pad_0x2300_0x3000[0x3000 - 0x2300]; /* 0x2300 */ | |
423 | ||
424 | /* MFC Control */ | |
425 | u64 mfc_control_RW; /* 0x3000 */ | |
426 | #define MFC_CNTL_RESUME_DMA_QUEUE (0ull << 0) | |
427 | #define MFC_CNTL_SUSPEND_DMA_QUEUE (1ull << 0) | |
428 | #define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK (1ull << 0) | |
49776d30 | 429 | #define MFC_CNTL_SUSPEND_MASK (1ull << 4) |
67207b96 AB |
430 | #define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION (0ull << 8) |
431 | #define MFC_CNTL_SUSPEND_IN_PROGRESS (1ull << 8) | |
432 | #define MFC_CNTL_SUSPEND_COMPLETE (3ull << 8) | |
433 | #define MFC_CNTL_SUSPEND_DMA_STATUS_MASK (3ull << 8) | |
434 | #define MFC_CNTL_DMA_QUEUES_EMPTY (1ull << 14) | |
435 | #define MFC_CNTL_DMA_QUEUES_EMPTY_MASK (1ull << 14) | |
436 | #define MFC_CNTL_PURGE_DMA_REQUEST (1ull << 15) | |
437 | #define MFC_CNTL_PURGE_DMA_IN_PROGRESS (1ull << 24) | |
438 | #define MFC_CNTL_PURGE_DMA_COMPLETE (3ull << 24) | |
439 | #define MFC_CNTL_PURGE_DMA_STATUS_MASK (3ull << 24) | |
440 | #define MFC_CNTL_RESTART_DMA_COMMAND (1ull << 32) | |
441 | #define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING (1ull << 32) | |
442 | #define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32) | |
443 | #define MFC_CNTL_MFC_PRIVILEGE_STATE (2ull << 33) | |
444 | #define MFC_CNTL_MFC_PROBLEM_STATE (3ull << 33) | |
445 | #define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK (3ull << 33) | |
446 | #define MFC_CNTL_DECREMENTER_HALTED (1ull << 35) | |
447 | #define MFC_CNTL_DECREMENTER_RUNNING (1ull << 40) | |
448 | #define MFC_CNTL_DECREMENTER_STATUS_MASK (1ull << 40) | |
449 | u8 pad_0x3008_0x4000[0x4000 - 0x3008]; /* 0x3008 */ | |
450 | ||
451 | /* Interrupt Mailbox */ | |
452 | u64 puint_mb_R; /* 0x4000 */ | |
453 | u8 pad_0x4008_0x4040[0x4040 - 0x4008]; /* 0x4008 */ | |
454 | ||
455 | /* SPU Control */ | |
456 | u64 spu_privcntl_RW; /* 0x4040 */ | |
457 | #define SPU_PRIVCNTL_MODE_NORMAL (0x0ull << 0) | |
458 | #define SPU_PRIVCNTL_MODE_SINGLE_STEP (0x1ull << 0) | |
459 | #define SPU_PRIVCNTL_MODE_MASK (0x1ull << 0) | |
460 | #define SPU_PRIVCNTL_NO_ATTENTION_EVENT (0x0ull << 1) | |
461 | #define SPU_PRIVCNTL_ATTENTION_EVENT (0x1ull << 1) | |
462 | #define SPU_PRIVCNTL_ATTENTION_EVENT_MASK (0x1ull << 1) | |
463 | #define SPU_PRIVCNT_LOAD_REQUEST_NORMAL (0x0ull << 2) | |
464 | #define SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK (0x1ull << 2) | |
465 | u8 pad_0x4048_0x4058[0x10]; /* 0x4048 */ | |
466 | u64 spu_lslr_RW; /* 0x4058 */ | |
467 | u64 spu_chnlcntptr_RW; /* 0x4060 */ | |
468 | u64 spu_chnlcnt_RW; /* 0x4068 */ | |
469 | u64 spu_chnldata_RW; /* 0x4070 */ | |
470 | u64 spu_cfg_RW; /* 0x4078 */ | |
471 | u8 pad_0x4080_0x5000[0x5000 - 0x4080]; /* 0x4080 */ | |
472 | ||
473 | /* PV2_ImplRegs: Implementation-specific privileged-state 2 regs */ | |
474 | u64 spu_pm_trace_tag_status_RW; /* 0x5000 */ | |
475 | u64 spu_tag_status_query_RW; /* 0x5008 */ | |
476 | #define TAG_STATUS_QUERY_CONDITION_BITS (0x3ull << 32) | |
477 | #define TAG_STATUS_QUERY_MASK_BITS (0xffffffffull) | |
478 | u64 spu_cmd_buf1_RW; /* 0x5010 */ | |
479 | #define SPU_COMMAND_BUFFER_1_LSA_BITS (0x7ffffull << 32) | |
480 | #define SPU_COMMAND_BUFFER_1_EAH_BITS (0xffffffffull) | |
481 | u64 spu_cmd_buf2_RW; /* 0x5018 */ | |
482 | #define SPU_COMMAND_BUFFER_2_EAL_BITS ((0xffffffffull) << 32) | |
483 | #define SPU_COMMAND_BUFFER_2_TS_BITS (0xffffull << 16) | |
484 | #define SPU_COMMAND_BUFFER_2_TAG_BITS (0x3full) | |
485 | u64 spu_atomic_status_RW; /* 0x5020 */ | |
486 | } __attribute__ ((aligned(0x20000))); | |
487 | ||
488 | /* SPU Privilege 1 State Area */ | |
489 | struct spu_priv1 { | |
490 | /* Control and Configuration Area */ | |
491 | u64 mfc_sr1_RW; /* 0x000 */ | |
492 | #define MFC_STATE1_LOCAL_STORAGE_DECODE_MASK 0x01ull | |
493 | #define MFC_STATE1_BUS_TLBIE_MASK 0x02ull | |
494 | #define MFC_STATE1_REAL_MODE_OFFSET_ENABLE_MASK 0x04ull | |
495 | #define MFC_STATE1_PROBLEM_STATE_MASK 0x08ull | |
496 | #define MFC_STATE1_RELOCATE_MASK 0x10ull | |
497 | #define MFC_STATE1_MASTER_RUN_CONTROL_MASK 0x20ull | |
be703177 | 498 | #define MFC_STATE1_TABLE_SEARCH_MASK 0x40ull |
67207b96 AB |
499 | u64 mfc_lpid_RW; /* 0x008 */ |
500 | u64 spu_idr_RW; /* 0x010 */ | |
501 | u64 mfc_vr_RO; /* 0x018 */ | |
502 | #define MFC_VERSION_BITS (0xffff << 16) | |
503 | #define MFC_REVISION_BITS (0xffff) | |
504 | #define MFC_GET_VERSION_BITS(vr) (((vr) & MFC_VERSION_BITS) >> 16) | |
505 | #define MFC_GET_REVISION_BITS(vr) ((vr) & MFC_REVISION_BITS) | |
506 | u64 spu_vr_RO; /* 0x020 */ | |
507 | #define SPU_VERSION_BITS (0xffff << 16) | |
508 | #define SPU_REVISION_BITS (0xffff) | |
509 | #define SPU_GET_VERSION_BITS(vr) (vr & SPU_VERSION_BITS) >> 16 | |
510 | #define SPU_GET_REVISION_BITS(vr) (vr & SPU_REVISION_BITS) | |
511 | u8 pad_0x28_0x100[0x100 - 0x28]; /* 0x28 */ | |
512 | ||
67207b96 | 513 | /* Interrupt Area */ |
f0831acc | 514 | u64 int_mask_RW[3]; /* 0x100 */ |
67207b96 AB |
515 | #define CLASS0_ENABLE_DMA_ALIGNMENT_INTR 0x1L |
516 | #define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR 0x2L | |
517 | #define CLASS0_ENABLE_SPU_ERROR_INTR 0x4L | |
518 | #define CLASS0_ENABLE_MFC_FIR_INTR 0x8L | |
67207b96 AB |
519 | #define CLASS1_ENABLE_SEGMENT_FAULT_INTR 0x1L |
520 | #define CLASS1_ENABLE_STORAGE_FAULT_INTR 0x2L | |
521 | #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L | |
522 | #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L | |
67207b96 AB |
523 | #define CLASS2_ENABLE_MAILBOX_INTR 0x1L |
524 | #define CLASS2_ENABLE_SPU_STOP_INTR 0x2L | |
525 | #define CLASS2_ENABLE_SPU_HALT_INTR 0x4L | |
526 | #define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L | |
8af30675 | 527 | #define CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR 0x10L |
67207b96 | 528 | u8 pad_0x118_0x140[0x28]; /* 0x118 */ |
f0831acc | 529 | u64 int_stat_RW[3]; /* 0x140 */ |
8af30675 JK |
530 | #define CLASS0_DMA_ALIGNMENT_INTR 0x1L |
531 | #define CLASS0_INVALID_DMA_COMMAND_INTR 0x2L | |
532 | #define CLASS0_SPU_ERROR_INTR 0x4L | |
533 | #define CLASS0_INTR_MASK 0x7L | |
534 | #define CLASS1_SEGMENT_FAULT_INTR 0x1L | |
535 | #define CLASS1_STORAGE_FAULT_INTR 0x2L | |
536 | #define CLASS1_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L | |
537 | #define CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L | |
9476141c | 538 | #define CLASS1_INTR_MASK 0xfL |
8af30675 JK |
539 | #define CLASS2_MAILBOX_INTR 0x1L |
540 | #define CLASS2_SPU_STOP_INTR 0x2L | |
541 | #define CLASS2_SPU_HALT_INTR 0x4L | |
542 | #define CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L | |
543 | #define CLASS2_MAILBOX_THRESHOLD_INTR 0x10L | |
9476141c | 544 | #define CLASS2_INTR_MASK 0x1fL |
67207b96 AB |
545 | u8 pad_0x158_0x180[0x28]; /* 0x158 */ |
546 | u64 int_route_RW; /* 0x180 */ | |
547 | ||
548 | /* Interrupt Routing */ | |
549 | u8 pad_0x188_0x200[0x200 - 0x188]; /* 0x188 */ | |
550 | ||
551 | /* Atomic Unit Control Area */ | |
552 | u64 mfc_atomic_flush_RW; /* 0x200 */ | |
553 | #define mfc_atomic_flush_enable 0x1L | |
554 | u8 pad_0x208_0x280[0x78]; /* 0x208 */ | |
555 | u64 resource_allocation_groupID_RW; /* 0x280 */ | |
556 | u64 resource_allocation_enable_RW; /* 0x288 */ | |
557 | u8 pad_0x290_0x3c8[0x3c8 - 0x290]; /* 0x290 */ | |
558 | ||
559 | /* SPU_Cache_ImplRegs: Implementation-dependent cache registers */ | |
560 | ||
561 | u64 smf_sbi_signal_sel; /* 0x3c8 */ | |
562 | #define smf_sbi_mask_lsb 56 | |
563 | #define smf_sbi_shift (63 - smf_sbi_mask_lsb) | |
564 | #define smf_sbi_mask (0x301LL << smf_sbi_shift) | |
565 | #define smf_sbi_bus0_bits (0x001LL << smf_sbi_shift) | |
566 | #define smf_sbi_bus2_bits (0x100LL << smf_sbi_shift) | |
567 | #define smf_sbi2_bus0_bits (0x201LL << smf_sbi_shift) | |
568 | #define smf_sbi2_bus2_bits (0x300LL << smf_sbi_shift) | |
569 | u64 smf_ato_signal_sel; /* 0x3d0 */ | |
570 | #define smf_ato_mask_lsb 35 | |
571 | #define smf_ato_shift (63 - smf_ato_mask_lsb) | |
572 | #define smf_ato_mask (0x3LL << smf_ato_shift) | |
573 | #define smf_ato_bus0_bits (0x2LL << smf_ato_shift) | |
574 | #define smf_ato_bus2_bits (0x1LL << smf_ato_shift) | |
575 | u8 pad_0x3d8_0x400[0x400 - 0x3d8]; /* 0x3d8 */ | |
576 | ||
577 | /* TLB Management Registers */ | |
578 | u64 mfc_sdr_RW; /* 0x400 */ | |
579 | u8 pad_0x408_0x500[0xf8]; /* 0x408 */ | |
580 | u64 tlb_index_hint_RO; /* 0x500 */ | |
581 | u64 tlb_index_W; /* 0x508 */ | |
582 | u64 tlb_vpn_RW; /* 0x510 */ | |
583 | u64 tlb_rpn_RW; /* 0x518 */ | |
584 | u8 pad_0x520_0x540[0x20]; /* 0x520 */ | |
585 | u64 tlb_invalidate_entry_W; /* 0x540 */ | |
586 | u64 tlb_invalidate_all_W; /* 0x548 */ | |
587 | u8 pad_0x550_0x580[0x580 - 0x550]; /* 0x550 */ | |
588 | ||
589 | /* SPU_MMU_ImplRegs: Implementation-dependent MMU registers */ | |
590 | u64 smm_hid; /* 0x580 */ | |
591 | #define PAGE_SIZE_MASK 0xf000000000000000ull | |
592 | #define PAGE_SIZE_16MB_64KB 0x2000000000000000ull | |
593 | u8 pad_0x588_0x600[0x600 - 0x588]; /* 0x588 */ | |
594 | ||
595 | /* MFC Status/Control Area */ | |
596 | u64 mfc_accr_RW; /* 0x600 */ | |
597 | #define MFC_ACCR_EA_ACCESS_GET (1 << 0) | |
598 | #define MFC_ACCR_EA_ACCESS_PUT (1 << 1) | |
599 | #define MFC_ACCR_LS_ACCESS_GET (1 << 3) | |
600 | #define MFC_ACCR_LS_ACCESS_PUT (1 << 4) | |
601 | u8 pad_0x608_0x610[0x8]; /* 0x608 */ | |
602 | u64 mfc_dsisr_RW; /* 0x610 */ | |
603 | #define MFC_DSISR_PTE_NOT_FOUND (1 << 30) | |
604 | #define MFC_DSISR_ACCESS_DENIED (1 << 27) | |
605 | #define MFC_DSISR_ATOMIC (1 << 26) | |
606 | #define MFC_DSISR_ACCESS_PUT (1 << 25) | |
607 | #define MFC_DSISR_ADDR_MATCH (1 << 22) | |
608 | #define MFC_DSISR_LS (1 << 17) | |
609 | #define MFC_DSISR_L (1 << 16) | |
610 | #define MFC_DSISR_ADDRESS_OVERFLOW (1 << 0) | |
611 | u8 pad_0x618_0x620[0x8]; /* 0x618 */ | |
612 | u64 mfc_dar_RW; /* 0x620 */ | |
613 | u8 pad_0x628_0x700[0x700 - 0x628]; /* 0x628 */ | |
614 | ||
615 | /* Replacement Management Table (RMT) Area */ | |
616 | u64 rmt_index_RW; /* 0x700 */ | |
617 | u8 pad_0x708_0x710[0x8]; /* 0x708 */ | |
618 | u64 rmt_data1_RW; /* 0x710 */ | |
619 | u8 pad_0x718_0x800[0x800 - 0x718]; /* 0x718 */ | |
620 | ||
621 | /* Control/Configuration Registers */ | |
622 | u64 mfc_dsir_R; /* 0x800 */ | |
623 | #define MFC_DSIR_Q (1 << 31) | |
624 | #define MFC_DSIR_SPU_QUEUE MFC_DSIR_Q | |
625 | u64 mfc_lsacr_RW; /* 0x808 */ | |
626 | #define MFC_LSACR_COMPARE_MASK ((~0ull) << 32) | |
627 | #define MFC_LSACR_COMPARE_ADDR ((~0ull) >> 32) | |
628 | u64 mfc_lscrr_R; /* 0x810 */ | |
629 | #define MFC_LSCRR_Q (1 << 31) | |
630 | #define MFC_LSCRR_SPU_QUEUE MFC_LSCRR_Q | |
631 | #define MFC_LSCRR_QI_SHIFT 32 | |
632 | #define MFC_LSCRR_QI_MASK ((~0ull) << MFC_LSCRR_QI_SHIFT) | |
633 | u8 pad_0x818_0x820[0x8]; /* 0x818 */ | |
634 | u64 mfc_tclass_id_RW; /* 0x820 */ | |
635 | #define MFC_TCLASS_ID_ENABLE (1L << 0L) | |
636 | #define MFC_TCLASS_SLOT2_ENABLE (1L << 5L) | |
637 | #define MFC_TCLASS_SLOT1_ENABLE (1L << 6L) | |
638 | #define MFC_TCLASS_SLOT0_ENABLE (1L << 7L) | |
639 | #define MFC_TCLASS_QUOTA_2_SHIFT 8L | |
640 | #define MFC_TCLASS_QUOTA_1_SHIFT 16L | |
641 | #define MFC_TCLASS_QUOTA_0_SHIFT 24L | |
642 | #define MFC_TCLASS_QUOTA_2_MASK (0x1FL << MFC_TCLASS_QUOTA_2_SHIFT) | |
643 | #define MFC_TCLASS_QUOTA_1_MASK (0x1FL << MFC_TCLASS_QUOTA_1_SHIFT) | |
644 | #define MFC_TCLASS_QUOTA_0_MASK (0x1FL << MFC_TCLASS_QUOTA_0_SHIFT) | |
645 | u8 pad_0x828_0x900[0x900 - 0x828]; /* 0x828 */ | |
646 | ||
647 | /* Real Mode Support Registers */ | |
648 | u64 mfc_rm_boundary; /* 0x900 */ | |
649 | u8 pad_0x908_0x938[0x30]; /* 0x908 */ | |
650 | u64 smf_dma_signal_sel; /* 0x938 */ | |
651 | #define mfc_dma1_mask_lsb 41 | |
652 | #define mfc_dma1_shift (63 - mfc_dma1_mask_lsb) | |
653 | #define mfc_dma1_mask (0x3LL << mfc_dma1_shift) | |
654 | #define mfc_dma1_bits (0x1LL << mfc_dma1_shift) | |
655 | #define mfc_dma2_mask_lsb 43 | |
656 | #define mfc_dma2_shift (63 - mfc_dma2_mask_lsb) | |
657 | #define mfc_dma2_mask (0x3LL << mfc_dma2_shift) | |
658 | #define mfc_dma2_bits (0x1LL << mfc_dma2_shift) | |
659 | u8 pad_0x940_0xa38[0xf8]; /* 0x940 */ | |
660 | u64 smm_signal_sel; /* 0xa38 */ | |
661 | #define smm_sig_mask_lsb 12 | |
662 | #define smm_sig_shift (63 - smm_sig_mask_lsb) | |
663 | #define smm_sig_mask (0x3LL << smm_sig_shift) | |
664 | #define smm_sig_bus0_bits (0x2LL << smm_sig_shift) | |
665 | #define smm_sig_bus2_bits (0x1LL << smm_sig_shift) | |
666 | u8 pad_0xa40_0xc00[0xc00 - 0xa40]; /* 0xa40 */ | |
667 | ||
668 | /* DMA Command Error Area */ | |
669 | u64 mfc_cer_R; /* 0xc00 */ | |
670 | #define MFC_CER_Q (1 << 31) | |
671 | #define MFC_CER_SPU_QUEUE MFC_CER_Q | |
672 | u8 pad_0xc08_0x1000[0x1000 - 0xc08]; /* 0xc08 */ | |
673 | ||
674 | /* PV1_ImplRegs: Implementation-dependent privileged-state 1 regs */ | |
675 | /* DMA Command Error Area */ | |
676 | u64 spu_ecc_cntl_RW; /* 0x1000 */ | |
677 | #define SPU_ECC_CNTL_E (1ull << 0ull) | |
678 | #define SPU_ECC_CNTL_ENABLE SPU_ECC_CNTL_E | |
679 | #define SPU_ECC_CNTL_DISABLE (~SPU_ECC_CNTL_E & 1L) | |
680 | #define SPU_ECC_CNTL_S (1ull << 1ull) | |
681 | #define SPU_ECC_STOP_AFTER_ERROR SPU_ECC_CNTL_S | |
682 | #define SPU_ECC_CONTINUE_AFTER_ERROR (~SPU_ECC_CNTL_S & 2L) | |
683 | #define SPU_ECC_CNTL_B (1ull << 2ull) | |
684 | #define SPU_ECC_BACKGROUND_ENABLE SPU_ECC_CNTL_B | |
685 | #define SPU_ECC_BACKGROUND_DISABLE (~SPU_ECC_CNTL_B & 4L) | |
686 | #define SPU_ECC_CNTL_I_SHIFT 3ull | |
687 | #define SPU_ECC_CNTL_I_MASK (3ull << SPU_ECC_CNTL_I_SHIFT) | |
688 | #define SPU_ECC_WRITE_ALWAYS (~SPU_ECC_CNTL_I & 12L) | |
689 | #define SPU_ECC_WRITE_CORRECTABLE (1ull << SPU_ECC_CNTL_I_SHIFT) | |
690 | #define SPU_ECC_WRITE_UNCORRECTABLE (3ull << SPU_ECC_CNTL_I_SHIFT) | |
691 | #define SPU_ECC_CNTL_D (1ull << 5ull) | |
692 | #define SPU_ECC_DETECTION_ENABLE SPU_ECC_CNTL_D | |
693 | #define SPU_ECC_DETECTION_DISABLE (~SPU_ECC_CNTL_D & 32L) | |
694 | u64 spu_ecc_stat_RW; /* 0x1008 */ | |
695 | #define SPU_ECC_CORRECTED_ERROR (1ull << 0ul) | |
696 | #define SPU_ECC_UNCORRECTED_ERROR (1ull << 1ul) | |
697 | #define SPU_ECC_SCRUB_COMPLETE (1ull << 2ul) | |
698 | #define SPU_ECC_SCRUB_IN_PROGRESS (1ull << 3ul) | |
699 | #define SPU_ECC_INSTRUCTION_ERROR (1ull << 4ul) | |
700 | #define SPU_ECC_DATA_ERROR (1ull << 5ul) | |
701 | #define SPU_ECC_DMA_ERROR (1ull << 6ul) | |
702 | #define SPU_ECC_STATUS_CNT_MASK (256ull << 8) | |
703 | u64 spu_ecc_addr_RW; /* 0x1010 */ | |
704 | u64 spu_err_mask_RW; /* 0x1018 */ | |
705 | #define SPU_ERR_ILLEGAL_INSTR (1ull << 0ul) | |
706 | #define SPU_ERR_ILLEGAL_CHANNEL (1ull << 1ul) | |
707 | u8 pad_0x1020_0x1028[0x1028 - 0x1020]; /* 0x1020 */ | |
708 | ||
709 | /* SPU Debug-Trace Bus (DTB) Selection Registers */ | |
710 | u64 spu_trig0_sel; /* 0x1028 */ | |
711 | u64 spu_trig1_sel; /* 0x1030 */ | |
712 | u64 spu_trig2_sel; /* 0x1038 */ | |
713 | u64 spu_trig3_sel; /* 0x1040 */ | |
714 | u64 spu_trace_sel; /* 0x1048 */ | |
715 | #define spu_trace_sel_mask 0x1f1fLL | |
716 | #define spu_trace_sel_bus0_bits 0x1000LL | |
717 | #define spu_trace_sel_bus2_bits 0x0010LL | |
718 | u64 spu_event0_sel; /* 0x1050 */ | |
719 | u64 spu_event1_sel; /* 0x1058 */ | |
720 | u64 spu_event2_sel; /* 0x1060 */ | |
721 | u64 spu_event3_sel; /* 0x1068 */ | |
722 | u64 spu_trace_cntl; /* 0x1070 */ | |
723 | } __attribute__ ((aligned(0x2000))); | |
724 | ||
88ced031 | 725 | #endif /* __KERNEL__ */ |
67207b96 | 726 | #endif |