Commit | Line | Data |
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14cf11af PM |
1 | /* |
2 | * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> | |
3 | */ | |
bbeb3f4c SR |
4 | #ifndef _ASM_POWERPC_SYSTEM_H |
5 | #define _ASM_POWERPC_SYSTEM_H | |
14cf11af | 6 | |
14cf11af | 7 | #include <linux/kernel.h> |
14b3ca40 | 8 | #include <linux/irqflags.h> |
14cf11af PM |
9 | |
10 | #include <asm/hw_irq.h> | |
14cf11af PM |
11 | |
12 | /* | |
13 | * Memory barrier. | |
14 | * The sync instruction guarantees that all memory accesses initiated | |
15 | * by this processor have been performed (with respect to all other | |
16 | * mechanisms that access memory). The eieio instruction is a barrier | |
17 | * providing an ordering (separately) for (a) cacheable stores and (b) | |
18 | * loads and stores to non-cacheable memory (e.g. I/O devices). | |
19 | * | |
20 | * mb() prevents loads and stores being reordered across this point. | |
21 | * rmb() prevents loads being reordered across this point. | |
22 | * wmb() prevents stores being reordered across this point. | |
23 | * read_barrier_depends() prevents data-dependent loads being reordered | |
24 | * across this point (nop on PPC). | |
25 | * | |
957ab07b NP |
26 | * *mb() variants without smp_ prefix must order all types of memory |
27 | * operations with one another. sync is the only instruction sufficient | |
28 | * to do this. | |
14cf11af | 29 | * |
957ab07b NP |
30 | * For the smp_ barriers, ordering is for cacheable memory operations |
31 | * only. We have to use the sync instruction for smp_mb(), since lwsync | |
32 | * doesn't order loads with respect to previous stores. Lwsync can be | |
33 | * used for smp_rmb() and smp_wmb(). | |
34 | * | |
35 | * However, on CPUs that don't support lwsync, lwsync actually maps to a | |
36 | * heavy-weight sync, so smp_wmb() can be a lighter-weight eieio. | |
14cf11af PM |
37 | */ |
38 | #define mb() __asm__ __volatile__ ("sync" : : : "memory") | |
598056d5 | 39 | #define rmb() __asm__ __volatile__ ("sync" : : : "memory") |
14cf11af PM |
40 | #define wmb() __asm__ __volatile__ ("sync" : : : "memory") |
41 | #define read_barrier_depends() do { } while(0) | |
42 | ||
43 | #define set_mb(var, value) do { var = value; mb(); } while (0) | |
14cf11af | 44 | |
88ced031 | 45 | #ifdef __KERNEL__ |
4f9a58d7 | 46 | #define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */ |
14cf11af | 47 | #ifdef CONFIG_SMP |
74f06095 NP |
48 | |
49 | #ifdef __SUBARCH_HAS_LWSYNC | |
46d075be | 50 | # define SMPWMB LWSYNC |
74f06095 NP |
51 | #else |
52 | # define SMPWMB eieio | |
53 | #endif | |
54 | ||
14cf11af | 55 | #define smp_mb() mb() |
957ab07b | 56 | #define smp_rmb() __asm__ __volatile__ (stringify_in_c(LWSYNC) : : :"memory") |
46d075be | 57 | #define smp_wmb() __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory") |
14cf11af PM |
58 | #define smp_read_barrier_depends() read_barrier_depends() |
59 | #else | |
60 | #define smp_mb() barrier() | |
61 | #define smp_rmb() barrier() | |
62 | #define smp_wmb() barrier() | |
63 | #define smp_read_barrier_depends() do { } while(0) | |
64 | #endif /* CONFIG_SMP */ | |
65 | ||
5db9fa95 NL |
66 | /* |
67 | * This is a barrier which prevents following instructions from being | |
68 | * started until the value of the argument x is known. For example, if | |
69 | * x is a variable loaded from memory, this prevents following | |
70 | * instructions from being executed until the load has been performed. | |
71 | */ | |
72 | #define data_barrier(x) \ | |
73 | asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory"); | |
74 | ||
14cf11af PM |
75 | struct task_struct; |
76 | struct pt_regs; | |
77 | ||
7dbb922c | 78 | #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) |
14cf11af PM |
79 | |
80 | extern int (*__debugger)(struct pt_regs *regs); | |
81 | extern int (*__debugger_ipi)(struct pt_regs *regs); | |
82 | extern int (*__debugger_bpt)(struct pt_regs *regs); | |
83 | extern int (*__debugger_sstep)(struct pt_regs *regs); | |
84 | extern int (*__debugger_iabr_match)(struct pt_regs *regs); | |
85 | extern int (*__debugger_dabr_match)(struct pt_regs *regs); | |
86 | extern int (*__debugger_fault_handler)(struct pt_regs *regs); | |
87 | ||
88 | #define DEBUGGER_BOILERPLATE(__NAME) \ | |
89 | static inline int __NAME(struct pt_regs *regs) \ | |
90 | { \ | |
91 | if (unlikely(__ ## __NAME)) \ | |
92 | return __ ## __NAME(regs); \ | |
93 | return 0; \ | |
94 | } | |
95 | ||
96 | DEBUGGER_BOILERPLATE(debugger) | |
97 | DEBUGGER_BOILERPLATE(debugger_ipi) | |
98 | DEBUGGER_BOILERPLATE(debugger_bpt) | |
99 | DEBUGGER_BOILERPLATE(debugger_sstep) | |
100 | DEBUGGER_BOILERPLATE(debugger_iabr_match) | |
101 | DEBUGGER_BOILERPLATE(debugger_dabr_match) | |
102 | DEBUGGER_BOILERPLATE(debugger_fault_handler) | |
103 | ||
14cf11af PM |
104 | #else |
105 | static inline int debugger(struct pt_regs *regs) { return 0; } | |
106 | static inline int debugger_ipi(struct pt_regs *regs) { return 0; } | |
107 | static inline int debugger_bpt(struct pt_regs *regs) { return 0; } | |
108 | static inline int debugger_sstep(struct pt_regs *regs) { return 0; } | |
109 | static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; } | |
110 | static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; } | |
111 | static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; } | |
112 | #endif | |
113 | ||
114 | extern int set_dabr(unsigned long dabr); | |
d6a61bfc LM |
115 | extern void do_dabr(struct pt_regs *regs, unsigned long address, |
116 | unsigned long error_code); | |
14cf11af PM |
117 | extern void print_backtrace(unsigned long *); |
118 | extern void show_regs(struct pt_regs * regs); | |
119 | extern void flush_instruction_cache(void); | |
120 | extern void hard_reset_now(void); | |
121 | extern void poweroff_now(void); | |
122 | ||
123 | #ifdef CONFIG_6xx | |
124 | extern long _get_L2CR(void); | |
125 | extern long _get_L3CR(void); | |
126 | extern void _set_L2CR(unsigned long); | |
127 | extern void _set_L3CR(unsigned long); | |
128 | #else | |
129 | #define _get_L2CR() 0L | |
130 | #define _get_L3CR() 0L | |
131 | #define _set_L2CR(val) do { } while(0) | |
132 | #define _set_L3CR(val) do { } while(0) | |
133 | #endif | |
134 | ||
135 | extern void via_cuda_init(void); | |
14cf11af PM |
136 | extern void read_rtc_time(void); |
137 | extern void pmac_find_display(void); | |
138 | extern void giveup_fpu(struct task_struct *); | |
cabb5587 | 139 | extern void disable_kernel_fp(void); |
14cf11af PM |
140 | extern void enable_kernel_fp(void); |
141 | extern void flush_fp_to_thread(struct task_struct *); | |
142 | extern void enable_kernel_altivec(void); | |
143 | extern void giveup_altivec(struct task_struct *); | |
144 | extern void load_up_altivec(struct task_struct *); | |
40ef8cbc | 145 | extern int emulate_altivec(struct pt_regs *); |
7c292170 | 146 | extern void __giveup_vsx(struct task_struct *); |
ce48b210 | 147 | extern void giveup_vsx(struct task_struct *); |
d169d140 | 148 | extern void enable_kernel_spe(void); |
14cf11af PM |
149 | extern void giveup_spe(struct task_struct *); |
150 | extern void load_up_spe(struct task_struct *); | |
151 | extern int fix_alignment(struct pt_regs *); | |
25c8a78b DG |
152 | extern void cvt_fd(float *from, double *to, struct thread_struct *thread); |
153 | extern void cvt_df(double *from, float *to, struct thread_struct *thread); | |
14cf11af | 154 | |
5388fb10 PM |
155 | #ifndef CONFIG_SMP |
156 | extern void discard_lazy_cpu_state(void); | |
157 | #else | |
158 | static inline void discard_lazy_cpu_state(void) | |
159 | { | |
160 | } | |
161 | #endif | |
162 | ||
14cf11af PM |
163 | #ifdef CONFIG_ALTIVEC |
164 | extern void flush_altivec_to_thread(struct task_struct *); | |
165 | #else | |
166 | static inline void flush_altivec_to_thread(struct task_struct *t) | |
167 | { | |
168 | } | |
169 | #endif | |
170 | ||
ce48b210 MN |
171 | #ifdef CONFIG_VSX |
172 | extern void flush_vsx_to_thread(struct task_struct *); | |
173 | #else | |
174 | static inline void flush_vsx_to_thread(struct task_struct *t) | |
175 | { | |
176 | } | |
177 | #endif | |
178 | ||
14cf11af PM |
179 | #ifdef CONFIG_SPE |
180 | extern void flush_spe_to_thread(struct task_struct *); | |
181 | #else | |
182 | static inline void flush_spe_to_thread(struct task_struct *t) | |
183 | { | |
184 | } | |
185 | #endif | |
186 | ||
187 | extern int call_rtas(const char *, int, int, unsigned long *, ...); | |
188 | extern void cacheable_memzero(void *p, unsigned int nb); | |
189 | extern void *cacheable_memcpy(void *, const void *, unsigned int); | |
190 | extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long); | |
191 | extern void bad_page_fault(struct pt_regs *, unsigned long, int); | |
192 | extern int die(const char *, struct pt_regs *, long); | |
193 | extern void _exception(int, struct pt_regs *, int, unsigned long); | |
1d59483a JL |
194 | extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); |
195 | ||
14cf11af PM |
196 | #ifdef CONFIG_BOOKE_WDT |
197 | extern u32 booke_wdt_enabled; | |
198 | extern u32 booke_wdt_period; | |
199 | #endif /* CONFIG_BOOKE_WDT */ | |
200 | ||
14cf11af PM |
201 | struct device_node; |
202 | extern void note_scsi_host(struct device_node *, void *); | |
203 | ||
204 | extern struct task_struct *__switch_to(struct task_struct *, | |
205 | struct task_struct *); | |
206 | #define switch_to(prev, next, last) ((last) = __switch_to((prev), (next))) | |
207 | ||
208 | struct thread_struct; | |
209 | extern struct task_struct *_switch(struct thread_struct *prev, | |
210 | struct thread_struct *next); | |
211 | ||
212 | extern unsigned int rtas_data; | |
40ef8cbc | 213 | extern int mem_init_done; /* set on boot once kmalloc can be called */ |
5f25f065 | 214 | extern int init_bootmem_done; /* set on !NUMA once bootmem is available */ |
cf00a8d1 | 215 | extern unsigned long memory_limit; |
49b09853 | 216 | extern unsigned long klimit; |
14cf11af | 217 | |
7b2c3c5b | 218 | extern void *alloc_maybe_bootmem(size_t size, gfp_t mask); |
5669c3cf | 219 | extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask); |
7b2c3c5b | 220 | |
17a6392d PM |
221 | extern int powersave_nap; /* set if nap mode can be used in idle loop */ |
222 | ||
14cf11af PM |
223 | /* |
224 | * Atomic exchange | |
225 | * | |
226 | * Changes the memory location '*ptr' to be val and returns | |
227 | * the previous value stored there. | |
228 | */ | |
dd18434f | 229 | static __always_inline unsigned long |
14cf11af PM |
230 | __xchg_u32(volatile void *p, unsigned long val) |
231 | { | |
232 | unsigned long prev; | |
233 | ||
234 | __asm__ __volatile__( | |
144b9c13 | 235 | LWSYNC_ON_SMP |
14cf11af PM |
236 | "1: lwarx %0,0,%2 \n" |
237 | PPC405_ERR77(0,%2) | |
238 | " stwcx. %3,0,%2 \n\ | |
239 | bne- 1b" | |
240 | ISYNC_ON_SMP | |
e2a3d402 LT |
241 | : "=&r" (prev), "+m" (*(volatile unsigned int *)p) |
242 | : "r" (p), "r" (val) | |
14cf11af PM |
243 | : "cc", "memory"); |
244 | ||
245 | return prev; | |
246 | } | |
247 | ||
f46e477e MD |
248 | /* |
249 | * Atomic exchange | |
250 | * | |
251 | * Changes the memory location '*ptr' to be val and returns | |
252 | * the previous value stored there. | |
253 | */ | |
dd18434f | 254 | static __always_inline unsigned long |
f46e477e MD |
255 | __xchg_u32_local(volatile void *p, unsigned long val) |
256 | { | |
257 | unsigned long prev; | |
258 | ||
259 | __asm__ __volatile__( | |
260 | "1: lwarx %0,0,%2 \n" | |
261 | PPC405_ERR77(0,%2) | |
262 | " stwcx. %3,0,%2 \n\ | |
263 | bne- 1b" | |
264 | : "=&r" (prev), "+m" (*(volatile unsigned int *)p) | |
265 | : "r" (p), "r" (val) | |
266 | : "cc", "memory"); | |
267 | ||
268 | return prev; | |
269 | } | |
270 | ||
14cf11af | 271 | #ifdef CONFIG_PPC64 |
dd18434f | 272 | static __always_inline unsigned long |
14cf11af PM |
273 | __xchg_u64(volatile void *p, unsigned long val) |
274 | { | |
275 | unsigned long prev; | |
276 | ||
277 | __asm__ __volatile__( | |
144b9c13 | 278 | LWSYNC_ON_SMP |
14cf11af PM |
279 | "1: ldarx %0,0,%2 \n" |
280 | PPC405_ERR77(0,%2) | |
281 | " stdcx. %3,0,%2 \n\ | |
282 | bne- 1b" | |
283 | ISYNC_ON_SMP | |
e2a3d402 LT |
284 | : "=&r" (prev), "+m" (*(volatile unsigned long *)p) |
285 | : "r" (p), "r" (val) | |
14cf11af PM |
286 | : "cc", "memory"); |
287 | ||
288 | return prev; | |
289 | } | |
f46e477e | 290 | |
dd18434f | 291 | static __always_inline unsigned long |
f46e477e MD |
292 | __xchg_u64_local(volatile void *p, unsigned long val) |
293 | { | |
294 | unsigned long prev; | |
295 | ||
296 | __asm__ __volatile__( | |
297 | "1: ldarx %0,0,%2 \n" | |
298 | PPC405_ERR77(0,%2) | |
299 | " stdcx. %3,0,%2 \n\ | |
300 | bne- 1b" | |
301 | : "=&r" (prev), "+m" (*(volatile unsigned long *)p) | |
302 | : "r" (p), "r" (val) | |
303 | : "cc", "memory"); | |
304 | ||
305 | return prev; | |
306 | } | |
14cf11af PM |
307 | #endif |
308 | ||
309 | /* | |
310 | * This function doesn't exist, so you'll get a linker error | |
311 | * if something tries to do an invalid xchg(). | |
312 | */ | |
313 | extern void __xchg_called_with_bad_pointer(void); | |
314 | ||
dd18434f | 315 | static __always_inline unsigned long |
14cf11af PM |
316 | __xchg(volatile void *ptr, unsigned long x, unsigned int size) |
317 | { | |
318 | switch (size) { | |
319 | case 4: | |
320 | return __xchg_u32(ptr, x); | |
321 | #ifdef CONFIG_PPC64 | |
322 | case 8: | |
323 | return __xchg_u64(ptr, x); | |
324 | #endif | |
325 | } | |
326 | __xchg_called_with_bad_pointer(); | |
327 | return x; | |
328 | } | |
329 | ||
dd18434f | 330 | static __always_inline unsigned long |
f46e477e MD |
331 | __xchg_local(volatile void *ptr, unsigned long x, unsigned int size) |
332 | { | |
333 | switch (size) { | |
334 | case 4: | |
335 | return __xchg_u32_local(ptr, x); | |
336 | #ifdef CONFIG_PPC64 | |
337 | case 8: | |
338 | return __xchg_u64_local(ptr, x); | |
339 | #endif | |
340 | } | |
341 | __xchg_called_with_bad_pointer(); | |
342 | return x; | |
343 | } | |
14cf11af PM |
344 | #define xchg(ptr,x) \ |
345 | ({ \ | |
346 | __typeof__(*(ptr)) _x_ = (x); \ | |
347 | (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \ | |
348 | }) | |
349 | ||
f46e477e MD |
350 | #define xchg_local(ptr,x) \ |
351 | ({ \ | |
352 | __typeof__(*(ptr)) _x_ = (x); \ | |
353 | (__typeof__(*(ptr))) __xchg_local((ptr), \ | |
354 | (unsigned long)_x_, sizeof(*(ptr))); \ | |
355 | }) | |
356 | ||
14cf11af PM |
357 | /* |
358 | * Compare and exchange - if *p == old, set it to new, | |
359 | * and return the old value of *p. | |
360 | */ | |
361 | #define __HAVE_ARCH_CMPXCHG 1 | |
362 | ||
dd18434f | 363 | static __always_inline unsigned long |
14cf11af PM |
364 | __cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new) |
365 | { | |
366 | unsigned int prev; | |
367 | ||
368 | __asm__ __volatile__ ( | |
144b9c13 | 369 | LWSYNC_ON_SMP |
14cf11af PM |
370 | "1: lwarx %0,0,%2 # __cmpxchg_u32\n\ |
371 | cmpw 0,%0,%3\n\ | |
372 | bne- 2f\n" | |
373 | PPC405_ERR77(0,%2) | |
374 | " stwcx. %4,0,%2\n\ | |
375 | bne- 1b" | |
376 | ISYNC_ON_SMP | |
377 | "\n\ | |
378 | 2:" | |
e2a3d402 LT |
379 | : "=&r" (prev), "+m" (*p) |
380 | : "r" (p), "r" (old), "r" (new) | |
14cf11af PM |
381 | : "cc", "memory"); |
382 | ||
383 | return prev; | |
384 | } | |
385 | ||
dd18434f | 386 | static __always_inline unsigned long |
f46e477e MD |
387 | __cmpxchg_u32_local(volatile unsigned int *p, unsigned long old, |
388 | unsigned long new) | |
389 | { | |
390 | unsigned int prev; | |
391 | ||
392 | __asm__ __volatile__ ( | |
393 | "1: lwarx %0,0,%2 # __cmpxchg_u32\n\ | |
394 | cmpw 0,%0,%3\n\ | |
395 | bne- 2f\n" | |
396 | PPC405_ERR77(0,%2) | |
397 | " stwcx. %4,0,%2\n\ | |
398 | bne- 1b" | |
399 | "\n\ | |
400 | 2:" | |
401 | : "=&r" (prev), "+m" (*p) | |
402 | : "r" (p), "r" (old), "r" (new) | |
403 | : "cc", "memory"); | |
404 | ||
405 | return prev; | |
406 | } | |
407 | ||
14cf11af | 408 | #ifdef CONFIG_PPC64 |
dd18434f | 409 | static __always_inline unsigned long |
3c726f8d | 410 | __cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new) |
14cf11af PM |
411 | { |
412 | unsigned long prev; | |
413 | ||
414 | __asm__ __volatile__ ( | |
144b9c13 | 415 | LWSYNC_ON_SMP |
14cf11af PM |
416 | "1: ldarx %0,0,%2 # __cmpxchg_u64\n\ |
417 | cmpd 0,%0,%3\n\ | |
418 | bne- 2f\n\ | |
419 | stdcx. %4,0,%2\n\ | |
420 | bne- 1b" | |
421 | ISYNC_ON_SMP | |
422 | "\n\ | |
423 | 2:" | |
e2a3d402 LT |
424 | : "=&r" (prev), "+m" (*p) |
425 | : "r" (p), "r" (old), "r" (new) | |
14cf11af PM |
426 | : "cc", "memory"); |
427 | ||
428 | return prev; | |
429 | } | |
f46e477e | 430 | |
dd18434f | 431 | static __always_inline unsigned long |
f46e477e MD |
432 | __cmpxchg_u64_local(volatile unsigned long *p, unsigned long old, |
433 | unsigned long new) | |
434 | { | |
435 | unsigned long prev; | |
436 | ||
437 | __asm__ __volatile__ ( | |
438 | "1: ldarx %0,0,%2 # __cmpxchg_u64\n\ | |
439 | cmpd 0,%0,%3\n\ | |
440 | bne- 2f\n\ | |
441 | stdcx. %4,0,%2\n\ | |
442 | bne- 1b" | |
443 | "\n\ | |
444 | 2:" | |
445 | : "=&r" (prev), "+m" (*p) | |
446 | : "r" (p), "r" (old), "r" (new) | |
447 | : "cc", "memory"); | |
448 | ||
449 | return prev; | |
450 | } | |
14cf11af PM |
451 | #endif |
452 | ||
453 | /* This function doesn't exist, so you'll get a linker error | |
454 | if something tries to do an invalid cmpxchg(). */ | |
455 | extern void __cmpxchg_called_with_bad_pointer(void); | |
456 | ||
dd18434f | 457 | static __always_inline unsigned long |
14cf11af PM |
458 | __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, |
459 | unsigned int size) | |
460 | { | |
461 | switch (size) { | |
462 | case 4: | |
463 | return __cmpxchg_u32(ptr, old, new); | |
464 | #ifdef CONFIG_PPC64 | |
465 | case 8: | |
466 | return __cmpxchg_u64(ptr, old, new); | |
467 | #endif | |
468 | } | |
469 | __cmpxchg_called_with_bad_pointer(); | |
470 | return old; | |
471 | } | |
472 | ||
dd18434f | 473 | static __always_inline unsigned long |
f46e477e MD |
474 | __cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long new, |
475 | unsigned int size) | |
476 | { | |
477 | switch (size) { | |
478 | case 4: | |
479 | return __cmpxchg_u32_local(ptr, old, new); | |
480 | #ifdef CONFIG_PPC64 | |
481 | case 8: | |
482 | return __cmpxchg_u64_local(ptr, old, new); | |
483 | #endif | |
484 | } | |
485 | __cmpxchg_called_with_bad_pointer(); | |
486 | return old; | |
487 | } | |
488 | ||
f9c4650b | 489 | #define cmpxchg(ptr, o, n) \ |
14cf11af PM |
490 | ({ \ |
491 | __typeof__(*(ptr)) _o_ = (o); \ | |
492 | __typeof__(*(ptr)) _n_ = (n); \ | |
493 | (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ | |
494 | (unsigned long)_n_, sizeof(*(ptr))); \ | |
495 | }) | |
496 | ||
f46e477e | 497 | |
f9c4650b | 498 | #define cmpxchg_local(ptr, o, n) \ |
f46e477e MD |
499 | ({ \ |
500 | __typeof__(*(ptr)) _o_ = (o); \ | |
501 | __typeof__(*(ptr)) _n_ = (n); \ | |
502 | (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_, \ | |
503 | (unsigned long)_n_, sizeof(*(ptr))); \ | |
504 | }) | |
505 | ||
14cf11af PM |
506 | #ifdef CONFIG_PPC64 |
507 | /* | |
508 | * We handle most unaligned accesses in hardware. On the other hand | |
509 | * unaligned DMA can be very expensive on some ppc64 IO chips (it does | |
510 | * powers of 2 writes until it reaches sufficient alignment). | |
511 | * | |
512 | * Based on this we disable the IP header alignment in network drivers. | |
025be81e AB |
513 | * We also modify NET_SKB_PAD to be a cacheline in size, thus maintaining |
514 | * cacheline alignment of buffers. | |
14cf11af | 515 | */ |
025be81e AB |
516 | #define NET_IP_ALIGN 0 |
517 | #define NET_SKB_PAD L1_CACHE_BYTES | |
f9c4650b MD |
518 | |
519 | #define cmpxchg64(ptr, o, n) \ | |
520 | ({ \ | |
521 | BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ | |
522 | cmpxchg((ptr), (o), (n)); \ | |
523 | }) | |
524 | #define cmpxchg64_local(ptr, o, n) \ | |
525 | ({ \ | |
526 | BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ | |
527 | cmpxchg_local((ptr), (o), (n)); \ | |
528 | }) | |
529 | #else | |
530 | #include <asm-generic/cmpxchg-local.h> | |
531 | #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) | |
14cf11af PM |
532 | #endif |
533 | ||
d839088c | 534 | extern unsigned long arch_align_stack(unsigned long sp); |
14cf11af | 535 | |
9b6b563c | 536 | /* Used in very early kernel initialization. */ |
cabb5587 | 537 | extern unsigned long reloc_offset(void); |
9b6b563c PM |
538 | extern unsigned long add_reloc_offset(unsigned long); |
539 | extern void reloc_got2(unsigned long); | |
540 | ||
541 | #define PTRRELOC(x) ((typeof(x)) add_reloc_offset((unsigned long)(x))) | |
cabb5587 | 542 | |
c6622f63 PM |
543 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
544 | extern void account_system_vtime(struct task_struct *); | |
545 | #endif | |
546 | ||
94a3807c ME |
547 | extern struct dentry *powerpc_debugfs_root; |
548 | ||
14cf11af | 549 | #endif /* __KERNEL__ */ |
bbeb3f4c | 550 | #endif /* _ASM_POWERPC_SYSTEM_H */ |