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1970282f SR |
1 | #ifndef _ASM_POWERPC_TLBFLUSH_H |
2 | #define _ASM_POWERPC_TLBFLUSH_H | |
e701d269 | 3 | |
1970282f SR |
4 | /* |
5 | * TLB flushing: | |
6 | * | |
7 | * - flush_tlb_mm(mm) flushes the specified mm context TLB's | |
8 | * - flush_tlb_page(vma, vmaddr) flushes one page | |
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9 | * - local_flush_tlb_mm(mm) flushes the specified mm context on |
10 | * the local processor | |
11 | * - local_flush_tlb_page(vma, vmaddr) flushes one page on the local processor | |
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12 | * - flush_tlb_page_nohash(vma, vmaddr) flushes one page if SW loaded TLB |
13 | * - flush_tlb_range(vma, start, end) flushes a range of pages | |
14 | * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages | |
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15 | * |
16 | * This program is free software; you can redistribute it and/or | |
17 | * modify it under the terms of the GNU General Public License | |
18 | * as published by the Free Software Foundation; either version | |
19 | * 2 of the License, or (at your option) any later version. | |
20 | */ | |
21 | #ifdef __KERNEL__ | |
22 | ||
f048aace | 23 | #ifdef CONFIG_PPC_MMU_NOHASH |
62102307 DG |
24 | /* |
25 | * TLB flushing for software loaded TLB chips | |
26 | * | |
27 | * TODO: (CONFIG_FSL_BOOKE) determine if flush_tlb_range & | |
28 | * flush_tlb_kernel_range are best implemented as tlbia vs | |
29 | * specific tlbie's | |
30 | */ | |
31 | ||
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32 | #include <linux/mm.h> |
33 | ||
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34 | #define MMU_NO_CONTEXT ((unsigned int)-1) |
35 | ||
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36 | extern void _tlbil_all(void); |
37 | extern void _tlbil_pid(unsigned int pid); | |
38 | extern void _tlbil_va(unsigned long address, unsigned int pid); | |
f048aace | 39 | extern void _tlbivax_bcast(unsigned long address, unsigned int pid); |
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40 | |
41 | #if defined(CONFIG_40x) || defined(CONFIG_8xx) | |
42 | #define _tlbia() asm volatile ("tlbia; sync" : : : "memory") | |
43 | #else /* CONFIG_44x || CONFIG_FSL_BOOKE */ | |
44 | extern void _tlbia(void); | |
45 | #endif | |
1970282f | 46 | |
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47 | extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, |
48 | unsigned long end); | |
49 | extern void flush_tlb_kernel_range(unsigned long start, unsigned long end); | |
62102307 | 50 | |
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51 | extern void local_flush_tlb_mm(struct mm_struct *mm); |
52 | extern void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr); | |
62102307 | 53 | |
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54 | #ifdef CONFIG_SMP |
55 | extern void flush_tlb_mm(struct mm_struct *mm); | |
56 | extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr); | |
57 | #else | |
58 | #define flush_tlb_mm(mm) local_flush_tlb_mm(mm) | |
59 | #define flush_tlb_page(vma,addr) local_flush_tlb_page(vma,addr) | |
60 | #endif | |
61 | #define flush_tlb_page_nohash(vma,addr) flush_tlb_page(vma,addr) | |
62102307 | 62 | |
f048aace | 63 | #elif defined(CONFIG_PPC_STD_MMU_32) |
62102307 | 64 | |
62102307 | 65 | /* |
f048aace | 66 | * TLB flushing for "classic" hash-MMU 32-bit CPUs, 6xx, 7xx, 7xxx |
62102307 DG |
67 | */ |
68 | extern void _tlbie(unsigned long address); | |
69 | extern void _tlbia(void); | |
70 | ||
71 | extern void flush_tlb_mm(struct mm_struct *mm); | |
72 | extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr); | |
73 | extern void flush_tlb_page_nohash(struct vm_area_struct *vma, unsigned long addr); | |
74 | extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, | |
75 | unsigned long end); | |
76 | extern void flush_tlb_kernel_range(unsigned long start, unsigned long end); | |
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77 | static inline void local_flush_tlb_page(struct vm_area_struct *vma, |
78 | unsigned long vmaddr) | |
df3b8611 | 79 | { |
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80 | flush_tlb_page(vma, vmaddr); |
81 | } | |
82 | static inline void local_flush_tlb_mm(struct mm_struct *mm) | |
83 | { | |
84 | flush_tlb_mm(mm); | |
df3b8611 | 85 | } |
62102307 | 86 | |
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87 | #elif defined(CONFIG_PPC_STD_MMU_64) |
88 | ||
62102307 | 89 | /* |
f048aace | 90 | * TLB flushing for 64-bit hash-MMU CPUs |
62102307 | 91 | */ |
1970282f SR |
92 | |
93 | #include <linux/percpu.h> | |
94 | #include <asm/page.h> | |
95 | ||
96 | #define PPC64_TLB_BATCH_NR 192 | |
97 | ||
98 | struct ppc64_tlb_batch { | |
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99 | int active; |
100 | unsigned long index; | |
101 | struct mm_struct *mm; | |
102 | real_pte_t pte[PPC64_TLB_BATCH_NR]; | |
103 | unsigned long vaddr[PPC64_TLB_BATCH_NR]; | |
104 | unsigned int psize; | |
1189be65 | 105 | int ssize; |
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106 | }; |
107 | DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch); | |
108 | ||
109 | extern void __flush_tlb_pending(struct ppc64_tlb_batch *batch); | |
110 | ||
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111 | extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr, |
112 | pte_t *ptep, unsigned long pte, int huge); | |
113 | ||
114 | #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE | |
115 | ||
116 | static inline void arch_enter_lazy_mmu_mode(void) | |
117 | { | |
118 | struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch); | |
119 | ||
120 | batch->active = 1; | |
121 | } | |
122 | ||
123 | static inline void arch_leave_lazy_mmu_mode(void) | |
1970282f | 124 | { |
a741e679 | 125 | struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch); |
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126 | |
127 | if (batch->index) | |
128 | __flush_tlb_pending(batch); | |
a741e679 | 129 | batch->active = 0; |
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130 | } |
131 | ||
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132 | #define arch_flush_lazy_mmu_mode() do {} while (0) |
133 | ||
134 | ||
3c726f8d | 135 | extern void flush_hash_page(unsigned long va, real_pte_t pte, int psize, |
1189be65 | 136 | int ssize, int local); |
3c726f8d | 137 | extern void flush_hash_range(unsigned long number, int local); |
1970282f | 138 | |
1970282f | 139 | |
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140 | static inline void local_flush_tlb_mm(struct mm_struct *mm) |
141 | { | |
142 | } | |
143 | ||
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144 | static inline void flush_tlb_mm(struct mm_struct *mm) |
145 | { | |
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146 | } |
147 | ||
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148 | static inline void local_flush_tlb_page(struct vm_area_struct *vma, |
149 | unsigned long vmaddr) | |
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150 | { |
151 | } | |
152 | ||
1970282f | 153 | static inline void flush_tlb_page(struct vm_area_struct *vma, |
62102307 | 154 | unsigned long vmaddr) |
1970282f | 155 | { |
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156 | } |
157 | ||
158 | static inline void flush_tlb_page_nohash(struct vm_area_struct *vma, | |
159 | unsigned long vmaddr) | |
160 | { | |
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161 | } |
162 | ||
163 | static inline void flush_tlb_range(struct vm_area_struct *vma, | |
62102307 | 164 | unsigned long start, unsigned long end) |
1970282f | 165 | { |
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166 | } |
167 | ||
168 | static inline void flush_tlb_kernel_range(unsigned long start, | |
62102307 | 169 | unsigned long end) |
1970282f | 170 | { |
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171 | } |
172 | ||
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173 | /* Private function for use by PCI IO mapping code */ |
174 | extern void __flush_hash_table_range(struct mm_struct *mm, unsigned long start, | |
175 | unsigned long end); | |
176 | ||
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177 | #else |
178 | #error Unsupported MMU type | |
1970282f SR |
179 | #endif |
180 | ||
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181 | #endif /*__KERNEL__ */ |
182 | #endif /* _ASM_POWERPC_TLBFLUSH_H */ |