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Merge commit 'ftrace/function-graph' into next
[deliverable/linux.git] / arch / powerpc / kernel / align.c
CommitLineData
1da177e4
LT		 1/* align.c - handle alignment exceptions for the Power PC.
2 *
3 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
4 * Copyright (c) 1998-1999 TiVo, Inc.
5 * PowerPC 403GCX modifications.
6 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
7 * PowerPC 403GCX/405GP modifications.
8 * Copyright (c) 2001-2002 PPC64 team, IBM Corp
9 * 64-bit and Power4 support
5daf9071
BH		 10 * Copyright (c) 2005 Benjamin Herrenschmidt, IBM Corp
11 * <benh@kernel.crashing.org>
12 * Merge ppc32 and ppc64 implementations
1da177e4
LT		 13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
18 */
19
20#include <linux/kernel.h>
21#include <linux/mm.h>
22#include <asm/processor.h>
23#include <asm/uaccess.h>
24#include <asm/system.h>
25#include <asm/cache.h>
26#include <asm/cputable.h>
27
28struct aligninfo {
29 unsigned char len;
30 unsigned char flags;
31};
32
33#define IS_XFORM(inst) (((inst) >> 26) == 31)
34#define IS_DSFORM(inst) (((inst) >> 26) >= 56)
35
36#define INVALID { 0, 0 }
37
fab5db97
PM		 38/* Bits in the flags field */
39#define LD 0 /* load */
40#define ST 1 /* store */
c6d4267e 41#define SE 2 /* sign-extend value, or FP ld/st as word */
fab5db97
PM		 42#define F 4 /* to/from fp regs */
43#define U 8 /* update index register */
44#define M 0x10 /* multiple load/store */
45#define SW 0x20 /* byte swap */
46#define S 0x40 /* single-precision fp or... */
47#define SX 0x40 /* ... byte count in XER */
5daf9071 48#define HARD 0x80 /* string, stwcx. */
26caeb2e
KG		 49#define E4 0x40 /* SPE endianness is word */
50#define E8 0x80 /* SPE endianness is double word */
cd6f37be 51#define SPLT 0x80 /* VSX SPLAT load */
1da177e4 52
fab5db97 53/* DSISR bits reported for a DCBZ instruction: */
1da177e4
LT		 54#define DCBZ 0x5f /* 8xx/82xx dcbz faults when cache not enabled */
55
5daf9071
BH		 56#define SWAP(a, b) (t = (a), (a) = (b), (b) = t)
57
1da177e4
LT		 58/*
59 * The PowerPC stores certain bits of the instruction that caused the
60 * alignment exception in the DSISR register. This array maps those
61 * bits to information about the operand length and what the
62 * instruction would do.
63 */
64static struct aligninfo aligninfo[128] = {
65 { 4, LD }, /* 00 0 0000: lwz / lwarx */
66 INVALID, /* 00 0 0001 */
67 { 4, ST }, /* 00 0 0010: stw */
68 INVALID, /* 00 0 0011 */
69 { 2, LD }, /* 00 0 0100: lhz */
70 { 2, LD+SE }, /* 00 0 0101: lha */
71 { 2, ST }, /* 00 0 0110: sth */
72 { 4, LD+M }, /* 00 0 0111: lmw */
5daf9071 73 { 4, LD+F+S }, /* 00 0 1000: lfs */
1da177e4 74 { 8, LD+F }, /* 00 0 1001: lfd */
5daf9071 75 { 4, ST+F+S }, /* 00 0 1010: stfs */
1da177e4
LT		 76 { 8, ST+F }, /* 00 0 1011: stfd */
77 INVALID, /* 00 0 1100 */
5daf9071 78 { 8, LD }, /* 00 0 1101: ld/ldu/lwa */
1da177e4 79 INVALID, /* 00 0 1110 */
5daf9071 80 { 8, ST }, /* 00 0 1111: std/stdu */
1da177e4
LT		 81 { 4, LD+U }, /* 00 1 0000: lwzu */
82 INVALID, /* 00 1 0001 */
83 { 4, ST+U }, /* 00 1 0010: stwu */
84 INVALID, /* 00 1 0011 */
85 { 2, LD+U }, /* 00 1 0100: lhzu */
86 { 2, LD+SE+U }, /* 00 1 0101: lhau */
87 { 2, ST+U }, /* 00 1 0110: sthu */
88 { 4, ST+M }, /* 00 1 0111: stmw */
5daf9071 89 { 4, LD+F+S+U }, /* 00 1 1000: lfsu */
1da177e4 90 { 8, LD+F+U }, /* 00 1 1001: lfdu */
5daf9071 91 { 4, ST+F+S+U }, /* 00 1 1010: stfsu */
1da177e4 92 { 8, ST+F+U }, /* 00 1 1011: stfdu */
c6d4267e 93 { 16, LD+F }, /* 00 1 1100: lfdp */
1da177e4 94 INVALID, /* 00 1 1101 */
c6d4267e 95 { 16, ST+F }, /* 00 1 1110: stfdp */
1da177e4
LT		 96 INVALID, /* 00 1 1111 */
97 { 8, LD }, /* 01 0 0000: ldx */
98 INVALID, /* 01 0 0001 */
99 { 8, ST }, /* 01 0 0010: stdx */
100 INVALID, /* 01 0 0011 */
101 INVALID, /* 01 0 0100 */
102 { 4, LD+SE }, /* 01 0 0101: lwax */
103 INVALID, /* 01 0 0110 */
104 INVALID, /* 01 0 0111 */
5daf9071
BH		 105 { 4, LD+M+HARD+SX }, /* 01 0 1000: lswx */
106 { 4, LD+M+HARD }, /* 01 0 1001: lswi */
107 { 4, ST+M+HARD+SX }, /* 01 0 1010: stswx */
108 { 4, ST+M+HARD }, /* 01 0 1011: stswi */
1da177e4
LT		 109 INVALID, /* 01 0 1100 */
110 { 8, LD+U }, /* 01 0 1101: ldu */
111 INVALID, /* 01 0 1110 */
112 { 8, ST+U }, /* 01 0 1111: stdu */
113 { 8, LD+U }, /* 01 1 0000: ldux */
114 INVALID, /* 01 1 0001 */
115 { 8, ST+U }, /* 01 1 0010: stdux */
116 INVALID, /* 01 1 0011 */
117 INVALID, /* 01 1 0100 */
118 { 4, LD+SE+U }, /* 01 1 0101: lwaux */
119 INVALID, /* 01 1 0110 */
120 INVALID, /* 01 1 0111 */
121 INVALID, /* 01 1 1000 */
122 INVALID, /* 01 1 1001 */
123 INVALID, /* 01 1 1010 */
124 INVALID, /* 01 1 1011 */
125 INVALID, /* 01 1 1100 */
126 INVALID, /* 01 1 1101 */
127 INVALID, /* 01 1 1110 */
128 INVALID, /* 01 1 1111 */
129 INVALID, /* 10 0 0000 */
130 INVALID, /* 10 0 0001 */
5daf9071 131 INVALID, /* 10 0 0010: stwcx. */
1da177e4
LT		 132 INVALID, /* 10 0 0011 */
133 INVALID, /* 10 0 0100 */
134 INVALID, /* 10 0 0101 */
135 INVALID, /* 10 0 0110 */
136 INVALID, /* 10 0 0111 */
137 { 4, LD+SW }, /* 10 0 1000: lwbrx */
138 INVALID, /* 10 0 1001 */
139 { 4, ST+SW }, /* 10 0 1010: stwbrx */
140 INVALID, /* 10 0 1011 */
141 { 2, LD+SW }, /* 10 0 1100: lhbrx */
142 { 4, LD+SE }, /* 10 0 1101 lwa */
143 { 2, ST+SW }, /* 10 0 1110: sthbrx */
144 INVALID, /* 10 0 1111 */
145 INVALID, /* 10 1 0000 */
146 INVALID, /* 10 1 0001 */
147 INVALID, /* 10 1 0010 */
148 INVALID, /* 10 1 0011 */
149 INVALID, /* 10 1 0100 */
150 INVALID, /* 10 1 0101 */
151 INVALID, /* 10 1 0110 */
152 INVALID, /* 10 1 0111 */
153 INVALID, /* 10 1 1000 */
154 INVALID, /* 10 1 1001 */
155 INVALID, /* 10 1 1010 */
156 INVALID, /* 10 1 1011 */
157 INVALID, /* 10 1 1100 */
158 INVALID, /* 10 1 1101 */
159 INVALID, /* 10 1 1110 */
5daf9071 160 { 0, ST+HARD }, /* 10 1 1111: dcbz */
1da177e4
LT		 161 { 4, LD }, /* 11 0 0000: lwzx */
162 INVALID, /* 11 0 0001 */
163 { 4, ST }, /* 11 0 0010: stwx */
164 INVALID, /* 11 0 0011 */
165 { 2, LD }, /* 11 0 0100: lhzx */
166 { 2, LD+SE }, /* 11 0 0101: lhax */
167 { 2, ST }, /* 11 0 0110: sthx */
168 INVALID, /* 11 0 0111 */
5daf9071 169 { 4, LD+F+S }, /* 11 0 1000: lfsx */
1da177e4 170 { 8, LD+F }, /* 11 0 1001: lfdx */
5daf9071 171 { 4, ST+F+S }, /* 11 0 1010: stfsx */
1da177e4 172 { 8, ST+F }, /* 11 0 1011: stfdx */
c6d4267e
PM		 173 { 16, LD+F }, /* 11 0 1100: lfdpx */
174 { 4, LD+F+SE }, /* 11 0 1101: lfiwax */
175 { 16, ST+F }, /* 11 0 1110: stfdpx */
176 { 4, ST+F }, /* 11 0 1111: stfiwx */
1da177e4
LT		 177 { 4, LD+U }, /* 11 1 0000: lwzux */
178 INVALID, /* 11 1 0001 */
179 { 4, ST+U }, /* 11 1 0010: stwux */
180 INVALID, /* 11 1 0011 */
181 { 2, LD+U }, /* 11 1 0100: lhzux */
182 { 2, LD+SE+U }, /* 11 1 0101: lhaux */
183 { 2, ST+U }, /* 11 1 0110: sthux */
184 INVALID, /* 11 1 0111 */
5daf9071 185 { 4, LD+F+S+U }, /* 11 1 1000: lfsux */
1da177e4 186 { 8, LD+F+U }, /* 11 1 1001: lfdux */
5daf9071 187 { 4, ST+F+S+U }, /* 11 1 1010: stfsux */
1da177e4
LT		 188 { 8, ST+F+U }, /* 11 1 1011: stfdux */
189 INVALID, /* 11 1 1100 */
190 INVALID, /* 11 1 1101 */
191 INVALID, /* 11 1 1110 */
192 INVALID, /* 11 1 1111 */
193};
194
5daf9071
BH		 195/*
196 * Create a DSISR value from the instruction
197 */
1da177e4
LT		 198static inline unsigned make_dsisr(unsigned instr)
199{
200 unsigned dsisr;
5daf9071
BH		 201
202
203 /* bits 6:15 --> 22:31 */
204 dsisr = (instr & 0x03ff0000) >> 16;
205
206 if (IS_XFORM(instr)) {
207 /* bits 29:30 --> 15:16 */
208 dsisr |= (instr & 0x00000006) << 14;
209 /* bit 25 --> 17 */
210 dsisr |= (instr & 0x00000040) << 8;
211 /* bits 21:24 --> 18:21 */
212 dsisr |= (instr & 0x00000780) << 3;
213 } else {
214 /* bit 5 --> 17 */
215 dsisr |= (instr & 0x04000000) >> 12;
216 /* bits 1: 4 --> 18:21 */
217 dsisr |= (instr & 0x78000000) >> 17;
218 /* bits 30:31 --> 12:13 */
219 if (IS_DSFORM(instr))
220 dsisr |= (instr & 0x00000003) << 18;
1da177e4 221 }
5daf9071
BH		 222
223 return dsisr;
224}
225
226/*
227 * The dcbz (data cache block zero) instruction
228 * gives an alignment fault if used on non-cacheable
229 * memory. We handle the fault mainly for the
230 * case when we are running with the cache disabled
231 * for debugging.
232 */
233static int emulate_dcbz(struct pt_regs *regs, unsigned char __user *addr)
234{
235 long __user *p;
236 int i, size;
237
238#ifdef __powerpc64__
239 size = ppc64_caches.dline_size;
240#else
241 size = L1_CACHE_BYTES;
242#endif
243 p = (long __user *) (regs->dar & -size);
244 if (user_mode(regs) && !access_ok(VERIFY_WRITE, p, size))
245 return -EFAULT;
246 for (i = 0; i < size / sizeof(long); ++i)
e4ee3891 247 if (__put_user_inatomic(0, p+i))
5daf9071
BH		 248 return -EFAULT;
249 return 1;
250}
251
252/*
253 * Emulate load & store multiple instructions
254 * On 64-bit machines, these instructions only affect/use the
255 * bottom 4 bytes of each register, and the loads clear the
256 * top 4 bytes of the affected register.
257 */
258#ifdef CONFIG_PPC64
259#define REG_BYTE(rp, i) *((u8 *)((rp) + ((i) >> 2)) + ((i) & 3) + 4)
260#else
261#define REG_BYTE(rp, i) *((u8 *)(rp) + (i))
262#endif
263
fab5db97
PM		 264#define SWIZ_PTR(p) ((unsigned char __user *)((p) ^ swiz))
265
5daf9071
BH		 266static int emulate_multiple(struct pt_regs *regs, unsigned char __user *addr,
267 unsigned int reg, unsigned int nb,
fab5db97
PM		 268 unsigned int flags, unsigned int instr,
269 unsigned long swiz)
5daf9071
BH		 270{
271 unsigned long *rptr;
fab5db97
PM		 272 unsigned int nb0, i, bswiz;
273 unsigned long p;
5daf9071
BH		 274
275 /*
276 * We do not try to emulate 8 bytes multiple as they aren't really
277 * available in our operating environments and we don't try to
278 * emulate multiples operations in kernel land as they should never
279 * be used/generated there at least not on unaligned boundaries
280 */
281 if (unlikely((nb > 4) || !user_mode(regs)))
282 return 0;
283
284 /* lmw, stmw, lswi/x, stswi/x */
285 nb0 = 0;
286 if (flags & HARD) {
287 if (flags & SX) {
288 nb = regs->xer & 127;
289 if (nb == 0)
290 return 1;
291 } else {
fab5db97
PM		 292 unsigned long pc = regs->nip ^ (swiz & 4);
293
e4ee3891
BH		 294 if (__get_user_inatomic(instr,
295 (unsigned int __user *)pc))
5daf9071 296 return -EFAULT;
fab5db97
PM		 297 if (swiz == 0 && (flags & SW))
298 instr = cpu_to_le32(instr);
5daf9071
BH		 299 nb = (instr >> 11) & 0x1f;
300 if (nb == 0)
301 nb = 32;
1da177e4 302 }
5daf9071
BH		 303 if (nb + reg * 4 > 128) {
304 nb0 = nb + reg * 4 - 128;
305 nb = 128 - reg * 4;
306 }
307 } else {
308 /* lwm, stmw */
309 nb = (32 - reg) * 4;
1da177e4 310 }
5daf9071
BH		 311
312 if (!access_ok((flags & ST ? VERIFY_WRITE: VERIFY_READ), addr, nb+nb0))
313 return -EFAULT; /* bad address */
314
315 rptr = &regs->gpr[reg];
fab5db97
PM		 316 p = (unsigned long) addr;
317 bswiz = (flags & SW)? 3: 0;
318
319 if (!(flags & ST)) {
5daf9071
BH		 320 /*
321 * This zeroes the top 4 bytes of the affected registers
322 * in 64-bit mode, and also zeroes out any remaining
323 * bytes of the last register for lsw*.
324 */
325 memset(rptr, 0, ((nb + 3) / 4) * sizeof(unsigned long));
326 if (nb0 > 0)
327 memset(&regs->gpr[0], 0,
328 ((nb0 + 3) / 4) * sizeof(unsigned long));
329
fab5db97 330 for (i = 0; i < nb; ++i, ++p)
e4ee3891
BH		 331 if (__get_user_inatomic(REG_BYTE(rptr, i ^ bswiz),
332 SWIZ_PTR(p)))
5daf9071
BH		 333 return -EFAULT;
334 if (nb0 > 0) {
335 rptr = &regs->gpr[0];
336 addr += nb;
fab5db97 337 for (i = 0; i < nb0; ++i, ++p)
e4ee3891
BH		 338 if (__get_user_inatomic(REG_BYTE(rptr,
339 i ^ bswiz),
340 SWIZ_PTR(p)))
5daf9071
BH		 341 return -EFAULT;
342 }
343
344 } else {
fab5db97 345 for (i = 0; i < nb; ++i, ++p)
e4ee3891
BH		 346 if (__put_user_inatomic(REG_BYTE(rptr, i ^ bswiz),
347 SWIZ_PTR(p)))
5daf9071
BH		 348 return -EFAULT;
349 if (nb0 > 0) {
350 rptr = &regs->gpr[0];
351 addr += nb;
fab5db97 352 for (i = 0; i < nb0; ++i, ++p)
e4ee3891
BH		 353 if (__put_user_inatomic(REG_BYTE(rptr,
354 i ^ bswiz),
355 SWIZ_PTR(p)))
5daf9071
BH		 356 return -EFAULT;
357 }
358 }
359 return 1;
1da177e4
LT		 360}
361
c6d4267e
PM		 362/*
363 * Emulate floating-point pair loads and stores.
364 * Only POWER6 has these instructions, and it does true little-endian,
365 * so we don't need the address swizzling.
366 */
b887ec62
MN		 367static int emulate_fp_pair(unsigned char __user *addr, unsigned int reg,
368 unsigned int flags)
c6d4267e 369{
9c75a31c 370 char *ptr = (char *) &current->thread.TS_FPR(reg);
c6d4267e
PM		 371 int i, ret;
372
373 if (!(flags & F))
374 return 0;
375 if (reg & 1)
376 return 0; /* invalid form: FRS/FRT must be even */
377 if (!(flags & SW)) {
378 /* not byte-swapped - easy */
379 if (!(flags & ST))
380 ret = __copy_from_user(ptr, addr, 16);
381 else
382 ret = __copy_to_user(addr, ptr, 16);
383 } else {
384 /* each FPR value is byte-swapped separately */
385 ret = 0;
386 for (i = 0; i < 16; ++i) {
387 if (!(flags & ST))
388 ret |= __get_user(ptr[i^7], addr + i);
389 else
390 ret |= __put_user(ptr[i^7], addr + i);
391 }
392 }
393 if (ret)
394 return -EFAULT;
395 return 1; /* exception handled and fixed up */
396}
397
26caeb2e
KG		 398#ifdef CONFIG_SPE
399
400static struct aligninfo spe_aligninfo[32] = {
401 { 8, LD+E8 }, /* 0 00 00: evldd[x] */
402 { 8, LD+E4 }, /* 0 00 01: evldw[x] */
403 { 8, LD }, /* 0 00 10: evldh[x] */
404 INVALID, /* 0 00 11 */
405 { 2, LD }, /* 0 01 00: evlhhesplat[x] */
406 INVALID, /* 0 01 01 */
407 { 2, LD }, /* 0 01 10: evlhhousplat[x] */
408 { 2, LD+SE }, /* 0 01 11: evlhhossplat[x] */
409 { 4, LD }, /* 0 10 00: evlwhe[x] */
410 INVALID, /* 0 10 01 */
411 { 4, LD }, /* 0 10 10: evlwhou[x] */
412 { 4, LD+SE }, /* 0 10 11: evlwhos[x] */
413 { 4, LD+E4 }, /* 0 11 00: evlwwsplat[x] */
414 INVALID, /* 0 11 01 */
415 { 4, LD }, /* 0 11 10: evlwhsplat[x] */
416 INVALID, /* 0 11 11 */
417
418 { 8, ST+E8 }, /* 1 00 00: evstdd[x] */
419 { 8, ST+E4 }, /* 1 00 01: evstdw[x] */
420 { 8, ST }, /* 1 00 10: evstdh[x] */
421 INVALID, /* 1 00 11 */
422 INVALID, /* 1 01 00 */
423 INVALID, /* 1 01 01 */
424 INVALID, /* 1 01 10 */
425 INVALID, /* 1 01 11 */
426 { 4, ST }, /* 1 10 00: evstwhe[x] */
427 INVALID, /* 1 10 01 */
428 { 4, ST }, /* 1 10 10: evstwho[x] */
429 INVALID, /* 1 10 11 */
430 { 4, ST+E4 }, /* 1 11 00: evstwwe[x] */
431 INVALID, /* 1 11 01 */
432 { 4, ST+E4 }, /* 1 11 10: evstwwo[x] */
433 INVALID, /* 1 11 11 */
434};
435
436#define EVLDD 0x00
437#define EVLDW 0x01
438#define EVLDH 0x02
439#define EVLHHESPLAT 0x04
440#define EVLHHOUSPLAT 0x06
441#define EVLHHOSSPLAT 0x07
442#define EVLWHE 0x08
443#define EVLWHOU 0x0A
444#define EVLWHOS 0x0B
445#define EVLWWSPLAT 0x0C
446#define EVLWHSPLAT 0x0E
447#define EVSTDD 0x10
448#define EVSTDW 0x11
449#define EVSTDH 0x12
450#define EVSTWHE 0x18
451#define EVSTWHO 0x1A
452#define EVSTWWE 0x1C
453#define EVSTWWO 0x1E
454
455/*
456 * Emulate SPE loads and stores.
457 * Only Book-E has these instructions, and it does true little-endian,
458 * so we don't need the address swizzling.
459 */
460static int emulate_spe(struct pt_regs *regs, unsigned int reg,
461 unsigned int instr)
462{
463 int t, ret;
464 union {
465 u64 ll;
466 u32 w[2];
467 u16 h[4];
468 u8 v[8];
469 } data, temp;
470 unsigned char __user *p, *addr;
471 unsigned long *evr = &current->thread.evr[reg];
472 unsigned int nb, flags;
473
474 instr = (instr >> 1) & 0x1f;
475
476 /* DAR has the operand effective address */
477 addr = (unsigned char __user *)regs->dar;
478
479 nb = spe_aligninfo[instr].len;
480 flags = spe_aligninfo[instr].flags;
481
482 /* Verify the address of the operand */
483 if (unlikely(user_mode(regs) &&
484 !access_ok((flags & ST ? VERIFY_WRITE : VERIFY_READ),
485 addr, nb)))
486 return -EFAULT;
487
488 /* userland only */
489 if (unlikely(!user_mode(regs)))
490 return 0;
491
492 flush_spe_to_thread(current);
493
494 /* If we are loading, get the data from user space, else
495 * get it from register values
496 */
497 if (flags & ST) {
498 data.ll = 0;
499 switch (instr) {
500 case EVSTDD:
501 case EVSTDW:
502 case EVSTDH:
503 data.w[0] = *evr;
504 data.w[1] = regs->gpr[reg];
505 break;
506 case EVSTWHE:
507 data.h[2] = *evr >> 16;
508 data.h[3] = regs->gpr[reg] >> 16;
509 break;
510 case EVSTWHO:
511 data.h[2] = *evr & 0xffff;
512 data.h[3] = regs->gpr[reg] & 0xffff;
513 break;
514 case EVSTWWE:
515 data.w[1] = *evr;
516 break;
517 case EVSTWWO:
518 data.w[1] = regs->gpr[reg];
519 break;
520 default:
521 return -EINVAL;
522 }
523 } else {
524 temp.ll = data.ll = 0;
525 ret = 0;
526 p = addr;
527
528 switch (nb) {
529 case 8:
530 ret |= __get_user_inatomic(temp.v[0], p++);
531 ret |= __get_user_inatomic(temp.v[1], p++);
532 ret |= __get_user_inatomic(temp.v[2], p++);
533 ret |= __get_user_inatomic(temp.v[3], p++);
534 case 4:
535 ret |= __get_user_inatomic(temp.v[4], p++);
536 ret |= __get_user_inatomic(temp.v[5], p++);
537 case 2:
538 ret |= __get_user_inatomic(temp.v[6], p++);
539 ret |= __get_user_inatomic(temp.v[7], p++);
540 if (unlikely(ret))
541 return -EFAULT;
542 }
543
544 switch (instr) {
545 case EVLDD:
546 case EVLDW:
547 case EVLDH:
548 data.ll = temp.ll;
549 break;
550 case EVLHHESPLAT:
551 data.h[0] = temp.h[3];
552 data.h[2] = temp.h[3];
553 break;
554 case EVLHHOUSPLAT:
555 case EVLHHOSSPLAT:
556 data.h[1] = temp.h[3];
557 data.h[3] = temp.h[3];
558 break;
559 case EVLWHE:
560 data.h[0] = temp.h[2];
561 data.h[2] = temp.h[3];
562 break;
563 case EVLWHOU:
564 case EVLWHOS:
565 data.h[1] = temp.h[2];
566 data.h[3] = temp.h[3];
567 break;
568 case EVLWWSPLAT:
569 data.w[0] = temp.w[1];
570 data.w[1] = temp.w[1];
571 break;
572 case EVLWHSPLAT:
573 data.h[0] = temp.h[2];
574 data.h[1] = temp.h[2];
575 data.h[2] = temp.h[3];
576 data.h[3] = temp.h[3];
577 break;
578 default:
579 return -EINVAL;
580 }
581 }
582
583 if (flags & SW) {
584 switch (flags & 0xf0) {
585 case E8:
586 SWAP(data.v[0], data.v[7]);
587 SWAP(data.v[1], data.v[6]);
588 SWAP(data.v[2], data.v[5]);
589 SWAP(data.v[3], data.v[4]);
590 break;
591 case E4:
592
593 SWAP(data.v[0], data.v[3]);
594 SWAP(data.v[1], data.v[2]);
595 SWAP(data.v[4], data.v[7]);
596 SWAP(data.v[5], data.v[6]);
597 break;
598 /* Its half word endian */
599 default:
600 SWAP(data.v[0], data.v[1]);
601 SWAP(data.v[2], data.v[3]);
602 SWAP(data.v[4], data.v[5]);
603 SWAP(data.v[6], data.v[7]);
604 break;
605 }
606 }
607
608 if (flags & SE) {
609 data.w[0] = (s16)data.h[1];
610 data.w[1] = (s16)data.h[3];
611 }
612
613 /* Store result to memory or update registers */
614 if (flags & ST) {
615 ret = 0;
616 p = addr;
617 switch (nb) {
618 case 8:
619 ret |= __put_user_inatomic(data.v[0], p++);
620 ret |= __put_user_inatomic(data.v[1], p++);
621 ret |= __put_user_inatomic(data.v[2], p++);
622 ret |= __put_user_inatomic(data.v[3], p++);
623 case 4:
624 ret |= __put_user_inatomic(data.v[4], p++);
625 ret |= __put_user_inatomic(data.v[5], p++);
626 case 2:
627 ret |= __put_user_inatomic(data.v[6], p++);
628 ret |= __put_user_inatomic(data.v[7], p++);
629 }
630 if (unlikely(ret))
631 return -EFAULT;
632 } else {
633 *evr = data.w[0];
634 regs->gpr[reg] = data.w[1];
635 }
636
637 return 1;
638}
639#endif /* CONFIG_SPE */
5daf9071 640
cd6f37be
MN		 641#ifdef CONFIG_VSX
642/*
643 * Emulate VSX instructions...
644 */
645static int emulate_vsx(unsigned char __user *addr, unsigned int reg,
646 unsigned int areg, struct pt_regs *regs,
647 unsigned int flags, unsigned int length)
648{
26456dcf 649 char *ptr;
78fbc824 650 int ret = 0;
cd6f37be
MN		 651
652 flush_vsx_to_thread(current);
653
26456dcf
MN		 654 if (reg < 32)
655 ptr = (char *) &current->thread.TS_FPR(reg);
656 else
657 ptr = (char *) &current->thread.vr[reg - 32];
658
cd6f37be
MN		 659 if (flags & ST)
660 ret = __copy_to_user(addr, ptr, length);
661 else {
662 if (flags & SPLT){
663 ret = __copy_from_user(ptr, addr, length);
664 ptr += length;
665 }
666 ret |= __copy_from_user(ptr, addr, length);
667 }
668 if (flags & U)
669 regs->gpr[areg] = regs->dar;
670 if (ret)
671 return -EFAULT;
672 return 1;
673}
674#endif
675
5daf9071
BH		 676/*
677 * Called on alignment exception. Attempts to fixup
678 *
679 * Return 1 on success
680 * Return 0 if unable to handle the interrupt
681 * Return -EFAULT if data address is bad
682 */
683
684int fix_alignment(struct pt_regs *regs)
1da177e4 685{
cd6f37be 686 unsigned int instr, nb, flags, instruction = 0;
5daf9071
BH		 687 unsigned int reg, areg;
688 unsigned int dsisr;
1da177e4 689 unsigned char __user *addr;
fab5db97 690 unsigned long p, swiz;
5daf9071 691 int ret, t;
1da177e4 692 union {
5daf9071 693 u64 ll;
1da177e4
LT		 694 double dd;
695 unsigned char v[8];
696 struct {
697 unsigned hi32;
698 int low32;
699 } x32;
700 struct {
701 unsigned char hi48[6];
702 short low16;
703 } x16;
704 } data;
705
706 /*
5daf9071
BH		 707 * We require a complete register set, if not, then our assembly
708 * is broken
1da177e4 709 */
5daf9071 710 CHECK_FULL_REGS(regs);
1da177e4
LT		 711
712 dsisr = regs->dsisr;
713
5daf9071
BH		 714 /* Some processors don't provide us with a DSISR we can use here,
715 * let's make one up from the instruction
716 */
1da177e4 717 if (cpu_has_feature(CPU_FTR_NODSISRALIGN)) {
fab5db97
PM		 718 unsigned long pc = regs->nip;
719
720 if (cpu_has_feature(CPU_FTR_PPC_LE) && (regs->msr & MSR_LE))
721 pc ^= 4;
e4ee3891
BH		 722 if (unlikely(__get_user_inatomic(instr,
723 (unsigned int __user *)pc)))
5daf9071 724 return -EFAULT;
fab5db97
PM		 725 if (cpu_has_feature(CPU_FTR_REAL_LE) && (regs->msr & MSR_LE))
726 instr = cpu_to_le32(instr);
727 dsisr = make_dsisr(instr);
cd6f37be 728 instruction = instr;
1da177e4
LT		 729 }
730
731 /* extract the operation and registers from the dsisr */
732 reg = (dsisr >> 5) & 0x1f; /* source/dest register */
733 areg = dsisr & 0x1f; /* register to update */
26caeb2e
KG		 734
735#ifdef CONFIG_SPE
736 if ((instr >> 26) == 0x4)
737 return emulate_spe(regs, reg, instr);
738#endif
739
1da177e4
LT		 740 instr = (dsisr >> 10) & 0x7f;
741 instr |= (dsisr >> 13) & 0x60;
742
743 /* Lookup the operation in our table */
744 nb = aligninfo[instr].len;
745 flags = aligninfo[instr].flags;
746
fab5db97
PM		 747 /* Byteswap little endian loads and stores */
748 swiz = 0;
749 if (regs->msr & MSR_LE) {
750 flags ^= SW;
751 /*
752 * So-called "PowerPC little endian" mode works by
753 * swizzling addresses rather than by actually doing
754 * any byte-swapping. To emulate this, we XOR each
755 * byte address with 7. We also byte-swap, because
756 * the processor's address swizzling depends on the
757 * operand size (it xors the address with 7 for bytes,
758 * 6 for halfwords, 4 for words, 0 for doublewords) but
759 * we will xor with 7 and load/store each byte separately.
760 */
761 if (cpu_has_feature(CPU_FTR_PPC_LE))
762 swiz = 7;
763 }
764
1da177e4
LT		 765 /* DAR has the operand effective address */
766 addr = (unsigned char __user *)regs->dar;
767
cd6f37be
MN		 768#ifdef CONFIG_VSX
769 if ((instruction & 0xfc00003e) == 0x7c000018) {
770 /* Additional register addressing bit (64 VSX vs 32 FPR/GPR */
771 reg |= (instruction & 0x1) << 5;
772 /* Simple inline decoder instead of a table */
773 if (instruction & 0x200)
774 nb = 16;
775 else if (instruction & 0x080)
776 nb = 8;
777 else
778 nb = 4;
779 flags = 0;
780 if (instruction & 0x100)
781 flags |= ST;
782 if (instruction & 0x040)
783 flags |= U;
784 /* splat load needs a special decoder */
785 if ((instruction & 0x400) == 0){
786 flags |= SPLT;
787 nb = 8;
788 }
789 return emulate_vsx(addr, reg, areg, regs, flags, nb);
790 }
791#endif
5daf9071
BH		 792 /* A size of 0 indicates an instruction we don't support, with
793 * the exception of DCBZ which is handled as a special case here
1da177e4
LT		 794 */
795 if (instr == DCBZ)
5daf9071
BH		 796 return emulate_dcbz(regs, addr);
797 if (unlikely(nb == 0))
798 return 0;
799
800 /* Load/Store Multiple instructions are handled in their own
801 * function
802 */
803 if (flags & M)
fab5db97
PM		 804 return emulate_multiple(regs, addr, reg, nb,
805 flags, instr, swiz);
1da177e4
LT		 806
807 /* Verify the address of the operand */
5daf9071
BH		 808 if (unlikely(user_mode(regs) &&
809 !access_ok((flags & ST ? VERIFY_WRITE : VERIFY_READ),
810 addr, nb)))
811 return -EFAULT;
1da177e4
LT		 812
813 /* Force the fprs into the save area so we can reference them */
814 if (flags & F) {
5daf9071
BH		 815 /* userland only */
816 if (unlikely(!user_mode(regs)))
1da177e4
LT		 817 return 0;
818 flush_fp_to_thread(current);
819 }
5daf9071 820
c6d4267e
PM		 821 /* Special case for 16-byte FP loads and stores */
822 if (nb == 16)
b887ec62 823 return emulate_fp_pair(addr, reg, flags);
c6d4267e 824
5daf9071
BH		 825 /* If we are loading, get the data from user space, else
826 * get it from register values
827 */
fab5db97 828 if (!(flags & ST)) {
1da177e4
LT		 829 data.ll = 0;
830 ret = 0;
fab5db97 831 p = (unsigned long) addr;
1da177e4
LT		 832 switch (nb) {
833 case 8:
e4ee3891
BH		 834 ret |= __get_user_inatomic(data.v[0], SWIZ_PTR(p++));
835 ret |= __get_user_inatomic(data.v[1], SWIZ_PTR(p++));
836 ret |= __get_user_inatomic(data.v[2], SWIZ_PTR(p++));
837 ret |= __get_user_inatomic(data.v[3], SWIZ_PTR(p++));
1da177e4 838 case 4:
e4ee3891
BH		 839 ret |= __get_user_inatomic(data.v[4], SWIZ_PTR(p++));
840 ret |= __get_user_inatomic(data.v[5], SWIZ_PTR(p++));
1da177e4 841 case 2:
e4ee3891
BH		 842 ret |= __get_user_inatomic(data.v[6], SWIZ_PTR(p++));
843 ret |= __get_user_inatomic(data.v[7], SWIZ_PTR(p++));
5daf9071 844 if (unlikely(ret))
1da177e4
LT		 845 return -EFAULT;
846 }
fab5db97 847 } else if (flags & F) {
9c75a31c 848 data.dd = current->thread.TS_FPR(reg);
fab5db97
PM		 849 if (flags & S) {
850 /* Single-precision FP store requires conversion... */
851#ifdef CONFIG_PPC_FPU
852 preempt_disable();
853 enable_kernel_fp();
854 cvt_df(&data.dd, (float *)&data.v[4], &current->thread);
855 preempt_enable();
856#else
857 return 0;
858#endif
859 }
860 } else
5daf9071
BH		 861 data.ll = regs->gpr[reg];
862
fab5db97
PM		 863 if (flags & SW) {
864 switch (nb) {
865 case 8:
866 SWAP(data.v[0], data.v[7]);
867 SWAP(data.v[1], data.v[6]);
868 SWAP(data.v[2], data.v[5]);
869 SWAP(data.v[3], data.v[4]);
870 break;
871 case 4:
872 SWAP(data.v[4], data.v[7]);
873 SWAP(data.v[5], data.v[6]);
874 break;
875 case 2:
876 SWAP(data.v[6], data.v[7]);
877 break;
878 }
879 }
880
881 /* Perform other misc operations like sign extension
5daf9071
BH		 882 * or floating point single precision conversion
883 */
fab5db97 884 switch (flags & ~(U|SW)) {
c6d4267e
PM		 885 case LD+SE: /* sign extending integer loads */
886 case LD+F+SE: /* sign extend for lfiwax */
1da177e4
LT		 887 if ( nb == 2 )
888 data.ll = data.x16.low16;
889 else /* nb must be 4 */
890 data.ll = data.x32.low32;
5daf9071 891 break;
5daf9071 892
fab5db97 893 /* Single-precision FP load requires conversion... */
5daf9071
BH		 894 case LD+F+S:
895#ifdef CONFIG_PPC_FPU
896 preempt_disable();
897 enable_kernel_fp();
898 cvt_fd((float *)&data.v[4], &data.dd, &current->thread);
899 preempt_enable();
900#else
901 return 0;
5daf9071
BH		 902#endif
903 break;
1da177e4 904 }
5daf9071
BH		 905
906 /* Store result to memory or update registers */
1da177e4
LT		 907 if (flags & ST) {
908 ret = 0;
fab5db97 909 p = (unsigned long) addr;
1da177e4 910 switch (nb) {
1da177e4 911 case 8:
e4ee3891
BH		 912 ret |= __put_user_inatomic(data.v[0], SWIZ_PTR(p++));
913 ret |= __put_user_inatomic(data.v[1], SWIZ_PTR(p++));
914 ret |= __put_user_inatomic(data.v[2], SWIZ_PTR(p++));
915 ret |= __put_user_inatomic(data.v[3], SWIZ_PTR(p++));
1da177e4 916 case 4:
e4ee3891
BH		 917 ret |= __put_user_inatomic(data.v[4], SWIZ_PTR(p++));
918 ret |= __put_user_inatomic(data.v[5], SWIZ_PTR(p++));
1da177e4 919 case 2:
e4ee3891
BH		 920 ret |= __put_user_inatomic(data.v[6], SWIZ_PTR(p++));
921 ret |= __put_user_inatomic(data.v[7], SWIZ_PTR(p++));
1da177e4 922 }
5daf9071 923 if (unlikely(ret))
1da177e4 924 return -EFAULT;
5daf9071 925 } else if (flags & F)
9c75a31c 926 current->thread.TS_FPR(reg) = data.dd;
5daf9071
BH		 927 else
928 regs->gpr[reg] = data.ll;
929
1da177e4 930 /* Update RA as needed */
5daf9071 931 if (flags & U)
1da177e4 932 regs->gpr[areg] = regs->dar;
1da177e4
LT		 933
934 return 1;
935}
Linux kernel - Deliverables
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