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powerpc/mm/radix: Update LPCR only if it is powernv
[deliverable/linux.git] / arch / powerpc / kernel / asm-offsets.c
CommitLineData
14cf11af
PM		 1/*
2 * This program is used to generate definitions needed by
3 * assembly language modules.
4 *
5 * We use the technique used in the OSF Mach kernel code:
6 * generate asm statements containing #defines,
7 * compile this file to assembler, and then extract the
8 * #defines from the assembly-language output.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
14cf11af
PM		 16#include <linux/signal.h>
17#include <linux/sched.h>
18#include <linux/kernel.h>
19#include <linux/errno.h>
20#include <linux/string.h>
21#include <linux/types.h>
14cf11af
PM		 22#include <linux/mman.h>
23#include <linux/mm.h>
543b9fd3 24#include <linux/suspend.h>
ad7f7167 25#include <linux/hrtimer.h>
d1dead5c 26#ifdef CONFIG_PPC64
14cf11af
PM		 27#include <linux/time.h>
28#include <linux/hardirq.h>
d1dead5c 29#endif
d4d298fe 30#include <linux/kbuild.h>
d1dead5c 31
14cf11af
PM		 32#include <asm/io.h>
33#include <asm/page.h>
34#include <asm/pgtable.h>
35#include <asm/processor.h>
14cf11af
PM		 36#include <asm/cputable.h>
37#include <asm/thread_info.h>
033ef338 38#include <asm/rtas.h>
a7f290da 39#include <asm/vdso_datapage.h>
66feed61 40#include <asm/dbell.h>
14cf11af
PM		 41#ifdef CONFIG_PPC64
42#include <asm/paca.h>
43#include <asm/lppaca.h>
14cf11af 44#include <asm/cache.h>
14cf11af 45#include <asm/compat.h>
11a27ad7 46#include <asm/mmu.h>
f04da0bc 47#include <asm/hvcall.h>
19ccb76a 48#include <asm/xics.h>
14cf11af 49#endif
ed79ba9e
BH		 50#ifdef CONFIG_PPC_POWERNV
51#include <asm/opal.h>
52#endif
989044ee 53#if defined(CONFIG_KVM) || defined(CONFIG_KVM_GUEST)
366d4b9b 54#include <linux/kvm_host.h>
0604675f 55#endif
989044ee
AG		 56#if defined(CONFIG_KVM) && defined(CONFIG_PPC_BOOK3S)
57#include <asm/kvm_book3s.h>
5deb8e7a 58#include <asm/kvm_ppc.h>
db93f574 59#endif
14cf11af 60
57e2a99f 61#ifdef CONFIG_PPC32
fca622c5
KG		 62#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
63#include "head_booke.h"
64#endif
57e2a99f 65#endif
fca622c5 66
55fd766b 67#if defined(CONFIG_PPC_FSL_BOOK3E)
19f5465e
TP		 68#include "../mm/mmu_decl.h"
69#endif
70
14cf11af
PM		 71int main(void)
72{
d1dead5c
SR		 73 DEFINE(THREAD, offsetof(struct task_struct, thread));
74 DEFINE(MM, offsetof(struct task_struct, mm));
5e696617 75 DEFINE(MMCONTEXTID, offsetof(struct mm_struct, context.id));
14cf11af 76#ifdef CONFIG_PPC64
d1dead5c 77 DEFINE(AUDITCONTEXT, offsetof(struct task_struct, audit_context));
9c1e1052
PM		 78 DEFINE(SIGSEGV, SIGSEGV);
79 DEFINE(NMI_MASK, NMI_MASK);
efcac658 80 DEFINE(THREAD_DSCR, offsetof(struct thread_struct, dscr));
71433285 81 DEFINE(THREAD_DSCR_INHERIT, offsetof(struct thread_struct, dscr_inherit));
92779245 82 DEFINE(TASKTHREADPPR, offsetof(struct task_struct, thread.ppr));
d1dead5c 83#else
f7e4217b 84 DEFINE(THREAD_INFO, offsetof(struct task_struct, stack));
cbc9565e
BH		 85 DEFINE(THREAD_INFO_GAP, _ALIGN_UP(sizeof(struct thread_info), 16));
86 DEFINE(KSP_LIMIT, offsetof(struct thread_struct, ksp_limit));
d1dead5c
SR		 87#endif /* CONFIG_PPC64 */
88
85baa095
ME		 89#ifdef CONFIG_LIVEPATCH
90 DEFINE(TI_livepatch_sp, offsetof(struct thread_info, livepatch_sp));
91#endif
92
14cf11af 93 DEFINE(KSP, offsetof(struct thread_struct, ksp));
14cf11af 94 DEFINE(PT_REGS, offsetof(struct thread_struct, regs));
1325a684
AK		 95#ifdef CONFIG_BOOKE
96 DEFINE(THREAD_NORMSAVES, offsetof(struct thread_struct, normsave[0]));
97#endif
14cf11af 98 DEFINE(THREAD_FPEXC_MODE, offsetof(struct thread_struct, fpexc_mode));
de79f7b9 99 DEFINE(THREAD_FPSTATE, offsetof(struct thread_struct, fp_state));
18461960 100 DEFINE(THREAD_FPSAVEAREA, offsetof(struct thread_struct, fp_save_area));
de79f7b9 101 DEFINE(FPSTATE_FPSCR, offsetof(struct thread_fp_state, fpscr));
70fe3d98 102 DEFINE(THREAD_LOAD_FP, offsetof(struct thread_struct, load_fp));
14cf11af 103#ifdef CONFIG_ALTIVEC
de79f7b9 104 DEFINE(THREAD_VRSTATE, offsetof(struct thread_struct, vr_state));
18461960 105 DEFINE(THREAD_VRSAVEAREA, offsetof(struct thread_struct, vr_save_area));
14cf11af 106 DEFINE(THREAD_VRSAVE, offsetof(struct thread_struct, vrsave));
14cf11af 107 DEFINE(THREAD_USED_VR, offsetof(struct thread_struct, used_vr));
de79f7b9 108 DEFINE(VRSTATE_VSCR, offsetof(struct thread_vr_state, vscr));
70fe3d98 109 DEFINE(THREAD_LOAD_VEC, offsetof(struct thread_struct, load_vec));
14cf11af 110#endif /* CONFIG_ALTIVEC */
c6e6771b 111#ifdef CONFIG_VSX
c6e6771b
MN		 112 DEFINE(THREAD_USED_VSR, offsetof(struct thread_struct, used_vsr));
113#endif /* CONFIG_VSX */
d1dead5c
SR		 114#ifdef CONFIG_PPC64
115 DEFINE(KSP_VSID, offsetof(struct thread_struct, ksp_vsid));
116#else /* CONFIG_PPC64 */
117 DEFINE(PGDIR, offsetof(struct thread_struct, pgdir));
14cf11af
PM		 118#ifdef CONFIG_SPE
119 DEFINE(THREAD_EVR0, offsetof(struct thread_struct, evr[0]));
120 DEFINE(THREAD_ACC, offsetof(struct thread_struct, acc));
121 DEFINE(THREAD_SPEFSCR, offsetof(struct thread_struct, spefscr));
122 DEFINE(THREAD_USED_SPE, offsetof(struct thread_struct, used_spe));
123#endif /* CONFIG_SPE */
d1dead5c 124#endif /* CONFIG_PPC64 */
13d543cd 125#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
51ae8d4a 126 DEFINE(THREAD_DBCR0, offsetof(struct thread_struct, debug.dbcr0));
13d543cd 127#endif
97e49255
AG		 128#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
129 DEFINE(THREAD_KVM_SVCPU, offsetof(struct thread_struct, kvm_shadow_vcpu));
130#endif
ffe129ec 131#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
d30f6e48
SW		 132 DEFINE(THREAD_KVM_VCPU, offsetof(struct thread_struct, kvm_vcpu));
133#endif
d1dead5c 134
2468dcf6
IM		 135#ifdef CONFIG_PPC_BOOK3S_64
136 DEFINE(THREAD_TAR, offsetof(struct thread_struct, tar));
9353374b
ME		 137 DEFINE(THREAD_BESCR, offsetof(struct thread_struct, bescr));
138 DEFINE(THREAD_EBBHR, offsetof(struct thread_struct, ebbhr));
139 DEFINE(THREAD_EBBRR, offsetof(struct thread_struct, ebbrr));
59affcd3
ME		 140 DEFINE(THREAD_SIAR, offsetof(struct thread_struct, siar));
141 DEFINE(THREAD_SDAR, offsetof(struct thread_struct, sdar));
142 DEFINE(THREAD_SIER, offsetof(struct thread_struct, sier));
143 DEFINE(THREAD_MMCR0, offsetof(struct thread_struct, mmcr0));
144 DEFINE(THREAD_MMCR2, offsetof(struct thread_struct, mmcr2));
2468dcf6 145#endif
8b3c34cf 146#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
afc07701 147 DEFINE(PACATMSCRATCH, offsetof(struct paca_struct, tm_scratch));
8b3c34cf
MN		 148 DEFINE(THREAD_TM_TFHAR, offsetof(struct thread_struct, tm_tfhar));
149 DEFINE(THREAD_TM_TEXASR, offsetof(struct thread_struct, tm_texasr));
150 DEFINE(THREAD_TM_TFIAR, offsetof(struct thread_struct, tm_tfiar));
28e61cc4
MN		 151 DEFINE(THREAD_TM_TAR, offsetof(struct thread_struct, tm_tar));
152 DEFINE(THREAD_TM_PPR, offsetof(struct thread_struct, tm_ppr));
153 DEFINE(THREAD_TM_DSCR, offsetof(struct thread_struct, tm_dscr));
8b3c34cf 154 DEFINE(PT_CKPT_REGS, offsetof(struct thread_struct, ckpt_regs));
de79f7b9
PM		 155 DEFINE(THREAD_TRANSACT_VRSTATE, offsetof(struct thread_struct,
156 transact_vr));
8b3c34cf
MN		 157 DEFINE(THREAD_TRANSACT_VRSAVE, offsetof(struct thread_struct,
158 transact_vrsave));
de79f7b9
PM		 159 DEFINE(THREAD_TRANSACT_FPSTATE, offsetof(struct thread_struct,
160 transact_fp));
8b3c34cf
MN		 161 /* Local pt_regs on stack for Transactional Memory funcs. */
162 DEFINE(TM_FRAME_SIZE, STACK_FRAME_OVERHEAD +
163 sizeof(struct pt_regs) + 16);
164#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
2468dcf6 165
d1dead5c 166 DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
f39224a8 167 DEFINE(TI_LOCAL_FLAGS, offsetof(struct thread_info, local_flags));
d1dead5c 168 DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count));
d1dead5c 169 DEFINE(TI_TASK, offsetof(struct thread_info, task));
d1dead5c 170 DEFINE(TI_CPU, offsetof(struct thread_info, cpu));
d1dead5c
SR		 171
172#ifdef CONFIG_PPC64
173 DEFINE(DCACHEL1LINESIZE, offsetof(struct ppc64_caches, dline_size));
174 DEFINE(DCACHEL1LOGLINESIZE, offsetof(struct ppc64_caches, log_dline_size));
175 DEFINE(DCACHEL1LINESPERPAGE, offsetof(struct ppc64_caches, dlines_per_page));
176 DEFINE(ICACHEL1LINESIZE, offsetof(struct ppc64_caches, iline_size));
177 DEFINE(ICACHEL1LOGLINESIZE, offsetof(struct ppc64_caches, log_iline_size));
178 DEFINE(ICACHEL1LINESPERPAGE, offsetof(struct ppc64_caches, ilines_per_page));
d1dead5c
SR		 179 /* paca */
180 DEFINE(PACA_SIZE, sizeof(struct paca_struct));
9e368f29 181 DEFINE(PACA_LOCK_TOKEN, offsetof(struct paca_struct, lock_token));
d1dead5c
SR		 182 DEFINE(PACAPACAINDEX, offsetof(struct paca_struct, paca_index));
183 DEFINE(PACAPROCSTART, offsetof(struct paca_struct, cpu_start));
184 DEFINE(PACAKSAVE, offsetof(struct paca_struct, kstack));
185 DEFINE(PACACURRENT, offsetof(struct paca_struct, __current));
186 DEFINE(PACASAVEDMSR, offsetof(struct paca_struct, saved_msr));
d1dead5c
SR		 187 DEFINE(PACASTABRR, offsetof(struct paca_struct, stab_rr));
188 DEFINE(PACAR1, offsetof(struct paca_struct, saved_r1));
189 DEFINE(PACATOC, offsetof(struct paca_struct, kernel_toc));
1f6a93e4
PM		 190 DEFINE(PACAKBASE, offsetof(struct paca_struct, kernelbase));
191 DEFINE(PACAKMSR, offsetof(struct paca_struct, kernel_msr));
d04c56f7 192 DEFINE(PACASOFTIRQEN, offsetof(struct paca_struct, soft_enabled));
7230c564 193 DEFINE(PACAIRQHAPPENED, offsetof(struct paca_struct, irq_happened));
c395465d 194#ifdef CONFIG_PPC_BOOK3S
2fc251a8 195 DEFINE(PACACONTEXTID, offsetof(struct paca_struct, mm_ctx_id));
d0f13e3c
BH		 196#ifdef CONFIG_PPC_MM_SLICES
197 DEFINE(PACALOWSLICESPSIZE, offsetof(struct paca_struct,
2fc251a8 198 mm_ctx_low_slices_psize));
d0f13e3c 199 DEFINE(PACAHIGHSLICEPSIZE, offsetof(struct paca_struct,
2fc251a8 200 mm_ctx_high_slices_psize));
d0f13e3c 201 DEFINE(MMUPSIZEDEFSIZE, sizeof(struct mmu_psize_def));
91c60b5b 202#endif /* CONFIG_PPC_MM_SLICES */
c395465d 203#endif
dce6670a
BH		 204
205#ifdef CONFIG_PPC_BOOK3E
206 DEFINE(PACAPGD, offsetof(struct paca_struct, pgd));
207 DEFINE(PACA_KERNELPGD, offsetof(struct paca_struct, kernel_pgd));
208 DEFINE(PACA_EXGEN, offsetof(struct paca_struct, exgen));
209 DEFINE(PACA_EXTLB, offsetof(struct paca_struct, extlb));
210 DEFINE(PACA_EXMC, offsetof(struct paca_struct, exmc));
211 DEFINE(PACA_EXCRIT, offsetof(struct paca_struct, excrit));
212 DEFINE(PACA_EXDBG, offsetof(struct paca_struct, exdbg));
213 DEFINE(PACA_MC_STACK, offsetof(struct paca_struct, mc_kstack));
214 DEFINE(PACA_CRIT_STACK, offsetof(struct paca_struct, crit_kstack));
215 DEFINE(PACA_DBG_STACK, offsetof(struct paca_struct, dbg_kstack));
28efc35f
SW		 216 DEFINE(PACA_TCD_PTR, offsetof(struct paca_struct, tcd_ptr));
217
218 DEFINE(TCD_ESEL_NEXT,
219 offsetof(struct tlb_core_data, esel_next));
220 DEFINE(TCD_ESEL_MAX,
221 offsetof(struct tlb_core_data, esel_max));
222 DEFINE(TCD_ESEL_FIRST,
223 offsetof(struct tlb_core_data, esel_first));
dce6670a
BH		 224#endif /* CONFIG_PPC_BOOK3E */
225
91c60b5b 226#ifdef CONFIG_PPC_STD_MMU_64
91c60b5b
BH		 227 DEFINE(PACASLBCACHE, offsetof(struct paca_struct, slb_cache));
228 DEFINE(PACASLBCACHEPTR, offsetof(struct paca_struct, slb_cache_ptr));
229 DEFINE(PACAVMALLOCSLLP, offsetof(struct paca_struct, vmalloc_sllp));
230#ifdef CONFIG_PPC_MM_SLICES
d0f13e3c
BH		 231 DEFINE(MMUPSIZESLLP, offsetof(struct mmu_psize_def, sllp));
232#else
2fc251a8 233 DEFINE(PACACONTEXTSLLP, offsetof(struct paca_struct, mm_ctx_sllp));
d0f13e3c 234#endif /* CONFIG_PPC_MM_SLICES */
d1dead5c
SR		 235 DEFINE(PACA_EXGEN, offsetof(struct paca_struct, exgen));
236 DEFINE(PACA_EXMC, offsetof(struct paca_struct, exmc));
237 DEFINE(PACA_EXSLB, offsetof(struct paca_struct, exslb));
3356bb9f 238 DEFINE(PACALPPACAPTR, offsetof(struct paca_struct, lppaca_ptr));
2f6093c8 239 DEFINE(PACA_SLBSHADOWPTR, offsetof(struct paca_struct, slb_shadow_ptr));
11a27ad7
MN		 240 DEFINE(SLBSHADOW_STACKVSID,
241 offsetof(struct slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid));
242 DEFINE(SLBSHADOW_STACKESID,
243 offsetof(struct slb_shadow, save_area[SLB_NUM_BOLTED - 1].esid));
cf9efce0 244 DEFINE(SLBSHADOW_SAVEAREA, offsetof(struct slb_shadow, save_area));
de56a948 245 DEFINE(LPPACA_PMCINUSE, offsetof(struct lppaca, pmcregs_in_use));
cf9efce0 246 DEFINE(LPPACA_DTLIDX, offsetof(struct lppaca, dtl_idx));
a8606e20 247 DEFINE(LPPACA_YIELDCOUNT, offsetof(struct lppaca, yield_count));
cf9efce0 248 DEFINE(PACA_DTL_RIDX, offsetof(struct paca_struct, dtl_ridx));
91c60b5b
BH		 249#endif /* CONFIG_PPC_STD_MMU_64 */
250 DEFINE(PACAEMERGSP, offsetof(struct paca_struct, emergency_sp));
1e9b4507
MS		 251#ifdef CONFIG_PPC_BOOK3S_64
252 DEFINE(PACAMCEMERGSP, offsetof(struct paca_struct, mc_emergency_sp));
253 DEFINE(PACA_IN_MCE, offsetof(struct paca_struct, in_mce));
254#endif
91c60b5b 255 DEFINE(PACAHWCPUID, offsetof(struct paca_struct, hw_cpu_id));
1fc711f7 256 DEFINE(PACAKEXECSTATE, offsetof(struct paca_struct, kexec_state));
1db36525 257 DEFINE(PACA_DSCR_DEFAULT, offsetof(struct paca_struct, dscr_default));
cf9efce0
PM		 258 DEFINE(PACA_STARTTIME, offsetof(struct paca_struct, starttime));
259 DEFINE(PACA_STARTTIME_USER, offsetof(struct paca_struct, starttime_user));
91c60b5b
BH		 260 DEFINE(PACA_USER_TIME, offsetof(struct paca_struct, user_time));
261 DEFINE(PACA_SYSTEM_TIME, offsetof(struct paca_struct, system_time));
91c60b5b 262 DEFINE(PACA_TRAP_SAVE, offsetof(struct paca_struct, trap_save));
2fde6d20 263 DEFINE(PACA_NAPSTATELOST, offsetof(struct paca_struct, nap_state_lost));
9d378dfa 264 DEFINE(PACA_SPRG_VDSO, offsetof(struct paca_struct, sprg_vdso));
033ef338 265#endif /* CONFIG_PPC64 */
d1dead5c
SR		 266
267 /* RTAS */
268 DEFINE(RTASBASE, offsetof(struct rtas_t, base));
269 DEFINE(RTASENTRY, offsetof(struct rtas_t, entry));
d1dead5c 270
14cf11af 271 /* Interrupt register frame */
91120cc8 272 DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE);
14cf11af 273 DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs));
218d169c 274#ifdef CONFIG_PPC64
d1dead5c
SR		 275 /* Create extra stack space for SRR0 and SRR1 when calling prom/rtas. */
276 DEFINE(PROM_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs) + 16);
277 DEFINE(RTAS_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs) + 16);
57852a85
MK		 278
279 /* hcall statistics */
280 DEFINE(HCALL_STAT_SIZE, sizeof(struct hcall_stats));
281 DEFINE(HCALL_STAT_CALLS, offsetof(struct hcall_stats, num_calls));
282 DEFINE(HCALL_STAT_TB, offsetof(struct hcall_stats, tb_total));
283 DEFINE(HCALL_STAT_PURR, offsetof(struct hcall_stats, purr_total));
d1dead5c 284#endif /* CONFIG_PPC64 */
14cf11af
PM		 285 DEFINE(GPR0, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[0]));
286 DEFINE(GPR1, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[1]));
287 DEFINE(GPR2, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[2]));
288 DEFINE(GPR3, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[3]));
289 DEFINE(GPR4, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[4]));
290 DEFINE(GPR5, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[5]));
291 DEFINE(GPR6, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[6]));
292 DEFINE(GPR7, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[7]));
293 DEFINE(GPR8, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[8]));
294 DEFINE(GPR9, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[9]));
295 DEFINE(GPR10, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[10]));
296 DEFINE(GPR11, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[11]));
297 DEFINE(GPR12, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[12]));
298 DEFINE(GPR13, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[13]));
d1dead5c 299#ifndef CONFIG_PPC64
14cf11af
PM		 300 DEFINE(GPR14, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[14]));
301 DEFINE(GPR15, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[15]));
302 DEFINE(GPR16, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[16]));
303 DEFINE(GPR17, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[17]));
304 DEFINE(GPR18, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[18]));
305 DEFINE(GPR19, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[19]));
306 DEFINE(GPR20, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[20]));
307 DEFINE(GPR21, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[21]));
308 DEFINE(GPR22, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[22]));
309 DEFINE(GPR23, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[23]));
310 DEFINE(GPR24, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[24]));
311 DEFINE(GPR25, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[25]));
312 DEFINE(GPR26, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[26]));
313 DEFINE(GPR27, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[27]));
314 DEFINE(GPR28, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[28]));
315 DEFINE(GPR29, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[29]));
316 DEFINE(GPR30, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[30]));
317 DEFINE(GPR31, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[31]));
d1dead5c 318#endif /* CONFIG_PPC64 */
14cf11af
PM		 319 /*
320 * Note: these symbols include _ because they overlap with special
321 * register names
322 */
323 DEFINE(_NIP, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, nip));
324 DEFINE(_MSR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, msr));
325 DEFINE(_CTR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, ctr));
326 DEFINE(_LINK, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, link));
327 DEFINE(_CCR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, ccr));
14cf11af
PM		 328 DEFINE(_XER, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, xer));
329 DEFINE(_DAR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dar));
330 DEFINE(_DSISR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dsisr));
d1dead5c
SR		 331 DEFINE(ORIG_GPR3, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, orig_gpr3));
332 DEFINE(RESULT, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, result));
d73e0c99 333 DEFINE(_TRAP, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, trap));
d1dead5c
SR		 334#ifndef CONFIG_PPC64
335 DEFINE(_MQ, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, mq));
336 /*
337 * The PowerPC 400-class & Book-E processors have neither the DAR
338 * nor the DSISR SPRs. Hence, we overload them to hold the similar
339 * DEAR and ESR SPRs for such processors. For critical interrupts
340 * we use them to hold SRR0 and SRR1.
14cf11af
PM		 341 */
342 DEFINE(_DEAR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dar));
343 DEFINE(_ESR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dsisr));
d1dead5c 344#else /* CONFIG_PPC64 */
d1dead5c
SR		 345 DEFINE(SOFTE, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, softe));
346
347 /* These _only_ to be used with {PROM,RTAS}_FRAME_SIZE!!! */
348 DEFINE(_SRR0, STACK_FRAME_OVERHEAD+sizeof(struct pt_regs));
349 DEFINE(_SRR1, STACK_FRAME_OVERHEAD+sizeof(struct pt_regs)+8);
350#endif /* CONFIG_PPC64 */
351
57e2a99f 352#if defined(CONFIG_PPC32)
fca622c5
KG		 353#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
354 DEFINE(EXC_LVL_SIZE, STACK_EXC_LVL_FRAME_SIZE);
355 DEFINE(MAS0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
356 /* we overload MMUCR for 44x on MAS0 since they are mutually exclusive */
357 DEFINE(MMUCR, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
358 DEFINE(MAS1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas1));
359 DEFINE(MAS2, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas2));
360 DEFINE(MAS3, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas3));
361 DEFINE(MAS6, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas6));
362 DEFINE(MAS7, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas7));
363 DEFINE(_SRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr0));
364 DEFINE(_SRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr1));
365 DEFINE(_CSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr0));
366 DEFINE(_CSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr1));
367 DEFINE(_DSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr0));
368 DEFINE(_DSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr1));
369 DEFINE(SAVED_KSP_LIMIT, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, saved_ksp_limit));
370#endif
57e2a99f 371#endif
14cf11af
PM		 372 DEFINE(CLONE_VM, CLONE_VM);
373 DEFINE(CLONE_UNTRACED, CLONE_UNTRACED);
d1dead5c
SR		 374
375#ifndef CONFIG_PPC64
14cf11af 376 DEFINE(MM_PGD, offsetof(struct mm_struct, pgd));
d1dead5c 377#endif /* ! CONFIG_PPC64 */
14cf11af
PM		 378
379 /* About the CPU features table */
14cf11af
PM		 380 DEFINE(CPU_SPEC_FEATURES, offsetof(struct cpu_spec, cpu_features));
381 DEFINE(CPU_SPEC_SETUP, offsetof(struct cpu_spec, cpu_setup));
f39b7a55 382 DEFINE(CPU_SPEC_RESTORE, offsetof(struct cpu_spec, cpu_restore));
e7affb1d 383 DEFINE(CPU_DOWN_FLUSH, offsetof(struct cpu_spec, cpu_down_flush));
14cf11af 384
d1dead5c
SR		 385 DEFINE(pbe_address, offsetof(struct pbe, address));
386 DEFINE(pbe_orig_address, offsetof(struct pbe, orig_address));
387 DEFINE(pbe_next, offsetof(struct pbe, next));
14cf11af 388
543b9fd3 389#ifndef CONFIG_PPC64
fd582ec8 390 DEFINE(TASK_SIZE, TASK_SIZE);
d1dead5c 391 DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>28);
a7f290da 392#endif /* ! CONFIG_PPC64 */
14cf11af 393
a7f290da
BH		 394 /* datapage offsets for use by vdso */
395 DEFINE(CFG_TB_ORIG_STAMP, offsetof(struct vdso_data, tb_orig_stamp));
396 DEFINE(CFG_TB_TICKS_PER_SEC, offsetof(struct vdso_data, tb_ticks_per_sec));
397 DEFINE(CFG_TB_TO_XS, offsetof(struct vdso_data, tb_to_xs));
398 DEFINE(CFG_STAMP_XSEC, offsetof(struct vdso_data, stamp_xsec));
399 DEFINE(CFG_TB_UPDATE_COUNT, offsetof(struct vdso_data, tb_update_count));
400 DEFINE(CFG_TZ_MINUTEWEST, offsetof(struct vdso_data, tz_minuteswest));
401 DEFINE(CFG_TZ_DSTTIME, offsetof(struct vdso_data, tz_dsttime));
402 DEFINE(CFG_SYSCALL_MAP32, offsetof(struct vdso_data, syscall_map_32));
403 DEFINE(WTOM_CLOCK_SEC, offsetof(struct vdso_data, wtom_clock_sec));
404 DEFINE(WTOM_CLOCK_NSEC, offsetof(struct vdso_data, wtom_clock_nsec));
597bc5c0 405 DEFINE(STAMP_XTIME, offsetof(struct vdso_data, stamp_xtime));
8fd63a9e 406 DEFINE(STAMP_SEC_FRAC, offsetof(struct vdso_data, stamp_sec_fraction));
fbe48175
OJ		 407 DEFINE(CFG_ICACHE_BLOCKSZ, offsetof(struct vdso_data, icache_block_size));
408 DEFINE(CFG_DCACHE_BLOCKSZ, offsetof(struct vdso_data, dcache_block_size));
409 DEFINE(CFG_ICACHE_LOGBLOCKSZ, offsetof(struct vdso_data, icache_log_block_size));
410 DEFINE(CFG_DCACHE_LOGBLOCKSZ, offsetof(struct vdso_data, dcache_log_block_size));
a7f290da
BH		 411#ifdef CONFIG_PPC64
412 DEFINE(CFG_SYSCALL_MAP64, offsetof(struct vdso_data, syscall_map_64));
14cf11af
PM		 413 DEFINE(TVAL64_TV_SEC, offsetof(struct timeval, tv_sec));
414 DEFINE(TVAL64_TV_USEC, offsetof(struct timeval, tv_usec));
415 DEFINE(TVAL32_TV_SEC, offsetof(struct compat_timeval, tv_sec));
416 DEFINE(TVAL32_TV_USEC, offsetof(struct compat_timeval, tv_usec));
0c37ec2a
BH		 417 DEFINE(TSPC64_TV_SEC, offsetof(struct timespec, tv_sec));
418 DEFINE(TSPC64_TV_NSEC, offsetof(struct timespec, tv_nsec));
a7f290da
BH		 419 DEFINE(TSPC32_TV_SEC, offsetof(struct compat_timespec, tv_sec));
420 DEFINE(TSPC32_TV_NSEC, offsetof(struct compat_timespec, tv_nsec));
421#else
422 DEFINE(TVAL32_TV_SEC, offsetof(struct timeval, tv_sec));
423 DEFINE(TVAL32_TV_USEC, offsetof(struct timeval, tv_usec));
0c37ec2a
BH		 424 DEFINE(TSPC32_TV_SEC, offsetof(struct timespec, tv_sec));
425 DEFINE(TSPC32_TV_NSEC, offsetof(struct timespec, tv_nsec));
a7f290da
BH		 426#endif
427 /* timeval/timezone offsets for use by vdso */
14cf11af
PM		 428 DEFINE(TZONE_TZ_MINWEST, offsetof(struct timezone, tz_minuteswest));
429 DEFINE(TZONE_TZ_DSTTIME, offsetof(struct timezone, tz_dsttime));
a7f290da
BH		 430
431 /* Other bits used by the vdso */
432 DEFINE(CLOCK_REALTIME, CLOCK_REALTIME);
433 DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC);
434 DEFINE(NSEC_PER_SEC, NSEC_PER_SEC);
151db1fc 435 DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
a7f290da 436
007d88d0
DW		 437#ifdef CONFIG_BUG
438 DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry));
439#endif
16a15a30 440
dd1842a2
AK		 441#ifdef MAX_PGD_TABLE_SIZE
442 DEFINE(PGD_TABLE_SIZE, MAX_PGD_TABLE_SIZE);
443#else
ee7a76da 444 DEFINE(PGD_TABLE_SIZE, PGD_TABLE_SIZE);
dd1842a2 445#endif
4ee7084e 446 DEFINE(PTE_SIZE, sizeof(pte_t));
bee86f14 447
bbf45ba5 448#ifdef CONFIG_KVM
bbf45ba5
HB		 449 DEFINE(VCPU_HOST_STACK, offsetof(struct kvm_vcpu, arch.host_stack));
450 DEFINE(VCPU_HOST_PID, offsetof(struct kvm_vcpu, arch.host_pid));
d30f6e48 451 DEFINE(VCPU_GUEST_PID, offsetof(struct kvm_vcpu, arch.pid));
bbf45ba5 452 DEFINE(VCPU_GPRS, offsetof(struct kvm_vcpu, arch.gpr));
eab17672 453 DEFINE(VCPU_VRSAVE, offsetof(struct kvm_vcpu, arch.vrsave));
efff1912 454 DEFINE(VCPU_FPRS, offsetof(struct kvm_vcpu, arch.fp.fpr));
de56a948 455#ifdef CONFIG_ALTIVEC
efff1912 456 DEFINE(VCPU_VRS, offsetof(struct kvm_vcpu, arch.vr.vr));
de56a948
PM		 457#endif
458 DEFINE(VCPU_XER, offsetof(struct kvm_vcpu, arch.xer));
459 DEFINE(VCPU_CTR, offsetof(struct kvm_vcpu, arch.ctr));
460 DEFINE(VCPU_LR, offsetof(struct kvm_vcpu, arch.lr));
e14e7a1e 461#ifdef CONFIG_PPC_BOOK3S
b005255e 462 DEFINE(VCPU_TAR, offsetof(struct kvm_vcpu, arch.tar));
e14e7a1e 463#endif
de56a948
PM		 464 DEFINE(VCPU_CR, offsetof(struct kvm_vcpu, arch.cr));
465 DEFINE(VCPU_PC, offsetof(struct kvm_vcpu, arch.pc));
9975f5e3 466#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
de56a948
PM		 467 DEFINE(VCPU_MSR, offsetof(struct kvm_vcpu, arch.shregs.msr));
468 DEFINE(VCPU_SRR0, offsetof(struct kvm_vcpu, arch.shregs.srr0));
469 DEFINE(VCPU_SRR1, offsetof(struct kvm_vcpu, arch.shregs.srr1));
470 DEFINE(VCPU_SPRG0, offsetof(struct kvm_vcpu, arch.shregs.sprg0));
471 DEFINE(VCPU_SPRG1, offsetof(struct kvm_vcpu, arch.shregs.sprg1));
472 DEFINE(VCPU_SPRG2, offsetof(struct kvm_vcpu, arch.shregs.sprg2));
473 DEFINE(VCPU_SPRG3, offsetof(struct kvm_vcpu, arch.shregs.sprg3));
b6c295df
PM		 474#endif
475#ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
476 DEFINE(VCPU_TB_RMENTRY, offsetof(struct kvm_vcpu, arch.rm_entry));
477 DEFINE(VCPU_TB_RMINTR, offsetof(struct kvm_vcpu, arch.rm_intr));
478 DEFINE(VCPU_TB_RMEXIT, offsetof(struct kvm_vcpu, arch.rm_exit));
479 DEFINE(VCPU_TB_GUEST, offsetof(struct kvm_vcpu, arch.guest_time));
480 DEFINE(VCPU_TB_CEDE, offsetof(struct kvm_vcpu, arch.cede_time));
481 DEFINE(VCPU_CUR_ACTIVITY, offsetof(struct kvm_vcpu, arch.cur_activity));
482 DEFINE(VCPU_ACTIVITY_START, offsetof(struct kvm_vcpu, arch.cur_tb_start));
483 DEFINE(TAS_SEQCOUNT, offsetof(struct kvmhv_tb_accumulator, seqcount));
484 DEFINE(TAS_TOTAL, offsetof(struct kvmhv_tb_accumulator, tb_total));
485 DEFINE(TAS_MIN, offsetof(struct kvmhv_tb_accumulator, tb_min));
486 DEFINE(TAS_MAX, offsetof(struct kvmhv_tb_accumulator, tb_max));
de56a948 487#endif
c8ae0ace 488 DEFINE(VCPU_SHARED_SPRG3, offsetof(struct kvm_vcpu_arch_shared, sprg3));
b5904972
SW		 489 DEFINE(VCPU_SHARED_SPRG4, offsetof(struct kvm_vcpu_arch_shared, sprg4));
490 DEFINE(VCPU_SHARED_SPRG5, offsetof(struct kvm_vcpu_arch_shared, sprg5));
491 DEFINE(VCPU_SHARED_SPRG6, offsetof(struct kvm_vcpu_arch_shared, sprg6));
492 DEFINE(VCPU_SHARED_SPRG7, offsetof(struct kvm_vcpu_arch_shared, sprg7));
49dd2c49 493 DEFINE(VCPU_SHADOW_PID, offsetof(struct kvm_vcpu, arch.shadow_pid));
dd9ebf1f 494 DEFINE(VCPU_SHADOW_PID1, offsetof(struct kvm_vcpu, arch.shadow_pid1));
96bc451a 495 DEFINE(VCPU_SHARED, offsetof(struct kvm_vcpu, arch.shared));
666e7252 496 DEFINE(VCPU_SHARED_MSR, offsetof(struct kvm_vcpu_arch_shared, msr));
ecee273f 497 DEFINE(VCPU_SHADOW_MSR, offsetof(struct kvm_vcpu, arch.shadow_msr));
5deb8e7a
AG		 498#if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_KVM_BOOK3S_PR_POSSIBLE)
499 DEFINE(VCPU_SHAREDBE, offsetof(struct kvm_vcpu, arch.shared_big_endian));
500#endif
bbf45ba5 501
b5904972
SW		 502 DEFINE(VCPU_SHARED_MAS0, offsetof(struct kvm_vcpu_arch_shared, mas0));
503 DEFINE(VCPU_SHARED_MAS1, offsetof(struct kvm_vcpu_arch_shared, mas1));
504 DEFINE(VCPU_SHARED_MAS2, offsetof(struct kvm_vcpu_arch_shared, mas2));
505 DEFINE(VCPU_SHARED_MAS7_3, offsetof(struct kvm_vcpu_arch_shared, mas7_3));
506 DEFINE(VCPU_SHARED_MAS4, offsetof(struct kvm_vcpu_arch_shared, mas4));
507 DEFINE(VCPU_SHARED_MAS6, offsetof(struct kvm_vcpu_arch_shared, mas6));
508
d30f6e48
SW		 509 DEFINE(VCPU_KVM, offsetof(struct kvm_vcpu, kvm));
510 DEFINE(KVM_LPID, offsetof(struct kvm, arch.lpid));
511
00c3a37c 512 /* book3s */
9975f5e3 513#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
de56a948
PM		 514 DEFINE(KVM_SDR1, offsetof(struct kvm, arch.sdr1));
515 DEFINE(KVM_HOST_LPID, offsetof(struct kvm, arch.host_lpid));
516 DEFINE(KVM_HOST_LPCR, offsetof(struct kvm, arch.host_lpcr));
517 DEFINE(KVM_HOST_SDR1, offsetof(struct kvm, arch.host_sdr1));
1b400ba0 518 DEFINE(KVM_NEED_FLUSH, offsetof(struct kvm, arch.need_tlb_flush.bits));
699a0ea0 519 DEFINE(KVM_ENABLED_HCALLS, offsetof(struct kvm, arch.enabled_hcalls));
aa04b4cc 520 DEFINE(KVM_LPCR, offsetof(struct kvm, arch.lpcr));
697d3899 521 DEFINE(KVM_VRMA_SLB_V, offsetof(struct kvm, arch.vrma_slb_v));
de56a948
PM		 522 DEFINE(VCPU_DSISR, offsetof(struct kvm_vcpu, arch.shregs.dsisr));
523 DEFINE(VCPU_DAR, offsetof(struct kvm_vcpu, arch.shregs.dar));
7657f408 524 DEFINE(VCPU_VPA, offsetof(struct kvm_vcpu, arch.vpa.pinned_addr));
c35635ef 525 DEFINE(VCPU_VPA_DIRTY, offsetof(struct kvm_vcpu, arch.vpa.dirty));
4a157d61 526 DEFINE(VCPU_HEIR, offsetof(struct kvm_vcpu, arch.emul_inst));
ec257165
PM		 527 DEFINE(VCPU_CPU, offsetof(struct kvm_vcpu, cpu));
528 DEFINE(VCPU_THREAD_CPU, offsetof(struct kvm_vcpu, arch.thread_cpu));
de56a948 529#endif
00c3a37c 530#ifdef CONFIG_PPC_BOOK3S
de56a948 531 DEFINE(VCPU_VCPUID, offsetof(struct kvm_vcpu, vcpu_id));
de56a948
PM		 532 DEFINE(VCPU_PURR, offsetof(struct kvm_vcpu, arch.purr));
533 DEFINE(VCPU_SPURR, offsetof(struct kvm_vcpu, arch.spurr));
b005255e
MN		 534 DEFINE(VCPU_IC, offsetof(struct kvm_vcpu, arch.ic));
535 DEFINE(VCPU_VTB, offsetof(struct kvm_vcpu, arch.vtb));
de56a948
PM		 536 DEFINE(VCPU_DSCR, offsetof(struct kvm_vcpu, arch.dscr));
537 DEFINE(VCPU_AMR, offsetof(struct kvm_vcpu, arch.amr));
538 DEFINE(VCPU_UAMOR, offsetof(struct kvm_vcpu, arch.uamor));
b005255e 539 DEFINE(VCPU_IAMR, offsetof(struct kvm_vcpu, arch.iamr));
de56a948
PM		 540 DEFINE(VCPU_CTRL, offsetof(struct kvm_vcpu, arch.ctrl));
541 DEFINE(VCPU_DABR, offsetof(struct kvm_vcpu, arch.dabr));
8563bf52 542 DEFINE(VCPU_DABRX, offsetof(struct kvm_vcpu, arch.dabrx));
b005255e
MN		 543 DEFINE(VCPU_DAWR, offsetof(struct kvm_vcpu, arch.dawr));
544 DEFINE(VCPU_DAWRX, offsetof(struct kvm_vcpu, arch.dawrx));
545 DEFINE(VCPU_CIABR, offsetof(struct kvm_vcpu, arch.ciabr));
62908905 546 DEFINE(VCPU_HFLAGS, offsetof(struct kvm_vcpu, arch.hflags));
de56a948
PM		 547 DEFINE(VCPU_DEC, offsetof(struct kvm_vcpu, arch.dec));
548 DEFINE(VCPU_DEC_EXPIRES, offsetof(struct kvm_vcpu, arch.dec_expires));
aa04b4cc 549 DEFINE(VCPU_PENDING_EXC, offsetof(struct kvm_vcpu, arch.pending_exceptions));
19ccb76a
PM		 550 DEFINE(VCPU_CEDED, offsetof(struct kvm_vcpu, arch.ceded));
551 DEFINE(VCPU_PRODDED, offsetof(struct kvm_vcpu, arch.prodded));
de56a948
PM		 552 DEFINE(VCPU_MMCR, offsetof(struct kvm_vcpu, arch.mmcr));
553 DEFINE(VCPU_PMC, offsetof(struct kvm_vcpu, arch.pmc));
b005255e 554 DEFINE(VCPU_SPMC, offsetof(struct kvm_vcpu, arch.spmc));
14941789
PM		 555 DEFINE(VCPU_SIAR, offsetof(struct kvm_vcpu, arch.siar));
556 DEFINE(VCPU_SDAR, offsetof(struct kvm_vcpu, arch.sdar));
b005255e 557 DEFINE(VCPU_SIER, offsetof(struct kvm_vcpu, arch.sier));
de56a948
PM		 558 DEFINE(VCPU_SLB, offsetof(struct kvm_vcpu, arch.slb));
559 DEFINE(VCPU_SLB_MAX, offsetof(struct kvm_vcpu, arch.slb_max));
560 DEFINE(VCPU_SLB_NR, offsetof(struct kvm_vcpu, arch.slb_nr));
de56a948
PM		 561 DEFINE(VCPU_FAULT_DSISR, offsetof(struct kvm_vcpu, arch.fault_dsisr));
562 DEFINE(VCPU_FAULT_DAR, offsetof(struct kvm_vcpu, arch.fault_dar));
e5ee5422 563 DEFINE(VCPU_INTR_MSR, offsetof(struct kvm_vcpu, arch.intr_msr));
de56a948
PM		 564 DEFINE(VCPU_LAST_INST, offsetof(struct kvm_vcpu, arch.last_inst));
565 DEFINE(VCPU_TRAP, offsetof(struct kvm_vcpu, arch.trap));
0acb9111 566 DEFINE(VCPU_CFAR, offsetof(struct kvm_vcpu, arch.cfar));
4b8473c9 567 DEFINE(VCPU_PPR, offsetof(struct kvm_vcpu, arch.ppr));
b005255e 568 DEFINE(VCPU_FSCR, offsetof(struct kvm_vcpu, arch.fscr));
616dff86 569 DEFINE(VCPU_SHADOW_FSCR, offsetof(struct kvm_vcpu, arch.shadow_fscr));
b005255e 570 DEFINE(VCPU_PSPB, offsetof(struct kvm_vcpu, arch.pspb));
b005255e
MN		 571 DEFINE(VCPU_EBBHR, offsetof(struct kvm_vcpu, arch.ebbhr));
572 DEFINE(VCPU_EBBRR, offsetof(struct kvm_vcpu, arch.ebbrr));
573 DEFINE(VCPU_BESCR, offsetof(struct kvm_vcpu, arch.bescr));
574 DEFINE(VCPU_CSIGR, offsetof(struct kvm_vcpu, arch.csigr));
575 DEFINE(VCPU_TACR, offsetof(struct kvm_vcpu, arch.tacr));
576 DEFINE(VCPU_TCSCR, offsetof(struct kvm_vcpu, arch.tcscr));
577 DEFINE(VCPU_ACOP, offsetof(struct kvm_vcpu, arch.acop));
578 DEFINE(VCPU_WORT, offsetof(struct kvm_vcpu, arch.wort));
a2d56020 579 DEFINE(VCPU_SHADOW_SRR1, offsetof(struct kvm_vcpu, arch.shadow_srr1));
7d6c40da 580 DEFINE(VCORE_ENTRY_EXIT, offsetof(struct kvmppc_vcore, entry_exit_map));
371fefd6 581 DEFINE(VCORE_IN_GUEST, offsetof(struct kvmppc_vcore, in_guest));
19ccb76a 582 DEFINE(VCORE_NAPPING_THREADS, offsetof(struct kvmppc_vcore, napping_threads));
e0b7ec05 583 DEFINE(VCORE_KVM, offsetof(struct kvmppc_vcore, kvm));
93b0f4dc 584 DEFINE(VCORE_TB_OFFSET, offsetof(struct kvmppc_vcore, tb_offset));
a0144e2a 585 DEFINE(VCORE_LPCR, offsetof(struct kvmppc_vcore, lpcr));
388cc6e1 586 DEFINE(VCORE_PCR, offsetof(struct kvmppc_vcore, pcr));
b005255e 587 DEFINE(VCORE_DPDES, offsetof(struct kvmppc_vcore, dpdes));
de56a948
PM		 588 DEFINE(VCPU_SLB_E, offsetof(struct kvmppc_slb, orige));
589 DEFINE(VCPU_SLB_V, offsetof(struct kvmppc_slb, origv));
590 DEFINE(VCPU_SLB_SIZE, sizeof(struct kvmppc_slb));
7b490411
MN		 591#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
592 DEFINE(VCPU_TFHAR, offsetof(struct kvm_vcpu, arch.tfhar));
593 DEFINE(VCPU_TFIAR, offsetof(struct kvm_vcpu, arch.tfiar));
594 DEFINE(VCPU_TEXASR, offsetof(struct kvm_vcpu, arch.texasr));
595 DEFINE(VCPU_GPR_TM, offsetof(struct kvm_vcpu, arch.gpr_tm));
596 DEFINE(VCPU_FPRS_TM, offsetof(struct kvm_vcpu, arch.fp_tm.fpr));
597 DEFINE(VCPU_VRS_TM, offsetof(struct kvm_vcpu, arch.vr_tm.vr));
598 DEFINE(VCPU_VRSAVE_TM, offsetof(struct kvm_vcpu, arch.vrsave_tm));
599 DEFINE(VCPU_CR_TM, offsetof(struct kvm_vcpu, arch.cr_tm));
600 DEFINE(VCPU_LR_TM, offsetof(struct kvm_vcpu, arch.lr_tm));
601 DEFINE(VCPU_CTR_TM, offsetof(struct kvm_vcpu, arch.ctr_tm));
602 DEFINE(VCPU_AMR_TM, offsetof(struct kvm_vcpu, arch.amr_tm));
603 DEFINE(VCPU_PPR_TM, offsetof(struct kvm_vcpu, arch.ppr_tm));
604 DEFINE(VCPU_DSCR_TM, offsetof(struct kvm_vcpu, arch.dscr_tm));
605 DEFINE(VCPU_TAR_TM, offsetof(struct kvm_vcpu, arch.tar_tm));
606#endif
3c42bf8a
PM		 607
608#ifdef CONFIG_PPC_BOOK3S_64
7aa79938 609#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
a2d56020 610 DEFINE(PACA_SVCPU, offsetof(struct paca_struct, shadow_vcpu));
3c42bf8a 611# define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, shadow_vcpu.f))
de56a948
PM		 612#else
613# define SVCPU_FIELD(x, f)
614#endif
3c42bf8a
PM		 615# define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, kvm_hstate.f))
616#else /* 32-bit */
617# define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, f))
618# define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, hstate.f))
619#endif
620
621 SVCPU_FIELD(SVCPU_CR, cr);
622 SVCPU_FIELD(SVCPU_XER, xer);
623 SVCPU_FIELD(SVCPU_CTR, ctr);
624 SVCPU_FIELD(SVCPU_LR, lr);
625 SVCPU_FIELD(SVCPU_PC, pc);
626 SVCPU_FIELD(SVCPU_R0, gpr[0]);
627 SVCPU_FIELD(SVCPU_R1, gpr[1]);
628 SVCPU_FIELD(SVCPU_R2, gpr[2]);
629 SVCPU_FIELD(SVCPU_R3, gpr[3]);
630 SVCPU_FIELD(SVCPU_R4, gpr[4]);
631 SVCPU_FIELD(SVCPU_R5, gpr[5]);
632 SVCPU_FIELD(SVCPU_R6, gpr[6]);
633 SVCPU_FIELD(SVCPU_R7, gpr[7]);
634 SVCPU_FIELD(SVCPU_R8, gpr[8]);
635 SVCPU_FIELD(SVCPU_R9, gpr[9]);
636 SVCPU_FIELD(SVCPU_R10, gpr[10]);
637 SVCPU_FIELD(SVCPU_R11, gpr[11]);
638 SVCPU_FIELD(SVCPU_R12, gpr[12]);
639 SVCPU_FIELD(SVCPU_R13, gpr[13]);
640 SVCPU_FIELD(SVCPU_FAULT_DSISR, fault_dsisr);
641 SVCPU_FIELD(SVCPU_FAULT_DAR, fault_dar);
642 SVCPU_FIELD(SVCPU_LAST_INST, last_inst);
643 SVCPU_FIELD(SVCPU_SHADOW_SRR1, shadow_srr1);
0604675f 644#ifdef CONFIG_PPC_BOOK3S_32
3c42bf8a 645 SVCPU_FIELD(SVCPU_SR, sr);
0604675f 646#endif
3c42bf8a
PM		 647#ifdef CONFIG_PPC64
648 SVCPU_FIELD(SVCPU_SLB, slb);
649 SVCPU_FIELD(SVCPU_SLB_MAX, slb_max);
616dff86 650 SVCPU_FIELD(SVCPU_SHADOW_FSCR, shadow_fscr);
3c42bf8a
PM		 651#endif
652
653 HSTATE_FIELD(HSTATE_HOST_R1, host_r1);
654 HSTATE_FIELD(HSTATE_HOST_R2, host_r2);
de56a948 655 HSTATE_FIELD(HSTATE_HOST_MSR, host_msr);
3c42bf8a
PM		 656 HSTATE_FIELD(HSTATE_VMHANDLER, vmhandler);
657 HSTATE_FIELD(HSTATE_SCRATCH0, scratch0);
658 HSTATE_FIELD(HSTATE_SCRATCH1, scratch1);
36e7bb38 659 HSTATE_FIELD(HSTATE_SCRATCH2, scratch2);
3c42bf8a 660 HSTATE_FIELD(HSTATE_IN_GUEST, in_guest);
02143947 661 HSTATE_FIELD(HSTATE_RESTORE_HID5, restore_hid5);
19ccb76a 662 HSTATE_FIELD(HSTATE_NAPPING, napping);
3c42bf8a 663
9975f5e3 664#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
7657f408
PM		 665 HSTATE_FIELD(HSTATE_HWTHREAD_REQ, hwthread_req);
666 HSTATE_FIELD(HSTATE_HWTHREAD_STATE, hwthread_state);
de56a948 667 HSTATE_FIELD(HSTATE_KVM_VCPU, kvm_vcpu);
371fefd6
PM		 668 HSTATE_FIELD(HSTATE_KVM_VCORE, kvm_vcore);
669 HSTATE_FIELD(HSTATE_XICS_PHYS, xics_phys);
54695c30
BH		 670 HSTATE_FIELD(HSTATE_SAVED_XIRR, saved_xirr);
671 HSTATE_FIELD(HSTATE_HOST_IPI, host_ipi);
e0b7ec05 672 HSTATE_FIELD(HSTATE_PTID, ptid);
9a4fc4ea
ME		 673 HSTATE_FIELD(HSTATE_MMCR0, host_mmcr[0]);
674 HSTATE_FIELD(HSTATE_MMCR1, host_mmcr[1]);
675 HSTATE_FIELD(HSTATE_MMCRA, host_mmcr[2]);
676 HSTATE_FIELD(HSTATE_SIAR, host_mmcr[3]);
677 HSTATE_FIELD(HSTATE_SDAR, host_mmcr[4]);
678 HSTATE_FIELD(HSTATE_MMCR2, host_mmcr[5]);
679 HSTATE_FIELD(HSTATE_SIER, host_mmcr[6]);
680 HSTATE_FIELD(HSTATE_PMC1, host_pmc[0]);
681 HSTATE_FIELD(HSTATE_PMC2, host_pmc[1]);
682 HSTATE_FIELD(HSTATE_PMC3, host_pmc[2]);
683 HSTATE_FIELD(HSTATE_PMC4, host_pmc[3]);
684 HSTATE_FIELD(HSTATE_PMC5, host_pmc[4]);
685 HSTATE_FIELD(HSTATE_PMC6, host_pmc[5]);
de56a948
PM		 686 HSTATE_FIELD(HSTATE_PURR, host_purr);
687 HSTATE_FIELD(HSTATE_SPURR, host_spurr);
688 HSTATE_FIELD(HSTATE_DSCR, host_dscr);
689 HSTATE_FIELD(HSTATE_DABR, dabr);
690 HSTATE_FIELD(HSTATE_DECEXP, dec_expires);
b4deba5c 691 HSTATE_FIELD(HSTATE_SPLIT_MODE, kvm_split_mode);
19ccb76a 692 DEFINE(IPI_PRIORITY, IPI_PRIORITY);
b4deba5c
PM		 693 DEFINE(KVM_SPLIT_RPR, offsetof(struct kvm_split_mode, rpr));
694 DEFINE(KVM_SPLIT_PMMAR, offsetof(struct kvm_split_mode, pmmar));
695 DEFINE(KVM_SPLIT_LDBAR, offsetof(struct kvm_split_mode, ldbar));
696 DEFINE(KVM_SPLIT_SIZE, offsetof(struct kvm_split_mode, subcore_size));
697 DEFINE(KVM_SPLIT_DO_NAP, offsetof(struct kvm_split_mode, do_nap));
698 DEFINE(KVM_SPLIT_NAPPED, offsetof(struct kvm_split_mode, napped));
9975f5e3 699#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
de56a948 700
0acb9111
PM		 701#ifdef CONFIG_PPC_BOOK3S_64
702 HSTATE_FIELD(HSTATE_CFAR, cfar);
4b8473c9 703 HSTATE_FIELD(HSTATE_PPR, ppr);
616dff86 704 HSTATE_FIELD(HSTATE_HOST_FSCR, host_fscr);
0acb9111
PM		 705#endif /* CONFIG_PPC_BOOK3S_64 */
706
3c42bf8a 707#else /* CONFIG_PPC_BOOK3S */
7e57cba0
AG		 708 DEFINE(VCPU_CR, offsetof(struct kvm_vcpu, arch.cr));
709 DEFINE(VCPU_XER, offsetof(struct kvm_vcpu, arch.xer));
0604675f
AG		 710 DEFINE(VCPU_LR, offsetof(struct kvm_vcpu, arch.lr));
711 DEFINE(VCPU_CTR, offsetof(struct kvm_vcpu, arch.ctr));
712 DEFINE(VCPU_PC, offsetof(struct kvm_vcpu, arch.pc));
99e99d19 713 DEFINE(VCPU_SPRG9, offsetof(struct kvm_vcpu, arch.sprg9));
0604675f
AG		 714 DEFINE(VCPU_LAST_INST, offsetof(struct kvm_vcpu, arch.last_inst));
715 DEFINE(VCPU_FAULT_DEAR, offsetof(struct kvm_vcpu, arch.fault_dear));
716 DEFINE(VCPU_FAULT_ESR, offsetof(struct kvm_vcpu, arch.fault_esr));
15b708be 717 DEFINE(VCPU_CRIT_SAVE, offsetof(struct kvm_vcpu, arch.crit_save));
00c3a37c 718#endif /* CONFIG_PPC_BOOK3S */
3c42bf8a 719#endif /* CONFIG_KVM */
d17051cb
AG		 720
721#ifdef CONFIG_KVM_GUEST
722 DEFINE(KVM_MAGIC_SCRATCH1, offsetof(struct kvm_vcpu_arch_shared,
723 scratch1));
724 DEFINE(KVM_MAGIC_SCRATCH2, offsetof(struct kvm_vcpu_arch_shared,
725 scratch2));
726 DEFINE(KVM_MAGIC_SCRATCH3, offsetof(struct kvm_vcpu_arch_shared,
727 scratch3));
728 DEFINE(KVM_MAGIC_INT, offsetof(struct kvm_vcpu_arch_shared,
729 int_pending));
730 DEFINE(KVM_MAGIC_MSR, offsetof(struct kvm_vcpu_arch_shared, msr));
731 DEFINE(KVM_MAGIC_CRITICAL, offsetof(struct kvm_vcpu_arch_shared,
732 critical));
cbe487fa 733 DEFINE(KVM_MAGIC_SR, offsetof(struct kvm_vcpu_arch_shared, sr));
d17051cb
AG		 734#endif
735
ca9153a3
IY		 736#ifdef CONFIG_44x
737 DEFINE(PGD_T_LOG2, PGD_T_LOG2);
738 DEFINE(PTE_T_LOG2, PTE_T_LOG2);
739#endif
55fd766b 740#ifdef CONFIG_PPC_FSL_BOOK3E
78f62237
KG		 741 DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));
742 DEFINE(TLBCAM_MAS0, offsetof(struct tlbcam, MAS0));
743 DEFINE(TLBCAM_MAS1, offsetof(struct tlbcam, MAS1));
744 DEFINE(TLBCAM_MAS2, offsetof(struct tlbcam, MAS2));
745 DEFINE(TLBCAM_MAS3, offsetof(struct tlbcam, MAS3));
746 DEFINE(TLBCAM_MAS7, offsetof(struct tlbcam, MAS7));
747#endif
bbf45ba5 748
4cd35f67
SW		 749#if defined(CONFIG_KVM) && defined(CONFIG_SPE)
750 DEFINE(VCPU_EVR, offsetof(struct kvm_vcpu, arch.evr[0]));
751 DEFINE(VCPU_ACC, offsetof(struct kvm_vcpu, arch.acc));
752 DEFINE(VCPU_SPEFSCR, offsetof(struct kvm_vcpu, arch.spefscr));
753 DEFINE(VCPU_HOST_SPEFSCR, offsetof(struct kvm_vcpu, arch.host_spefscr));
754#endif
755
d30f6e48
SW		 756#ifdef CONFIG_KVM_BOOKE_HV
757 DEFINE(VCPU_HOST_MAS4, offsetof(struct kvm_vcpu, arch.host_mas4));
758 DEFINE(VCPU_HOST_MAS6, offsetof(struct kvm_vcpu, arch.host_mas6));
759 DEFINE(VCPU_EPLC, offsetof(struct kvm_vcpu, arch.eplc));
760#endif
761
73e75b41
HB		 762#ifdef CONFIG_KVM_EXIT_TIMING
763 DEFINE(VCPU_TIMING_EXIT_TBU, offsetof(struct kvm_vcpu,
764 arch.timing_exit.tv32.tbu));
765 DEFINE(VCPU_TIMING_EXIT_TBL, offsetof(struct kvm_vcpu,
766 arch.timing_exit.tv32.tbl));
767 DEFINE(VCPU_TIMING_LAST_ENTER_TBU, offsetof(struct kvm_vcpu,
768 arch.timing_last_enter.tv32.tbu));
769 DEFINE(VCPU_TIMING_LAST_ENTER_TBL, offsetof(struct kvm_vcpu,
770 arch.timing_last_enter.tv32.tbl));
771#endif
772
7cba160a
SP		 773#ifdef CONFIG_PPC_POWERNV
774 DEFINE(PACA_CORE_IDLE_STATE_PTR,
775 offsetof(struct paca_struct, core_idle_state_ptr));
776 DEFINE(PACA_THREAD_IDLE_STATE,
777 offsetof(struct paca_struct, thread_idle_state));
778 DEFINE(PACA_THREAD_MASK,
779 offsetof(struct paca_struct, thread_mask));
77b54e9f
SP		 780 DEFINE(PACA_SUBCORE_SIBLING_MASK,
781 offsetof(struct paca_struct, subcore_sibling_mask));
7cba160a
SP		 782#endif
783
66feed61
PM		 784 DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SERVER);
785
14cf11af
PM		 786 return 0;
787}
Linux kernel - Deliverables
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