Commit | Line | Data |
---|---|---|
84e3ad5b VB |
1 | /* |
2 | * This file contains low level CPU setup functions. | |
3 | * Valentine Barshak <vbarshak@ru.mvista.com> | |
4 | * MontaVista Software, Inc (c) 2007 | |
5 | * | |
464076a4 | 6 | * Based on cpu_setup_6xx code by |
84e3ad5b VB |
7 | * Benjamin Herrenschmidt <benh@kernel.crashing.org> |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <asm/processor.h> | |
17 | #include <asm/cputable.h> | |
18 | #include <asm/ppc_asm.h> | |
19 | ||
8112753b VB |
20 | _GLOBAL(__setup_cpu_440ep) |
21 | b __init_fpu_44x | |
22 | _GLOBAL(__setup_cpu_440epx) | |
340ffd26 VB |
23 | mflr r4 |
24 | bl __init_fpu_44x | |
25 | bl __plb_disable_wrp | |
47c0bd1a | 26 | bl __fixup_440A_mcheck |
340ffd26 VB |
27 | mtlr r4 |
28 | blr | |
29 | _GLOBAL(__setup_cpu_440grx) | |
9ac30c31 JB |
30 | mflr r4 |
31 | bl __plb_disable_wrp | |
32 | bl __fixup_440A_mcheck | |
33 | mtlr r4 | |
34 | blr | |
464076a4 | 35 | _GLOBAL(__setup_cpu_460ex) |
939e622c | 36 | _GLOBAL(__setup_cpu_460gt) |
6c712090 | 37 | _GLOBAL(__setup_cpu_460sx) |
6612d9b0 BH |
38 | mflr r4 |
39 | bl __init_fpu_44x | |
40 | bl __fixup_440A_mcheck | |
41 | mtlr r4 | |
42 | blr | |
43 | ||
640d17d6 | 44 | _GLOBAL(__setup_cpu_440x5) |
47c0bd1a BH |
45 | _GLOBAL(__setup_cpu_440gx) |
46 | _GLOBAL(__setup_cpu_440spe) | |
47 | b __fixup_440A_mcheck | |
340ffd26 | 48 | |
8112753b VB |
49 | /* enable APU between CPU and FPU */ |
50 | _GLOBAL(__init_fpu_44x) | |
51 | mfspr r3,SPRN_CCR0 | |
52 | /* Clear DAPUIB flag in CCR0 */ | |
53 | rlwinm r3,r3,0,12,10 | |
54 | mtspr SPRN_CCR0,r3 | |
55 | isync | |
56 | blr | |
57 | ||
340ffd26 VB |
58 | /* |
59 | * Workaround for the incorrect write to DDR SDRAM errata. | |
60 | * The write address can be corrupted during writes to | |
61 | * DDR SDRAM when write pipelining is enabled on PLB0. | |
62 | * Disable write pipelining here. | |
63 | */ | |
64 | #define DCRN_PLB4A0_ACR 0x81 | |
65 | ||
66 | _GLOBAL(__plb_disable_wrp) | |
67 | mfdcr r3,DCRN_PLB4A0_ACR | |
68 | /* clear WRP bit in PLB4A0_ACR */ | |
69 | rlwinm r3,r3,0,8,6 | |
70 | mtdcr DCRN_PLB4A0_ACR,r3 | |
71 | isync | |
72 | blr | |
73 |