projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 84e3ad5b VB |
1 | /* |
| 2 | * This file contains low level CPU setup functions. | |
| 3 | * Valentine Barshak <vbarshak@ru.mvista.com> | |
| 4 | * MontaVista Software, Inc (c) 2007 | |
| 5 | * | |
| 464076a4 | 6 | * Based on cpu_setup_6xx code by |
| 84e3ad5b VB |
7 | * Benjamin Herrenschmidt <benh@kernel.crashing.org> |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or | |
| 10 | * modify it under the terms of the GNU General Public License | |
| 11 | * as published by the Free Software Foundation; either version | |
| 12 | * 2 of the License, or (at your option) any later version. | |
| 13 | * | |
| 14 | */ | |
| 15 | ||
| 16 | #include <asm/processor.h> | |
| 17 | #include <asm/cputable.h> | |
| 18 | #include <asm/ppc_asm.h> | |
| 19 | ||
| 8112753b VB |
20 | _GLOBAL(__setup_cpu_440ep) |
| 21 | b __init_fpu_44x | |
| 22 | _GLOBAL(__setup_cpu_440epx) | |
| 340ffd26 VB |
23 | mflr r4 |
| 24 | bl __init_fpu_44x | |
| 25 | bl __plb_disable_wrp | |
| 47c0bd1a | 26 | bl __fixup_440A_mcheck |
| 340ffd26 VB |
27 | mtlr r4 |
| 28 | blr | |
| 29 | _GLOBAL(__setup_cpu_440grx) | |
| 9ac30c31 JB |
30 | mflr r4 |
| 31 | bl __plb_disable_wrp | |
| 32 | bl __fixup_440A_mcheck | |
| 33 | mtlr r4 | |
| 34 | blr | |
| 464076a4 | 35 | _GLOBAL(__setup_cpu_460ex) |
| 939e622c | 36 | _GLOBAL(__setup_cpu_460gt) |
| 464076a4 | 37 | b __init_fpu_44x |
| 47c0bd1a BH |
38 | _GLOBAL(__setup_cpu_440gx) |
| 39 | _GLOBAL(__setup_cpu_440spe) | |
| 40 | b __fixup_440A_mcheck | |
| 340ffd26 | 41 | |
| 8112753b VB |
42 | /* enable APU between CPU and FPU */ |
| 43 | _GLOBAL(__init_fpu_44x) | |
| 44 | mfspr r3,SPRN_CCR0 | |
| 45 | /* Clear DAPUIB flag in CCR0 */ | |
| 46 | rlwinm r3,r3,0,12,10 | |
| 47 | mtspr SPRN_CCR0,r3 | |
| 48 | isync | |
| 49 | blr | |
| 50 | ||
| 340ffd26 VB |
51 | /* |
| 52 | * Workaround for the incorrect write to DDR SDRAM errata. | |
| 53 | * The write address can be corrupted during writes to | |
| 54 | * DDR SDRAM when write pipelining is enabled on PLB0. | |
| 55 | * Disable write pipelining here. | |
| 56 | */ | |
| 57 | #define DCRN_PLB4A0_ACR 0x81 | |
| 58 | ||
| 59 | _GLOBAL(__plb_disable_wrp) | |
| 60 | mfdcr r3,DCRN_PLB4A0_ACR | |
| 61 | /* clear WRP bit in PLB4A0_ACR */ | |
| 62 | rlwinm r3,r3,0,8,6 | |
| 63 | mtdcr DCRN_PLB4A0_ACR,r3 | |
| 64 | isync | |
| 65 | blr | |
| 66 |