projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 105c31df KG |
1 | /* |
| 2 | * This file contains low level CPU setup functions. | |
| 3 | * Kumar Gala <galak@kernel.crashing.org> | |
| 4 | * Copyright 2009 Freescale Semiconductor, Inc. | |
| 5 | * | |
| 6 | * Based on cpu_setup_6xx code by | |
| 7 | * Benjamin Herrenschmidt <benh@kernel.crashing.org> | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or | |
| 10 | * modify it under the terms of the GNU General Public License | |
| 11 | * as published by the Free Software Foundation; either version | |
| 12 | * 2 of the License, or (at your option) any later version. | |
| 13 | * | |
| 14 | */ | |
| 15 | ||
| 16 | #include <asm/processor.h> | |
| 17 | #include <asm/cputable.h> | |
| 18 | #include <asm/ppc_asm.h> | |
| 19 | ||
| cab888e6 NC |
20 | _GLOBAL(__e500_icache_setup) |
| 21 | mfspr r0, SPRN_L1CSR1 | |
| 22 | andi. r3, r0, L1CSR1_ICE | |
| 23 | bnelr /* Already enabled */ | |
| 24 | oris r0, r0, L1CSR1_CPE@h | |
| 25 | ori r0, r0, (L1CSR1_ICFI | L1CSR1_ICLFR | L1CSR1_ICE) | |
| 26 | mtspr SPRN_L1CSR1, r0 /* Enable I-Cache */ | |
| 27 | isync | |
| 28 | blr | |
| 29 | ||
| 30 | _GLOBAL(__e500_dcache_setup) | |
| 31 | mfspr r0, SPRN_L1CSR0 | |
| 32 | andi. r3, r0, L1CSR0_DCE | |
| 33 | bnelr /* Already enabled */ | |
| 34 | msync | |
| 35 | isync | |
| 36 | li r0, 0 | |
| 37 | mtspr SPRN_L1CSR0, r0 /* Disable */ | |
| 38 | msync | |
| 39 | isync | |
| 40 | li r0, (L1CSR0_DCFI | L1CSR0_CLFC) | |
| 41 | mtspr SPRN_L1CSR0, r0 /* Invalidate */ | |
| 42 | isync | |
| 43 | 1: mfspr r0, SPRN_L1CSR0 | |
| 44 | andi. r3, r0, L1CSR0_CLFC | |
| 45 | bne+ 1b /* Wait for lock bits reset */ | |
| 46 | oris r0, r0, L1CSR0_CPE@h | |
| 47 | ori r0, r0, L1CSR0_DCE | |
| 48 | msync | |
| 49 | isync | |
| 50 | mtspr SPRN_L1CSR0, r0 /* Enable */ | |
| 51 | isync | |
| 52 | blr | |
| 53 | ||
| 4490c06b | 54 | #ifdef CONFIG_PPC32 |
| 105c31df KG |
55 | _GLOBAL(__setup_cpu_e200) |
| 56 | /* enable dedicated debug exception handling resources (Debug APU) */ | |
| 57 | mfspr r3,SPRN_HID0 | |
| 58 | ori r3,r3,HID0_DAPUEN@l | |
| 59 | mtspr SPRN_HID0,r3 | |
| 60 | b __setup_e200_ivors | |
| 61 | _GLOBAL(__setup_cpu_e500v1) | |
| 62 | _GLOBAL(__setup_cpu_e500v2) | |
| cab888e6 NC |
63 | mflr r4 |
| 64 | bl __e500_icache_setup | |
| 65 | bl __e500_dcache_setup | |
| 66 | bl __setup_e500_ivors | |
| 388b78ad | 67 | #ifdef CONFIG_FSL_RIO |
| b5fb0cc7 SX |
68 | /* Ensure that RFXE is set */ |
| 69 | mfspr r3,SPRN_HID1 | |
| 70 | oris r3,r3,HID1_RFXE@h | |
| 71 | mtspr SPRN_HID1,r3 | |
| 72 | #endif | |
| cab888e6 NC |
73 | mtlr r4 |
| 74 | blr | |
| 105c31df | 75 | _GLOBAL(__setup_cpu_e500mc) |
| cab888e6 NC |
76 | mflr r4 |
| 77 | bl __e500_icache_setup | |
| 78 | bl __e500_dcache_setup | |
| 79 | bl __setup_e500mc_ivors | |
| 80 | mtlr r4 | |
| 81 | blr | |
| 4490c06b KG |
82 | #endif |
| 83 | /* Right now, restore and setup are the same thing */ | |
| 84 | _GLOBAL(__restore_cpu_e5500) | |
| 85 | _GLOBAL(__setup_cpu_e5500) | |
| 86 | mflr r4 | |
| 87 | bl __e500_icache_setup | |
| 88 | bl __e500_dcache_setup | |
| 89 | #ifdef CONFIG_PPC_BOOK3E_64 | |
| 90 | bl .__setup_base_ivors | |
| 3a6e9bd7 SW |
91 | bl .setup_perfmon_ivor |
| 92 | bl .setup_doorbell_ivors | |
| 93 | bl .setup_ehv_ivors | |
| 4490c06b KG |
94 | #else |
| 95 | bl __setup_e500mc_ivors | |
| 96 | #endif | |
| 97 | mtlr r4 | |
| 98 | blr |