projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 24cc67de BH |
1 | /* |
| 2 | * This file contains low level CPU setup functions. | |
| 3 | * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org) | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or | |
| 6 | * modify it under the terms of the GNU General Public License | |
| 7 | * as published by the Free Software Foundation; either version | |
| 8 | * 2 of the License, or (at your option) any later version. | |
| 9 | * | |
| 10 | */ | |
| 11 | ||
| 12 | #include <asm/processor.h> | |
| 13 | #include <asm/page.h> | |
| 14 | #include <asm/cputable.h> | |
| 15 | #include <asm/ppc_asm.h> | |
| 16 | #include <asm/asm-offsets.h> | |
| 17 | #include <asm/cache.h> | |
| 18 | ||
| 19 | /* Entry: r3 = crap, r4 = ptr to cputable entry | |
| 20 | * | |
| 21 | * Note that we can be called twice for pseudo-PVRs | |
| 22 | */ | |
| 23 | _GLOBAL(__setup_cpu_power7) | |
| 24 | mflr r11 | |
| 25 | bl __init_hvmode_206 | |
| 26 | mtlr r11 | |
| 27 | beqlr | |
| b144871c BH |
28 | li r0,0 |
| 29 | mtspr SPRN_LPID,r0 | |
| f7c32c24 | 30 | mfspr r3,SPRN_LPCR |
| 24cc67de | 31 | bl __init_LPCR |
| b144871c | 32 | bl __init_TLB |
| 24cc67de BH |
33 | mtlr r11 |
| 34 | blr | |
| 35 | ||
| 36 | _GLOBAL(__restore_cpu_power7) | |
| 37 | mflr r11 | |
| 38 | mfmsr r3 | |
| 39 | rldicl. r0,r3,4,63 | |
| 40 | beqlr | |
| b144871c BH |
41 | li r0,0 |
| 42 | mtspr SPRN_LPID,r0 | |
| f7c32c24 | 43 | mfspr r3,SPRN_LPCR |
| 24cc67de | 44 | bl __init_LPCR |
| aec937b1 MN |
45 | bl __init_TLB |
| 46 | mtlr r11 | |
| 47 | blr | |
| 48 | ||
| 49 | _GLOBAL(__setup_cpu_power8) | |
| 50 | mflr r11 | |
| 51 | bl __init_hvmode_206 | |
| 52 | mtlr r11 | |
| 53 | beqlr | |
| 54 | li r0,0 | |
| 55 | mtspr SPRN_LPID,r0 | |
| f7c32c24 | 56 | mfspr r3,SPRN_LPCR |
| b0302722 | 57 | oris r3, r3, LPCR_AIL_3@h |
| aec937b1 | 58 | bl __init_LPCR |
| 2468dcf6 | 59 | bl __init_FSCR |
| aec937b1 MN |
60 | bl __init_TLB |
| 61 | mtlr r11 | |
| 62 | blr | |
| 63 | ||
| 64 | _GLOBAL(__restore_cpu_power8) | |
| 65 | mflr r11 | |
| 66 | mfmsr r3 | |
| 67 | rldicl. r0,r3,4,63 | |
| 68 | beqlr | |
| 69 | li r0,0 | |
| 70 | mtspr SPRN_LPID,r0 | |
| f7c32c24 | 71 | mfspr r3,SPRN_LPCR |
| b0302722 | 72 | oris r3, r3, LPCR_AIL_3@h |
| aec937b1 | 73 | bl __init_LPCR |
| b144871c | 74 | bl __init_TLB |
| 24cc67de BH |
75 | mtlr r11 |
| 76 | blr | |
| 77 | ||
| 78 | __init_hvmode_206: | |
| 969391c5 | 79 | /* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */ |
| 24cc67de BH |
80 | mfmsr r3 |
| 81 | rldicl. r0,r3,4,63 | |
| 82 | bnelr | |
| 83 | ld r5,CPU_SPEC_FEATURES(r4) | |
| 969391c5 | 84 | LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE) |
| 24cc67de BH |
85 | xor r5,r5,r6 |
| 86 | std r5,CPU_SPEC_FEATURES(r4) | |
| 87 | blr | |
| 88 | ||
| 89 | __init_LPCR: | |
| 90 | /* Setup a sane LPCR: | |
| f7c32c24 | 91 | * Called with initial LPCR in R3 |
| 24cc67de | 92 | * |
| a5d4f3ad | 93 | * LPES = 0b01 (HSRR0/1 used for 0x500) |
| 24cc67de | 94 | * PECE = 0b111 |
| 895796a8 | 95 | * DPFD = 4 |
| 923c53ca PM |
96 | * HDICE = 0 |
| 97 | * VC = 0b100 (VPM0=1, VPM1=0, ISL=0) | |
| 98 | * VRMASD = 0b10000 (L=1, LP=00) | |
| 24cc67de BH |
99 | * |
| 100 | * Other bits untouched for now | |
| 101 | */ | |
| 923c53ca PM |
102 | li r5,1 |
| 103 | rldimi r3,r5, LPCR_LPES_SH, 64-LPCR_LPES_SH-2 | |
| 24cc67de | 104 | ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2) |
| 895796a8 | 105 | li r5,4 |
| 923c53ca PM |
106 | rldimi r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3 |
| 107 | clrrdi r3,r3,1 /* clear HDICE */ | |
| 108 | li r5,4 | |
| 109 | rldimi r3,r5, LPCR_VC_SH, 0 | |
| 110 | li r5,0x10 | |
| 111 | rldimi r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5 | |
| 24cc67de BH |
112 | mtspr SPRN_LPCR,r3 |
| 113 | isync | |
| 114 | blr | |
| b144871c | 115 | |
| 2468dcf6 IM |
116 | __init_FSCR: |
| 117 | mfspr r3,SPRN_FSCR | |
| 118 | ori r3,r3,FSCR_TAR | |
| 119 | mtspr SPRN_FSCR,r3 | |
| 120 | blr | |
| 121 | ||
| b144871c BH |
122 | __init_TLB: |
| 123 | /* Clear the TLB */ | |
| 124 | li r6,128 | |
| 125 | mtctr r6 | |
| 126 | li r7,0xc00 /* IS field = 0b11 */ | |
| 127 | ptesync | |
| 128 | 2: tlbiel r7 | |
| 129 | addi r7,r7,0x1000 | |
| 130 | bdnz 2b | |
| 131 | ptesync | |
| 132 | 1: blr |