[deliverable/linux.git] / arch / powerpc / kernel / eeh_cache.c

/*
 * PCI address cache; allows the lookup of PCI devices based on I/O address
 *
 * Copyright IBM Corporation 2004
 * Copyright Linas Vepstas <linas@austin.ibm.com> 2004
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */

#include <linux/list.h>
#include <linux/pci.h>
#include <linux/rbtree.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/atomic.h>
#include <asm/pci-bridge.h>
#include <asm/ppc-pci.h>


/**
 * The pci address cache subsystem.  This subsystem places
 * PCI device address resources into a red-black tree, sorted
 * according to the address range, so that given only an i/o
 * address, the corresponding PCI device can be **quickly**
 * found. It is safe to perform an address lookup in an interrupt
 * context; this ability is an important feature.
 *
 * Currently, the only customer of this code is the EEH subsystem;
 * thus, this code has been somewhat tailored to suit EEH better.
 * In particular, the cache does *not* hold the addresses of devices
 * for which EEH is not enabled.
 *
 * (Implementation Note: The RB tree seems to be better/faster
 * than any hash algo I could think of for this problem, even
 * with the penalty of slow pointer chases for d-cache misses).
 */
struct pci_io_addr_range {
	struct rb_node rb_node;
	resource_size_t addr_lo;
	resource_size_t addr_hi;
	struct eeh_dev *edev;
	struct pci_dev *pcidev;
	unsigned long flags;
};

static struct pci_io_addr_cache {
	struct rb_root rb_root;
	spinlock_t piar_lock;
} pci_io_addr_cache_root;

static inline struct eeh_dev *__eeh_addr_cache_get_device(unsigned long addr)
{
	struct rb_node *n = pci_io_addr_cache_root.rb_root.rb_node;

	while (n) {
		struct pci_io_addr_range *piar;
		piar = rb_entry(n, struct pci_io_addr_range, rb_node);

		if (addr < piar->addr_lo)
			n = n->rb_left;
		else if (addr > piar->addr_hi)
			n = n->rb_right;
		else
			return piar->edev;
	}

	return NULL;
}

/**
 * eeh_addr_cache_get_dev - Get device, given only address
 * @addr: mmio (PIO) phys address or i/o port number
 *
 * Given an mmio phys address, or a port number, find a pci device
 * that implements this address.  Be sure to pci_dev_put the device
 * when finished.  I/O port numbers are assumed to be offset
 * from zero (that is, they do *not* have pci_io_addr added in).
 * It is safe to call this function within an interrupt.
 */
struct eeh_dev *eeh_addr_cache_get_dev(unsigned long addr)
{
	struct eeh_dev *edev;
	unsigned long flags;

	spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
	edev = __eeh_addr_cache_get_device(addr);
	spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
	return edev;
}

#ifdef DEBUG
/*
 * Handy-dandy debug print routine, does nothing more
 * than print out the contents of our addr cache.
 */
static void eeh_addr_cache_print(struct pci_io_addr_cache *cache)
{
	struct rb_node *n;
	int cnt = 0;

	n = rb_first(&cache->rb_root);
	while (n) {
		struct pci_io_addr_range *piar;
		piar = rb_entry(n, struct pci_io_addr_range, rb_node);
		pr_debug("PCI: %s addr range %d [%lx-%lx]: %s\n",
		       (piar->flags & IORESOURCE_IO) ? "i/o" : "mem", cnt,
		       piar->addr_lo, piar->addr_hi, pci_name(piar->pcidev));
		cnt++;
		n = rb_next(n);
	}
}
#endif

/* Insert address range into the rb tree. */
static struct pci_io_addr_range *
eeh_addr_cache_insert(struct pci_dev *dev, resource_size_t alo,
		      resource_size_t ahi, unsigned long flags)
{
	struct rb_node **p = &pci_io_addr_cache_root.rb_root.rb_node;
	struct rb_node *parent = NULL;
	struct pci_io_addr_range *piar;

	/* Walk tree, find a place to insert into tree */
	while (*p) {
		parent = *p;
		piar = rb_entry(parent, struct pci_io_addr_range, rb_node);
		if (ahi < piar->addr_lo) {
			p = &parent->rb_left;
		} else if (alo > piar->addr_hi) {
			p = &parent->rb_right;
		} else {
			if (dev != piar->pcidev ||
			    alo != piar->addr_lo || ahi != piar->addr_hi) {
				pr_warn("PIAR: overlapping address range\n");
			}
			return piar;
		}
	}
	piar = kzalloc(sizeof(struct pci_io_addr_range), GFP_ATOMIC);
	if (!piar)
		return NULL;

	piar->addr_lo = alo;
	piar->addr_hi = ahi;
	piar->edev = pci_dev_to_eeh_dev(dev);
	piar->pcidev = dev;
	piar->flags = flags;

#ifdef DEBUG
	pr_debug("PIAR: insert range=[%lx:%lx] dev=%s\n",
	                  alo, ahi, pci_name(dev));
#endif

	rb_link_node(&piar->rb_node, parent, p);
	rb_insert_color(&piar->rb_node, &pci_io_addr_cache_root.rb_root);

	return piar;
}

static void __eeh_addr_cache_insert_dev(struct pci_dev *dev)
{
	struct pci_dn *pdn;
	struct eeh_dev *edev;
	int i;

	pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
	if (!pdn) {
		pr_warn("PCI: no pci dn found for dev=%s\n",
			pci_name(dev));
		return;
	}

	edev = pdn_to_eeh_dev(pdn);
	if (!edev) {
		pr_warn("PCI: no EEH dev found for %s\n",
			pci_name(dev));
		return;
	}

	/* Skip any devices for which EEH is not enabled. */
	if (!edev->pe) {
		dev_dbg(&dev->dev, "EEH: Skip building address cache\n");
		return;
	}

	/* Walk resources on this device, poke them into the tree */
	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
		resource_size_t start = pci_resource_start(dev,i);
		resource_size_t end = pci_resource_end(dev,i);
		unsigned long flags = pci_resource_flags(dev,i);

		/* We are interested only bus addresses, not dma or other stuff */
		if (0 == (flags & (IORESOURCE_IO | IORESOURCE_MEM)))
			continue;
		if (start == 0 || ~start == 0 || end == 0 || ~end == 0)
			 continue;
		eeh_addr_cache_insert(dev, start, end, flags);
	}
}

/**
 * eeh_addr_cache_insert_dev - Add a device to the address cache
 * @dev: PCI device whose I/O addresses we are interested in.
 *
 * In order to support the fast lookup of devices based on addresses,
 * we maintain a cache of devices that can be quickly searched.
 * This routine adds a device to that cache.
 */
void eeh_addr_cache_insert_dev(struct pci_dev *dev)
{
	unsigned long flags;

	/* Ignore PCI bridges */
	if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
		return;

	spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
	__eeh_addr_cache_insert_dev(dev);
	spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
}

static inline void __eeh_addr_cache_rmv_dev(struct pci_dev *dev)
{
	struct rb_node *n;

restart:
	n = rb_first(&pci_io_addr_cache_root.rb_root);
	while (n) {
		struct pci_io_addr_range *piar;
		piar = rb_entry(n, struct pci_io_addr_range, rb_node);

		if (piar->pcidev == dev) {
			rb_erase(n, &pci_io_addr_cache_root.rb_root);
			kfree(piar);
			goto restart;
		}
		n = rb_next(n);
	}
}

/**
 * eeh_addr_cache_rmv_dev - remove pci device from addr cache
 * @dev: device to remove
 *
 * Remove a device from the addr-cache tree.
 * This is potentially expensive, since it will walk
 * the tree multiple times (once per resource).
 * But so what; device removal doesn't need to be that fast.
 */
void eeh_addr_cache_rmv_dev(struct pci_dev *dev)
{
	unsigned long flags;

	spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
	__eeh_addr_cache_rmv_dev(dev);
	spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
}

/**
 * eeh_addr_cache_build - Build a cache of I/O addresses
 *
 * Build a cache of pci i/o addresses.  This cache will be used to
 * find the pci device that corresponds to a given address.
 * This routine scans all pci busses to build the cache.
 * Must be run late in boot process, after the pci controllers
 * have been scanned for devices (after all device resources are known).
 */
void eeh_addr_cache_build(void)
{
	struct pci_dn *pdn;
	struct eeh_dev *edev;
	struct pci_dev *dev = NULL;

	spin_lock_init(&pci_io_addr_cache_root.piar_lock);

	for_each_pci_dev(dev) {
		pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
		if (!pdn)
			continue;

		edev = pdn_to_eeh_dev(pdn);
		if (!edev)
			continue;

		dev->dev.archdata.edev = edev;
		edev->pdev = dev;

		eeh_addr_cache_insert_dev(dev);
		eeh_sysfs_add_device(dev);
	}

#ifdef DEBUG
	/* Verify tree built up above, echo back the list of addrs. */
	eeh_addr_cache_print(&pci_io_addr_cache_root);
#endif
}
Commit	Line	Data
5d5a0936	1	/*
5d5a0936 LV	2	* PCI address cache; allows the lookup of PCI devices based on I/O address
5d5a0936 LV	3	*
3c8c90ab LV	4	* Copyright IBM Corporation 2004
3c8c90ab LV	5	* Copyright Linas Vepstas <linas@austin.ibm.com> 2004
5d5a0936 LV	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21
	22	#include <linux/list.h>
	23	#include <linux/pci.h>
	24	#include <linux/rbtree.h>
5a0e3ad6	25	#include <linux/slab.h>
5d5a0936	26	#include <linux/spinlock.h>
60063497	27	#include <linux/atomic.h>
5d5a0936 LV	28	#include <asm/pci-bridge.h>
5d5a0936 LV	29	#include <asm/ppc-pci.h>
5d5a0936	30
5d5a0936 LV	31
	32	/**
	33	* The pci address cache subsystem. This subsystem places
	34	* PCI device address resources into a red-black tree, sorted
	35	* according to the address range, so that given only an i/o
	36	* address, the corresponding PCI device can be quickly
	37	* found. It is safe to perform an address lookup in an interrupt
	38	* context; this ability is an important feature.
	39	*
	40	* Currently, the only customer of this code is the EEH subsystem;
	41	* thus, this code has been somewhat tailored to suit EEH better.
	42	* In particular, the cache does not hold the addresses of devices
	43	* for which EEH is not enabled.
	44	*
	45	* (Implementation Note: The RB tree seems to be better/faster
	46	* than any hash algo I could think of for this problem, even
	47	* with the penalty of slow pointer chases for d-cache misses).
	48	*/
29f8bf1b	49	struct pci_io_addr_range {
5d5a0936	50	struct rb_node rb_node;
37213529 WY	51	resource_size_t addr_lo;
37213529 WY	52	resource_size_t addr_hi;
f8f7d63f	53	struct eeh_dev *edev;
5d5a0936	54	struct pci_dev *pcidev;
37213529	55	unsigned long flags;
5d5a0936 LV	56	};
5d5a0936 LV	57
29f8bf1b	58	static struct pci_io_addr_cache {
5d5a0936 LV	59	struct rb_root rb_root;
	60	spinlock_t piar_lock;
	61	} pci_io_addr_cache_root;
	62
3ab96a02	63	static inline struct eeh_dev *__eeh_addr_cache_get_device(unsigned long addr)
5d5a0936 LV	64	{
	65	struct rb_node *n = pci_io_addr_cache_root.rb_root.rb_node;
	66
	67	while (n) {
	68	struct pci_io_addr_range *piar;
	69	piar = rb_entry(n, struct pci_io_addr_range, rb_node);
	70
0ba17888	71	if (addr < piar->addr_lo)
5d5a0936	72	n = n->rb_left;
0ba17888 GS	73	else if (addr > piar->addr_hi)
	74	n = n->rb_right;
	75	else
	76	return piar->edev;
5d5a0936 LV	77	}
	78
	79	return NULL;
	80	}
	81
	82	/**
3ab96a02	83	* eeh_addr_cache_get_dev - Get device, given only address
5d5a0936 LV	84	* @addr: mmio (PIO) phys address or i/o port number
	85	*
	86	* Given an mmio phys address, or a port number, find a pci device
	87	* that implements this address. Be sure to pci_dev_put the device
	88	* when finished. I/O port numbers are assumed to be offset
	89	* from zero (that is, they do not have pci_io_addr added in).
	90	* It is safe to call this function within an interrupt.
	91	*/
3ab96a02	92	struct eeh_dev *eeh_addr_cache_get_dev(unsigned long addr)
5d5a0936	93	{
f8f7d63f	94	struct eeh_dev *edev;
5d5a0936 LV	95	unsigned long flags;
	96
	97	spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
3ab96a02	98	edev = __eeh_addr_cache_get_device(addr);
5d5a0936	99	spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
f8f7d63f	100	return edev;
5d5a0936 LV	101	}
	102
	103	#ifdef DEBUG
	104	/*
	105	* Handy-dandy debug print routine, does nothing more
	106	* than print out the contents of our addr cache.
	107	*/
3ab96a02	108	static void eeh_addr_cache_print(struct pci_io_addr_cache *cache)
5d5a0936 LV	109	{
	110	struct rb_node *n;
	111	int cnt = 0;
	112
	113	n = rb_first(&cache->rb_root);
	114	while (n) {
	115	struct pci_io_addr_range *piar;
	116	piar = rb_entry(n, struct pci_io_addr_range, rb_node);
3ab96a02	117	pr_debug("PCI: %s addr range %d [%lx-%lx]: %s\n",
5d5a0936 LV	118	(piar->flags & IORESOURCE_IO) ? "i/o" : "mem", cnt,
	119	piar->addr_lo, piar->addr_hi, pci_name(piar->pcidev));
	120	cnt++;
	121	n = rb_next(n);
	122	}
	123	}
	124	#endif
	125
	126	/* Insert address range into the rb tree. */
	127	static struct pci_io_addr_range *
37213529 WY	128	eeh_addr_cache_insert(struct pci_dev *dev, resource_size_t alo,
37213529 WY	129	resource_size_t ahi, unsigned long flags)
5d5a0936 LV	130	{
	131	struct rb_node **p = &pci_io_addr_cache_root.rb_root.rb_node;
	132	struct rb_node *parent = NULL;
	133	struct pci_io_addr_range *piar;
	134
	135	/* Walk tree, find a place to insert into tree */
	136	while (*p) {
	137	parent = *p;
	138	piar = rb_entry(parent, struct pci_io_addr_range, rb_node);
	139	if (ahi < piar->addr_lo) {
	140	p = &parent->rb_left;
	141	} else if (alo > piar->addr_hi) {
	142	p = &parent->rb_right;
	143	} else {
	144	if (dev != piar->pcidev \|\|
	145	alo != piar->addr_lo \|\| ahi != piar->addr_hi) {
0dae2743	146	pr_warn("PIAR: overlapping address range\n");
5d5a0936 LV	147	}
	148	return piar;
	149	}
	150	}
7e4bbaf0	151	piar = kzalloc(sizeof(struct pci_io_addr_range), GFP_ATOMIC);
5d5a0936 LV	152	if (!piar)
	153	return NULL;
	154
	155	piar->addr_lo = alo;
	156	piar->addr_hi = ahi;
f8f7d63f	157	piar->edev = pci_dev_to_eeh_dev(dev);
5d5a0936 LV	158	piar->pcidev = dev;
	159	piar->flags = flags;
	160
	161	#ifdef DEBUG
3ab96a02	162	pr_debug("PIAR: insert range=[%lx:%lx] dev=%s\n",
29f8bf1b	163	alo, ahi, pci_name(dev));
5d5a0936 LV	164	#endif
	165
	166	rb_link_node(&piar->rb_node, parent, p);
	167	rb_insert_color(&piar->rb_node, &pci_io_addr_cache_root.rb_root);
	168
	169	return piar;
	170	}
	171
3ab96a02	172	static void __eeh_addr_cache_insert_dev(struct pci_dev *dev)
5d5a0936	173	{
c6406d8f	174	struct pci_dn *pdn;
d50a7d4c	175	struct eeh_dev *edev;
5d5a0936	176	int i;
5d5a0936	177
c6406d8f GS	178	pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
c6406d8f GS	179	if (!pdn) {
0dae2743 GS	180	pr_warn("PCI: no pci dn found for dev=%s\n",
0dae2743 GS	181	pci_name(dev));
5d5a0936 LV	182	return;
	183	}
	184
c6406d8f	185	edev = pdn_to_eeh_dev(pdn);
d50a7d4c	186	if (!edev) {
c6406d8f GS	187	pr_warn("PCI: no EEH dev found for %s\n",
c6406d8f GS	188	pci_name(dev));
d50a7d4c GS	189	return;
	190	}
	191
5d5a0936	192	/* Skip any devices for which EEH is not enabled. */
05b1721d	193	if (!edev->pe) {
c6406d8f	194	dev_dbg(&dev->dev, "EEH: Skip building address cache\n");
5d5a0936 LV	195	return;
	196	}
	197
5d5a0936 LV	198	/* Walk resources on this device, poke them into the tree */
5d5a0936 LV	199	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
37213529 WY	200	resource_size_t start = pci_resource_start(dev,i);
	201	resource_size_t end = pci_resource_end(dev,i);
	202	unsigned long flags = pci_resource_flags(dev,i);
5d5a0936 LV	203
	204	/* We are interested only bus addresses, not dma or other stuff */
	205	if (0 == (flags & (IORESOURCE_IO \| IORESOURCE_MEM)))
	206	continue;
	207	if (start == 0 \|\| ~start == 0 \|\| end == 0 \|\| ~end == 0)
	208	continue;
3ab96a02	209	eeh_addr_cache_insert(dev, start, end, flags);
5d5a0936	210	}
5d5a0936 LV	211	}
	212
	213	/**
3ab96a02	214	* eeh_addr_cache_insert_dev - Add a device to the address cache
5d5a0936 LV	215	* @dev: PCI device whose I/O addresses we are interested in.
	216	*
	217	* In order to support the fast lookup of devices based on addresses,
	218	* we maintain a cache of devices that can be quickly searched.
	219	* This routine adds a device to that cache.
	220	*/
3ab96a02	221	void eeh_addr_cache_insert_dev(struct pci_dev *dev)
5d5a0936 LV	222	{
	223	unsigned long flags;
	224
093eda3c LV	225	/* Ignore PCI bridges */
	226	if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
	227	return;
	228
5d5a0936	229	spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
3ab96a02	230	__eeh_addr_cache_insert_dev(dev);
5d5a0936 LV	231	spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
	232	}
	233
3ab96a02	234	static inline void __eeh_addr_cache_rmv_dev(struct pci_dev *dev)
5d5a0936 LV	235	{
5d5a0936 LV	236	struct rb_node *n;
5d5a0936 LV	237
	238	restart:
	239	n = rb_first(&pci_io_addr_cache_root.rb_root);
	240	while (n) {
	241	struct pci_io_addr_range *piar;
	242	piar = rb_entry(n, struct pci_io_addr_range, rb_node);
	243
	244	if (piar->pcidev == dev) {
	245	rb_erase(n, &pci_io_addr_cache_root.rb_root);
5d5a0936 LV	246	kfree(piar);
	247	goto restart;
	248	}
	249	n = rb_next(n);
	250	}
5d5a0936 LV	251	}
	252
	253	/**
3ab96a02	254	* eeh_addr_cache_rmv_dev - remove pci device from addr cache
5d5a0936 LV	255	* @dev: device to remove
	256	*
	257	* Remove a device from the addr-cache tree.
	258	* This is potentially expensive, since it will walk
	259	* the tree multiple times (once per resource).
	260	* But so what; device removal doesn't need to be that fast.
	261	*/
3ab96a02	262	void eeh_addr_cache_rmv_dev(struct pci_dev *dev)
5d5a0936 LV	263	{
	264	unsigned long flags;
	265
	266	spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
3ab96a02	267	__eeh_addr_cache_rmv_dev(dev);
5d5a0936 LV	268	spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
	269	}
	270
	271	/**
3ab96a02	272	* eeh_addr_cache_build - Build a cache of I/O addresses
5d5a0936 LV	273	*
	274	* Build a cache of pci i/o addresses. This cache will be used to
	275	* find the pci device that corresponds to a given address.
	276	* This routine scans all pci busses to build the cache.
	277	* Must be run late in boot process, after the pci controllers
d6e05edc	278	* have been scanned for devices (after all device resources are known).
5d5a0936	279	*/
eeb6361f	280	void eeh_addr_cache_build(void)
5d5a0936	281	{
c6406d8f	282	struct pci_dn *pdn;
d50a7d4c	283	struct eeh_dev *edev;
5d5a0936 LV	284	struct pci_dev *dev = NULL;
	285
	286	spin_lock_init(&pci_io_addr_cache_root.piar_lock);
	287
6901c6cc	288	for_each_pci_dev(dev) {
c6406d8f GS	289	pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
c6406d8f GS	290	if (!pdn)
ccba051c	291	continue;
d50a7d4c	292
c6406d8f	293	edev = pdn_to_eeh_dev(pdn);
d50a7d4c GS	294	if (!edev)
	295	continue;
	296
d50a7d4c GS	297	dev->dev.archdata.edev = edev;
d50a7d4c GS	298	edev->pdev = dev;
e1d04c97	299
1abd6018	300	eeh_addr_cache_insert_dev(dev);
e1d04c97	301	eeh_sysfs_add_device(dev);
5d5a0936 LV	302	}
	303
	304	#ifdef DEBUG
	305	/* Verify tree built up above, echo back the list of addrs. */
3ab96a02	306	eeh_addr_cache_print(&pci_io_addr_cache_root);
5d5a0936 LV	307	#endif
5d5a0936 LV	308	}