Commit | Line | Data |
---|---|---|
5d5a0936 | 1 | /* |
5d5a0936 LV |
2 | * PCI address cache; allows the lookup of PCI devices based on I/O address |
3 | * | |
3c8c90ab LV |
4 | * Copyright IBM Corporation 2004 |
5 | * Copyright Linas Vepstas <linas@austin.ibm.com> 2004 | |
5d5a0936 LV |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | #include <linux/list.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/rbtree.h> | |
5a0e3ad6 | 25 | #include <linux/slab.h> |
5d5a0936 | 26 | #include <linux/spinlock.h> |
60063497 | 27 | #include <linux/atomic.h> |
5d5a0936 LV |
28 | #include <asm/pci-bridge.h> |
29 | #include <asm/ppc-pci.h> | |
5d5a0936 | 30 | |
5d5a0936 LV |
31 | |
32 | /** | |
33 | * The pci address cache subsystem. This subsystem places | |
34 | * PCI device address resources into a red-black tree, sorted | |
35 | * according to the address range, so that given only an i/o | |
36 | * address, the corresponding PCI device can be **quickly** | |
37 | * found. It is safe to perform an address lookup in an interrupt | |
38 | * context; this ability is an important feature. | |
39 | * | |
40 | * Currently, the only customer of this code is the EEH subsystem; | |
41 | * thus, this code has been somewhat tailored to suit EEH better. | |
42 | * In particular, the cache does *not* hold the addresses of devices | |
43 | * for which EEH is not enabled. | |
44 | * | |
45 | * (Implementation Note: The RB tree seems to be better/faster | |
46 | * than any hash algo I could think of for this problem, even | |
47 | * with the penalty of slow pointer chases for d-cache misses). | |
48 | */ | |
29f8bf1b | 49 | struct pci_io_addr_range { |
5d5a0936 LV |
50 | struct rb_node rb_node; |
51 | unsigned long addr_lo; | |
52 | unsigned long addr_hi; | |
f8f7d63f | 53 | struct eeh_dev *edev; |
5d5a0936 LV |
54 | struct pci_dev *pcidev; |
55 | unsigned int flags; | |
56 | }; | |
57 | ||
29f8bf1b | 58 | static struct pci_io_addr_cache { |
5d5a0936 LV |
59 | struct rb_root rb_root; |
60 | spinlock_t piar_lock; | |
61 | } pci_io_addr_cache_root; | |
62 | ||
3ab96a02 | 63 | static inline struct eeh_dev *__eeh_addr_cache_get_device(unsigned long addr) |
5d5a0936 LV |
64 | { |
65 | struct rb_node *n = pci_io_addr_cache_root.rb_root.rb_node; | |
66 | ||
67 | while (n) { | |
68 | struct pci_io_addr_range *piar; | |
69 | piar = rb_entry(n, struct pci_io_addr_range, rb_node); | |
70 | ||
0ba17888 | 71 | if (addr < piar->addr_lo) |
5d5a0936 | 72 | n = n->rb_left; |
0ba17888 GS |
73 | else if (addr > piar->addr_hi) |
74 | n = n->rb_right; | |
75 | else | |
76 | return piar->edev; | |
5d5a0936 LV |
77 | } |
78 | ||
79 | return NULL; | |
80 | } | |
81 | ||
82 | /** | |
3ab96a02 | 83 | * eeh_addr_cache_get_dev - Get device, given only address |
5d5a0936 LV |
84 | * @addr: mmio (PIO) phys address or i/o port number |
85 | * | |
86 | * Given an mmio phys address, or a port number, find a pci device | |
87 | * that implements this address. Be sure to pci_dev_put the device | |
88 | * when finished. I/O port numbers are assumed to be offset | |
89 | * from zero (that is, they do *not* have pci_io_addr added in). | |
90 | * It is safe to call this function within an interrupt. | |
91 | */ | |
3ab96a02 | 92 | struct eeh_dev *eeh_addr_cache_get_dev(unsigned long addr) |
5d5a0936 | 93 | { |
f8f7d63f | 94 | struct eeh_dev *edev; |
5d5a0936 LV |
95 | unsigned long flags; |
96 | ||
97 | spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags); | |
3ab96a02 | 98 | edev = __eeh_addr_cache_get_device(addr); |
5d5a0936 | 99 | spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags); |
f8f7d63f | 100 | return edev; |
5d5a0936 LV |
101 | } |
102 | ||
103 | #ifdef DEBUG | |
104 | /* | |
105 | * Handy-dandy debug print routine, does nothing more | |
106 | * than print out the contents of our addr cache. | |
107 | */ | |
3ab96a02 | 108 | static void eeh_addr_cache_print(struct pci_io_addr_cache *cache) |
5d5a0936 LV |
109 | { |
110 | struct rb_node *n; | |
111 | int cnt = 0; | |
112 | ||
113 | n = rb_first(&cache->rb_root); | |
114 | while (n) { | |
115 | struct pci_io_addr_range *piar; | |
116 | piar = rb_entry(n, struct pci_io_addr_range, rb_node); | |
3ab96a02 | 117 | pr_debug("PCI: %s addr range %d [%lx-%lx]: %s\n", |
5d5a0936 LV |
118 | (piar->flags & IORESOURCE_IO) ? "i/o" : "mem", cnt, |
119 | piar->addr_lo, piar->addr_hi, pci_name(piar->pcidev)); | |
120 | cnt++; | |
121 | n = rb_next(n); | |
122 | } | |
123 | } | |
124 | #endif | |
125 | ||
126 | /* Insert address range into the rb tree. */ | |
127 | static struct pci_io_addr_range * | |
3ab96a02 | 128 | eeh_addr_cache_insert(struct pci_dev *dev, unsigned long alo, |
5d5a0936 LV |
129 | unsigned long ahi, unsigned int flags) |
130 | { | |
131 | struct rb_node **p = &pci_io_addr_cache_root.rb_root.rb_node; | |
132 | struct rb_node *parent = NULL; | |
133 | struct pci_io_addr_range *piar; | |
134 | ||
135 | /* Walk tree, find a place to insert into tree */ | |
136 | while (*p) { | |
137 | parent = *p; | |
138 | piar = rb_entry(parent, struct pci_io_addr_range, rb_node); | |
139 | if (ahi < piar->addr_lo) { | |
140 | p = &parent->rb_left; | |
141 | } else if (alo > piar->addr_hi) { | |
142 | p = &parent->rb_right; | |
143 | } else { | |
144 | if (dev != piar->pcidev || | |
145 | alo != piar->addr_lo || ahi != piar->addr_hi) { | |
3ab96a02 | 146 | pr_warning("PIAR: overlapping address range\n"); |
5d5a0936 LV |
147 | } |
148 | return piar; | |
149 | } | |
150 | } | |
7e4bbaf0 | 151 | piar = kzalloc(sizeof(struct pci_io_addr_range), GFP_ATOMIC); |
5d5a0936 LV |
152 | if (!piar) |
153 | return NULL; | |
154 | ||
155 | piar->addr_lo = alo; | |
156 | piar->addr_hi = ahi; | |
f8f7d63f | 157 | piar->edev = pci_dev_to_eeh_dev(dev); |
5d5a0936 LV |
158 | piar->pcidev = dev; |
159 | piar->flags = flags; | |
160 | ||
161 | #ifdef DEBUG | |
3ab96a02 | 162 | pr_debug("PIAR: insert range=[%lx:%lx] dev=%s\n", |
29f8bf1b | 163 | alo, ahi, pci_name(dev)); |
5d5a0936 LV |
164 | #endif |
165 | ||
166 | rb_link_node(&piar->rb_node, parent, p); | |
167 | rb_insert_color(&piar->rb_node, &pci_io_addr_cache_root.rb_root); | |
168 | ||
169 | return piar; | |
170 | } | |
171 | ||
3ab96a02 | 172 | static void __eeh_addr_cache_insert_dev(struct pci_dev *dev) |
5d5a0936 LV |
173 | { |
174 | struct device_node *dn; | |
d50a7d4c | 175 | struct eeh_dev *edev; |
5d5a0936 | 176 | int i; |
5d5a0936 LV |
177 | |
178 | dn = pci_device_to_OF_node(dev); | |
179 | if (!dn) { | |
3ab96a02 | 180 | pr_warning("PCI: no pci dn found for dev=%s\n", pci_name(dev)); |
5d5a0936 LV |
181 | return; |
182 | } | |
183 | ||
d50a7d4c GS |
184 | edev = of_node_to_eeh_dev(dn); |
185 | if (!edev) { | |
186 | pr_warning("PCI: no EEH dev found for dn=%s\n", | |
187 | dn->full_name); | |
188 | return; | |
189 | } | |
190 | ||
5d5a0936 | 191 | /* Skip any devices for which EEH is not enabled. */ |
88b6d14b | 192 | if (!eeh_probe_mode_dev() && !edev->pe) { |
5d5a0936 | 193 | #ifdef DEBUG |
d50a7d4c GS |
194 | pr_info("PCI: skip building address cache for=%s - %s\n", |
195 | pci_name(dev), dn->full_name); | |
5d5a0936 LV |
196 | #endif |
197 | return; | |
198 | } | |
199 | ||
5d5a0936 LV |
200 | /* Walk resources on this device, poke them into the tree */ |
201 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
202 | unsigned long start = pci_resource_start(dev,i); | |
203 | unsigned long end = pci_resource_end(dev,i); | |
204 | unsigned int flags = pci_resource_flags(dev,i); | |
205 | ||
206 | /* We are interested only bus addresses, not dma or other stuff */ | |
207 | if (0 == (flags & (IORESOURCE_IO | IORESOURCE_MEM))) | |
208 | continue; | |
209 | if (start == 0 || ~start == 0 || end == 0 || ~end == 0) | |
210 | continue; | |
3ab96a02 | 211 | eeh_addr_cache_insert(dev, start, end, flags); |
5d5a0936 | 212 | } |
5d5a0936 LV |
213 | } |
214 | ||
215 | /** | |
3ab96a02 | 216 | * eeh_addr_cache_insert_dev - Add a device to the address cache |
5d5a0936 LV |
217 | * @dev: PCI device whose I/O addresses we are interested in. |
218 | * | |
219 | * In order to support the fast lookup of devices based on addresses, | |
220 | * we maintain a cache of devices that can be quickly searched. | |
221 | * This routine adds a device to that cache. | |
222 | */ | |
3ab96a02 | 223 | void eeh_addr_cache_insert_dev(struct pci_dev *dev) |
5d5a0936 LV |
224 | { |
225 | unsigned long flags; | |
226 | ||
093eda3c LV |
227 | /* Ignore PCI bridges */ |
228 | if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) | |
229 | return; | |
230 | ||
5d5a0936 | 231 | spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags); |
3ab96a02 | 232 | __eeh_addr_cache_insert_dev(dev); |
5d5a0936 LV |
233 | spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags); |
234 | } | |
235 | ||
3ab96a02 | 236 | static inline void __eeh_addr_cache_rmv_dev(struct pci_dev *dev) |
5d5a0936 LV |
237 | { |
238 | struct rb_node *n; | |
5d5a0936 LV |
239 | |
240 | restart: | |
241 | n = rb_first(&pci_io_addr_cache_root.rb_root); | |
242 | while (n) { | |
243 | struct pci_io_addr_range *piar; | |
244 | piar = rb_entry(n, struct pci_io_addr_range, rb_node); | |
245 | ||
246 | if (piar->pcidev == dev) { | |
247 | rb_erase(n, &pci_io_addr_cache_root.rb_root); | |
5d5a0936 LV |
248 | kfree(piar); |
249 | goto restart; | |
250 | } | |
251 | n = rb_next(n); | |
252 | } | |
5d5a0936 LV |
253 | } |
254 | ||
255 | /** | |
3ab96a02 | 256 | * eeh_addr_cache_rmv_dev - remove pci device from addr cache |
5d5a0936 LV |
257 | * @dev: device to remove |
258 | * | |
259 | * Remove a device from the addr-cache tree. | |
260 | * This is potentially expensive, since it will walk | |
261 | * the tree multiple times (once per resource). | |
262 | * But so what; device removal doesn't need to be that fast. | |
263 | */ | |
3ab96a02 | 264 | void eeh_addr_cache_rmv_dev(struct pci_dev *dev) |
5d5a0936 LV |
265 | { |
266 | unsigned long flags; | |
267 | ||
268 | spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags); | |
3ab96a02 | 269 | __eeh_addr_cache_rmv_dev(dev); |
5d5a0936 LV |
270 | spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags); |
271 | } | |
272 | ||
273 | /** | |
3ab96a02 | 274 | * eeh_addr_cache_build - Build a cache of I/O addresses |
5d5a0936 LV |
275 | * |
276 | * Build a cache of pci i/o addresses. This cache will be used to | |
277 | * find the pci device that corresponds to a given address. | |
278 | * This routine scans all pci busses to build the cache. | |
279 | * Must be run late in boot process, after the pci controllers | |
d6e05edc | 280 | * have been scanned for devices (after all device resources are known). |
5d5a0936 | 281 | */ |
eeb6361f | 282 | void eeh_addr_cache_build(void) |
5d5a0936 LV |
283 | { |
284 | struct device_node *dn; | |
d50a7d4c | 285 | struct eeh_dev *edev; |
5d5a0936 LV |
286 | struct pci_dev *dev = NULL; |
287 | ||
288 | spin_lock_init(&pci_io_addr_cache_root.piar_lock); | |
289 | ||
6901c6cc | 290 | for_each_pci_dev(dev) { |
5d5a0936 | 291 | dn = pci_device_to_OF_node(dev); |
ccba051c NL |
292 | if (!dn) |
293 | continue; | |
d50a7d4c GS |
294 | |
295 | edev = of_node_to_eeh_dev(dn); | |
296 | if (!edev) | |
297 | continue; | |
298 | ||
d50a7d4c GS |
299 | dev->dev.archdata.edev = edev; |
300 | edev->pdev = dev; | |
e1d04c97 | 301 | |
1abd6018 | 302 | eeh_addr_cache_insert_dev(dev); |
e1d04c97 | 303 | eeh_sysfs_add_device(dev); |
5d5a0936 LV |
304 | } |
305 | ||
306 | #ifdef DEBUG | |
307 | /* Verify tree built up above, echo back the list of addrs. */ | |
3ab96a02 | 308 | eeh_addr_cache_print(&pci_io_addr_cache_root); |
5d5a0936 LV |
309 | #endif |
310 | } |