Commit | Line | Data |
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0ebc4cda BH |
1 | /* |
2 | * This file contains the 64-bit "server" PowerPC variant | |
3 | * of the low level exception handling including exception | |
4 | * vectors, exception return, part of the slb and stab | |
5 | * handling and other fixed offset specific things. | |
6 | * | |
7 | * This file is meant to be #included from head_64.S due to | |
25985edc | 8 | * position dependent assembly. |
0ebc4cda BH |
9 | * |
10 | * Most of this originates from head_64.S and thus has the same | |
11 | * copyright history. | |
12 | * | |
13 | */ | |
14 | ||
8aa34ab8 | 15 | #include <asm/exception-64s.h> |
46f52210 | 16 | #include <asm/ptrace.h> |
8aa34ab8 | 17 | |
0ebc4cda BH |
18 | /* |
19 | * We layout physical memory as follows: | |
20 | * 0x0000 - 0x00ff : Secondary processor spin code | |
21 | * 0x0100 - 0x2fff : pSeries Interrupt prologs | |
4f8cf36f | 22 | * 0x3000 - 0x5fff : interrupt support common interrupt prologs |
0ebc4cda BH |
23 | * 0x6000 - 0x6fff : Initial (CPU0) segment table |
24 | * 0x7000 - 0x7fff : FWNMI data area | |
25 | * 0x8000 - : Early init and support code | |
26 | */ | |
27 | ||
0ebc4cda BH |
28 | /* |
29 | * This is the start of the interrupt handlers for pSeries | |
30 | * This code runs with relocation off. | |
31 | * Code from here to __end_interrupts gets copied down to real | |
32 | * address 0x100 when we are running a relocatable kernel. | |
33 | * Therefore any relative branches in this section must only | |
34 | * branch to labels in this section. | |
35 | */ | |
36 | . = 0x100 | |
37 | .globl __start_interrupts | |
38 | __start_interrupts: | |
39 | ||
948cf67c BH |
40 | .globl system_reset_pSeries; |
41 | system_reset_pSeries: | |
42 | HMT_MEDIUM; | |
948cf67c BH |
43 | SET_SCRATCH0(r13) |
44 | #ifdef CONFIG_PPC_P7_NAP | |
45 | BEGIN_FTR_SECTION | |
46 | /* Running native on arch 2.06 or later, check if we are | |
47 | * waking up from nap. We only handle no state loss and | |
48 | * supervisor state loss. We do -not- handle hypervisor | |
49 | * state loss at this time. | |
50 | */ | |
51 | mfspr r13,SPRN_SRR1 | |
371fefd6 PM |
52 | rlwinm. r13,r13,47-31,30,31 |
53 | beq 9f | |
54 | ||
55 | /* waking up from powersave (nap) state */ | |
56 | cmpwi cr1,r13,2 | |
948cf67c BH |
57 | /* Total loss of HV state is fatal, we could try to use the |
58 | * PIR to locate a PACA, then use an emergency stack etc... | |
59 | * but for now, let's just stay stuck here | |
60 | */ | |
371fefd6 PM |
61 | bgt cr1,. |
62 | GET_PACA(r13) | |
63 | ||
64 | #ifdef CONFIG_KVM_BOOK3S_64_HV | |
65 | lbz r0,PACAPROCSTART(r13) | |
66 | cmpwi r0,0x80 | |
67 | bne 1f | |
cba313da | 68 | li r0,1 |
371fefd6 PM |
69 | stb r0,PACAPROCSTART(r13) |
70 | b kvm_start_guest | |
71 | 1: | |
72 | #endif | |
73 | ||
74 | beq cr1,2f | |
75 | b .power7_wakeup_noloss | |
76 | 2: b .power7_wakeup_loss | |
77 | 9: | |
969391c5 | 78 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
948cf67c | 79 | #endif /* CONFIG_PPC_P7_NAP */ |
b01c8b54 PM |
80 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, |
81 | NOTEST, 0x100) | |
0ebc4cda BH |
82 | |
83 | . = 0x200 | |
b01c8b54 PM |
84 | machine_check_pSeries_1: |
85 | /* This is moved out of line as it can be patched by FW, but | |
86 | * some code path might still want to branch into the original | |
87 | * vector | |
88 | */ | |
89 | b machine_check_pSeries | |
0ebc4cda BH |
90 | |
91 | . = 0x300 | |
92 | .globl data_access_pSeries | |
93 | data_access_pSeries: | |
94 | HMT_MEDIUM | |
673b189a | 95 | SET_SCRATCH0(r13) |
b01c8b54 | 96 | #ifndef CONFIG_POWER4_ONLY |
0ebc4cda | 97 | BEGIN_FTR_SECTION |
b01c8b54 PM |
98 | b data_access_check_stab |
99 | data_access_not_stab: | |
100 | END_MMU_FTR_SECTION_IFCLR(MMU_FTR_SLB) | |
101 | #endif | |
102 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common, EXC_STD, | |
de56a948 | 103 | KVMTEST_PR, 0x300) |
0ebc4cda BH |
104 | |
105 | . = 0x380 | |
106 | .globl data_access_slb_pSeries | |
107 | data_access_slb_pSeries: | |
108 | HMT_MEDIUM | |
673b189a | 109 | SET_SCRATCH0(r13) |
de56a948 | 110 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380) |
0ebc4cda BH |
111 | std r3,PACA_EXSLB+EX_R3(r13) |
112 | mfspr r3,SPRN_DAR | |
0ebc4cda BH |
113 | #ifdef __DISABLED__ |
114 | /* Keep that around for when we re-implement dynamic VSIDs */ | |
115 | cmpdi r3,0 | |
116 | bge slb_miss_user_pseries | |
117 | #endif /* __DISABLED__ */ | |
b01c8b54 | 118 | mfspr r12,SPRN_SRR1 |
0ebc4cda BH |
119 | #ifndef CONFIG_RELOCATABLE |
120 | b .slb_miss_realmode | |
121 | #else | |
122 | /* | |
123 | * We can't just use a direct branch to .slb_miss_realmode | |
124 | * because the distance from here to there depends on where | |
125 | * the kernel ends up being put. | |
126 | */ | |
127 | mfctr r11 | |
128 | ld r10,PACAKBASE(r13) | |
129 | LOAD_HANDLER(r10, .slb_miss_realmode) | |
130 | mtctr r10 | |
131 | bctr | |
132 | #endif | |
133 | ||
b3e6b5df | 134 | STD_EXCEPTION_PSERIES(0x400, 0x400, instruction_access) |
0ebc4cda BH |
135 | |
136 | . = 0x480 | |
137 | .globl instruction_access_slb_pSeries | |
138 | instruction_access_slb_pSeries: | |
139 | HMT_MEDIUM | |
673b189a | 140 | SET_SCRATCH0(r13) |
de56a948 | 141 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480) |
0ebc4cda BH |
142 | std r3,PACA_EXSLB+EX_R3(r13) |
143 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
0ebc4cda BH |
144 | #ifdef __DISABLED__ |
145 | /* Keep that around for when we re-implement dynamic VSIDs */ | |
146 | cmpdi r3,0 | |
147 | bge slb_miss_user_pseries | |
148 | #endif /* __DISABLED__ */ | |
b01c8b54 | 149 | mfspr r12,SPRN_SRR1 |
0ebc4cda BH |
150 | #ifndef CONFIG_RELOCATABLE |
151 | b .slb_miss_realmode | |
152 | #else | |
153 | mfctr r11 | |
154 | ld r10,PACAKBASE(r13) | |
155 | LOAD_HANDLER(r10, .slb_miss_realmode) | |
156 | mtctr r10 | |
157 | bctr | |
158 | #endif | |
159 | ||
b3e6b5df BH |
160 | /* We open code these as we can't have a ". = x" (even with |
161 | * x = "." within a feature section | |
162 | */ | |
a5d4f3ad | 163 | . = 0x500; |
b3e6b5df BH |
164 | .globl hardware_interrupt_pSeries; |
165 | .globl hardware_interrupt_hv; | |
a5d4f3ad | 166 | hardware_interrupt_pSeries: |
b3e6b5df | 167 | hardware_interrupt_hv: |
a5d4f3ad | 168 | BEGIN_FTR_SECTION |
b01c8b54 PM |
169 | _MASKABLE_EXCEPTION_PSERIES(0x502, hardware_interrupt, |
170 | EXC_HV, SOFTEN_TEST_HV) | |
171 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0x502) | |
de56a948 PM |
172 | FTR_SECTION_ELSE |
173 | _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt, | |
9e368f29 | 174 | EXC_STD, SOFTEN_TEST_HV_201) |
de56a948 | 175 | KVM_HANDLER(PACA_EXGEN, EXC_STD, 0x500) |
969391c5 | 176 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
a5d4f3ad | 177 | |
b3e6b5df | 178 | STD_EXCEPTION_PSERIES(0x600, 0x600, alignment) |
de56a948 | 179 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x600) |
b01c8b54 | 180 | |
b3e6b5df | 181 | STD_EXCEPTION_PSERIES(0x700, 0x700, program_check) |
de56a948 | 182 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x700) |
b01c8b54 | 183 | |
b3e6b5df | 184 | STD_EXCEPTION_PSERIES(0x800, 0x800, fp_unavailable) |
de56a948 | 185 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x800) |
a5d4f3ad | 186 | |
b3e6b5df | 187 | MASKABLE_EXCEPTION_PSERIES(0x900, 0x900, decrementer) |
b01c8b54 | 188 | MASKABLE_EXCEPTION_HV(0x980, 0x982, decrementer) |
a5d4f3ad | 189 | |
b3e6b5df | 190 | STD_EXCEPTION_PSERIES(0xa00, 0xa00, trap_0a) |
de56a948 | 191 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xa00) |
b01c8b54 | 192 | |
b3e6b5df | 193 | STD_EXCEPTION_PSERIES(0xb00, 0xb00, trap_0b) |
de56a948 | 194 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xb00) |
0ebc4cda BH |
195 | |
196 | . = 0xc00 | |
197 | .globl system_call_pSeries | |
198 | system_call_pSeries: | |
199 | HMT_MEDIUM | |
b01c8b54 PM |
200 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
201 | SET_SCRATCH0(r13) | |
202 | GET_PACA(r13) | |
203 | std r9,PACA_EXGEN+EX_R9(r13) | |
204 | std r10,PACA_EXGEN+EX_R10(r13) | |
205 | mfcr r9 | |
206 | KVMTEST(0xc00) | |
207 | GET_SCRATCH0(r13) | |
208 | #endif | |
0ebc4cda BH |
209 | BEGIN_FTR_SECTION |
210 | cmpdi r0,0x1ebe | |
211 | beq- 1f | |
212 | END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) | |
213 | mr r9,r13 | |
2dd60d79 | 214 | GET_PACA(r13) |
0ebc4cda | 215 | mfspr r11,SPRN_SRR0 |
0ebc4cda | 216 | mfspr r12,SPRN_SRR1 |
f5f0307f AB |
217 | ld r10,PACAKBASE(r13) |
218 | LOAD_HANDLER(r10, system_call_entry) | |
219 | mtspr SPRN_SRR0,r10 | |
220 | ld r10,PACAKMSR(r13) | |
0ebc4cda BH |
221 | mtspr SPRN_SRR1,r10 |
222 | rfid | |
223 | b . /* prevent speculative execution */ | |
224 | ||
b01c8b54 PM |
225 | KVM_HANDLER(PACA_EXGEN, EXC_STD, 0xc00) |
226 | ||
0ebc4cda BH |
227 | /* Fast LE/BE switch system call */ |
228 | 1: mfspr r12,SPRN_SRR1 | |
229 | xori r12,r12,MSR_LE | |
230 | mtspr SPRN_SRR1,r12 | |
231 | rfid /* return to userspace */ | |
232 | b . | |
233 | ||
b3e6b5df | 234 | STD_EXCEPTION_PSERIES(0xd00, 0xd00, single_step) |
de56a948 | 235 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xd00) |
b3e6b5df BH |
236 | |
237 | /* At 0xe??? we have a bunch of hypervisor exceptions, we branch | |
238 | * out of line to handle them | |
239 | */ | |
240 | . = 0xe00 | |
241 | b h_data_storage_hv | |
242 | . = 0xe20 | |
243 | b h_instr_storage_hv | |
244 | . = 0xe40 | |
245 | b emulation_assist_hv | |
246 | . = 0xe50 | |
247 | b hmi_exception_hv | |
248 | . = 0xe60 | |
249 | b hmi_exception_hv | |
0ebc4cda BH |
250 | |
251 | /* We need to deal with the Altivec unavailable exception | |
252 | * here which is at 0xf20, thus in the middle of the | |
253 | * prolog code of the PerformanceMonitor one. A little | |
254 | * trickery is thus necessary | |
255 | */ | |
c86e2ead | 256 | performance_monitor_pSeries_1: |
0ebc4cda BH |
257 | . = 0xf00 |
258 | b performance_monitor_pSeries | |
259 | ||
c86e2ead | 260 | altivec_unavailable_pSeries_1: |
0ebc4cda BH |
261 | . = 0xf20 |
262 | b altivec_unavailable_pSeries | |
263 | ||
c86e2ead | 264 | vsx_unavailable_pSeries_1: |
0ebc4cda BH |
265 | . = 0xf40 |
266 | b vsx_unavailable_pSeries | |
267 | ||
268 | #ifdef CONFIG_CBE_RAS | |
b3e6b5df | 269 | STD_EXCEPTION_HV(0x1200, 0x1202, cbe_system_error) |
5ccf55dd | 270 | KVM_HANDLER_SKIP(PACA_EXGEN, EXC_HV, 0x1202) |
0ebc4cda | 271 | #endif /* CONFIG_CBE_RAS */ |
b01c8b54 | 272 | |
b3e6b5df | 273 | STD_EXCEPTION_PSERIES(0x1300, 0x1300, instruction_breakpoint) |
de56a948 | 274 | KVM_HANDLER_PR_SKIP(PACA_EXGEN, EXC_STD, 0x1300) |
b01c8b54 | 275 | |
0ebc4cda | 276 | #ifdef CONFIG_CBE_RAS |
b3e6b5df | 277 | STD_EXCEPTION_HV(0x1600, 0x1602, cbe_maintenance) |
5ccf55dd | 278 | KVM_HANDLER_SKIP(PACA_EXGEN, EXC_HV, 0x1602) |
0ebc4cda | 279 | #endif /* CONFIG_CBE_RAS */ |
b01c8b54 | 280 | |
b3e6b5df | 281 | STD_EXCEPTION_PSERIES(0x1700, 0x1700, altivec_assist) |
de56a948 | 282 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x1700) |
b01c8b54 | 283 | |
0ebc4cda | 284 | #ifdef CONFIG_CBE_RAS |
b3e6b5df | 285 | STD_EXCEPTION_HV(0x1800, 0x1802, cbe_thermal) |
5ccf55dd | 286 | KVM_HANDLER_SKIP(PACA_EXGEN, EXC_HV, 0x1802) |
0ebc4cda BH |
287 | #endif /* CONFIG_CBE_RAS */ |
288 | ||
289 | . = 0x3000 | |
290 | ||
b3e6b5df BH |
291 | /*** Out of line interrupts support ***/ |
292 | ||
b01c8b54 PM |
293 | /* moved from 0x200 */ |
294 | machine_check_pSeries: | |
295 | .globl machine_check_fwnmi | |
296 | machine_check_fwnmi: | |
297 | HMT_MEDIUM | |
298 | SET_SCRATCH0(r13) /* save r13 */ | |
299 | EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common, | |
300 | EXC_STD, KVMTEST, 0x200) | |
301 | KVM_HANDLER_SKIP(PACA_EXMC, EXC_STD, 0x200) | |
302 | ||
303 | #ifndef CONFIG_POWER4_ONLY | |
304 | /* moved from 0x300 */ | |
305 | data_access_check_stab: | |
306 | GET_PACA(r13) | |
307 | std r9,PACA_EXSLB+EX_R9(r13) | |
308 | std r10,PACA_EXSLB+EX_R10(r13) | |
309 | mfspr r10,SPRN_DAR | |
310 | mfspr r9,SPRN_DSISR | |
311 | srdi r10,r10,60 | |
312 | rlwimi r10,r9,16,0x20 | |
de56a948 | 313 | #ifdef CONFIG_KVM_BOOK3S_PR |
3c42bf8a | 314 | lbz r9,HSTATE_IN_GUEST(r13) |
b01c8b54 PM |
315 | rlwimi r10,r9,8,0x300 |
316 | #endif | |
317 | mfcr r9 | |
318 | cmpwi r10,0x2c | |
319 | beq do_stab_bolted_pSeries | |
320 | mtcrf 0x80,r9 | |
321 | ld r9,PACA_EXSLB+EX_R9(r13) | |
322 | ld r10,PACA_EXSLB+EX_R10(r13) | |
323 | b data_access_not_stab | |
324 | do_stab_bolted_pSeries: | |
325 | std r11,PACA_EXSLB+EX_R11(r13) | |
326 | std r12,PACA_EXSLB+EX_R12(r13) | |
327 | GET_SCRATCH0(r10) | |
328 | std r10,PACA_EXSLB+EX_R13(r13) | |
329 | EXCEPTION_PROLOG_PSERIES_1(.do_stab_bolted, EXC_STD) | |
330 | #endif /* CONFIG_POWER4_ONLY */ | |
331 | ||
de56a948 PM |
332 | KVM_HANDLER_PR_SKIP(PACA_EXGEN, EXC_STD, 0x300) |
333 | KVM_HANDLER_PR_SKIP(PACA_EXSLB, EXC_STD, 0x380) | |
334 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x400) | |
335 | KVM_HANDLER_PR(PACA_EXSLB, EXC_STD, 0x480) | |
336 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x900) | |
b01c8b54 PM |
337 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0x982) |
338 | ||
339 | .align 7 | |
b3e6b5df | 340 | /* moved from 0xe00 */ |
b01c8b54 PM |
341 | STD_EXCEPTION_HV(., 0xe02, h_data_storage) |
342 | KVM_HANDLER_SKIP(PACA_EXGEN, EXC_HV, 0xe02) | |
343 | STD_EXCEPTION_HV(., 0xe22, h_instr_storage) | |
344 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe22) | |
345 | STD_EXCEPTION_HV(., 0xe42, emulation_assist) | |
346 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe42) | |
347 | STD_EXCEPTION_HV(., 0xe62, hmi_exception) /* need to flush cache ? */ | |
348 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe62) | |
0ebc4cda BH |
349 | |
350 | /* moved from 0xf00 */ | |
b3e6b5df | 351 | STD_EXCEPTION_PSERIES(., 0xf00, performance_monitor) |
de56a948 | 352 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xf00) |
b3e6b5df | 353 | STD_EXCEPTION_PSERIES(., 0xf20, altivec_unavailable) |
de56a948 | 354 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xf20) |
b3e6b5df | 355 | STD_EXCEPTION_PSERIES(., 0xf40, vsx_unavailable) |
de56a948 | 356 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xf40) |
0ebc4cda BH |
357 | |
358 | /* | |
359 | * An interrupt came in while soft-disabled; clear EE in SRR1, | |
360 | * clear paca->hard_enabled and return. | |
361 | */ | |
362 | masked_interrupt: | |
363 | stb r10,PACAHARDIRQEN(r13) | |
364 | mtcrf 0x80,r9 | |
365 | ld r9,PACA_EXGEN+EX_R9(r13) | |
366 | mfspr r10,SPRN_SRR1 | |
367 | rldicl r10,r10,48,1 /* clear MSR_EE */ | |
368 | rotldi r10,r10,16 | |
369 | mtspr SPRN_SRR1,r10 | |
370 | ld r10,PACA_EXGEN+EX_R10(r13) | |
673b189a | 371 | GET_SCRATCH0(r13) |
0ebc4cda BH |
372 | rfid |
373 | b . | |
374 | ||
a5d4f3ad BH |
375 | masked_Hinterrupt: |
376 | stb r10,PACAHARDIRQEN(r13) | |
377 | mtcrf 0x80,r9 | |
378 | ld r9,PACA_EXGEN+EX_R9(r13) | |
379 | mfspr r10,SPRN_HSRR1 | |
380 | rldicl r10,r10,48,1 /* clear MSR_EE */ | |
381 | rotldi r10,r10,16 | |
382 | mtspr SPRN_HSRR1,r10 | |
383 | ld r10,PACA_EXGEN+EX_R10(r13) | |
673b189a | 384 | GET_SCRATCH0(r13) |
a5d4f3ad BH |
385 | hrfid |
386 | b . | |
387 | ||
0ebc4cda BH |
388 | #ifdef CONFIG_PPC_PSERIES |
389 | /* | |
390 | * Vectors for the FWNMI option. Share common code. | |
391 | */ | |
392 | .globl system_reset_fwnmi | |
393 | .align 7 | |
394 | system_reset_fwnmi: | |
395 | HMT_MEDIUM | |
673b189a | 396 | SET_SCRATCH0(r13) /* save r13 */ |
b01c8b54 PM |
397 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, |
398 | NOTEST, 0x100) | |
0ebc4cda BH |
399 | |
400 | #endif /* CONFIG_PPC_PSERIES */ | |
401 | ||
402 | #ifdef __DISABLED__ | |
403 | /* | |
404 | * This is used for when the SLB miss handler has to go virtual, | |
405 | * which doesn't happen for now anymore but will once we re-implement | |
406 | * dynamic VSIDs for shared page tables | |
407 | */ | |
408 | slb_miss_user_pseries: | |
409 | std r10,PACA_EXGEN+EX_R10(r13) | |
410 | std r11,PACA_EXGEN+EX_R11(r13) | |
411 | std r12,PACA_EXGEN+EX_R12(r13) | |
673b189a | 412 | GET_SCRATCH0(r10) |
0ebc4cda BH |
413 | ld r11,PACA_EXSLB+EX_R9(r13) |
414 | ld r12,PACA_EXSLB+EX_R3(r13) | |
415 | std r10,PACA_EXGEN+EX_R13(r13) | |
416 | std r11,PACA_EXGEN+EX_R9(r13) | |
417 | std r12,PACA_EXGEN+EX_R3(r13) | |
418 | clrrdi r12,r13,32 | |
419 | mfmsr r10 | |
420 | mfspr r11,SRR0 /* save SRR0 */ | |
421 | ori r12,r12,slb_miss_user_common@l /* virt addr of handler */ | |
422 | ori r10,r10,MSR_IR|MSR_DR|MSR_RI | |
423 | mtspr SRR0,r12 | |
424 | mfspr r12,SRR1 /* and SRR1 */ | |
425 | mtspr SRR1,r10 | |
426 | rfid | |
427 | b . /* prevent spec. execution */ | |
428 | #endif /* __DISABLED__ */ | |
429 | ||
430 | .align 7 | |
431 | .globl __end_interrupts | |
432 | __end_interrupts: | |
433 | ||
434 | /* | |
435 | * Code from here down to __end_handlers is invoked from the | |
436 | * exception prologs above. Because the prologs assemble the | |
437 | * addresses of these handlers using the LOAD_HANDLER macro, | |
438 | * which uses an addi instruction, these handlers must be in | |
439 | * the first 32k of the kernel image. | |
440 | */ | |
441 | ||
442 | /*** Common interrupt handlers ***/ | |
443 | ||
444 | STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception) | |
445 | ||
446 | /* | |
447 | * Machine check is different because we use a different | |
448 | * save area: PACA_EXMC instead of PACA_EXGEN. | |
449 | */ | |
450 | .align 7 | |
451 | .globl machine_check_common | |
452 | machine_check_common: | |
453 | EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) | |
454 | FINISH_NAP | |
455 | DISABLE_INTS | |
456 | bl .save_nvgprs | |
457 | addi r3,r1,STACK_FRAME_OVERHEAD | |
458 | bl .machine_check_exception | |
459 | b .ret_from_except | |
460 | ||
4f8cf36f | 461 | STD_EXCEPTION_COMMON_LITE(0x500, hardware_interrupt, do_IRQ) |
0ebc4cda BH |
462 | STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt) |
463 | STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception) | |
464 | STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception) | |
465 | STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception) | |
466 | STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception) | |
b3e6b5df BH |
467 | STD_EXCEPTION_COMMON(0xe40, emulation_assist, .program_check_exception) |
468 | STD_EXCEPTION_COMMON(0xe60, hmi_exception, .unknown_exception) | |
0ebc4cda BH |
469 | STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception) |
470 | STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception) | |
471 | #ifdef CONFIG_ALTIVEC | |
472 | STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception) | |
473 | #else | |
474 | STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception) | |
475 | #endif | |
476 | #ifdef CONFIG_CBE_RAS | |
477 | STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception) | |
478 | STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception) | |
479 | STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception) | |
480 | #endif /* CONFIG_CBE_RAS */ | |
481 | ||
482 | .align 7 | |
483 | system_call_entry: | |
484 | b system_call_common | |
485 | ||
486 | /* | |
487 | * Here we have detected that the kernel stack pointer is bad. | |
488 | * R9 contains the saved CR, r13 points to the paca, | |
489 | * r10 contains the (bad) kernel stack pointer, | |
490 | * r11 and r12 contain the saved SRR0 and SRR1. | |
491 | * We switch to using an emergency stack, save the registers there, | |
492 | * and call kernel_bad_stack(), which panics. | |
493 | */ | |
494 | bad_stack: | |
495 | ld r1,PACAEMERGSP(r13) | |
496 | subi r1,r1,64+INT_FRAME_SIZE | |
497 | std r9,_CCR(r1) | |
498 | std r10,GPR1(r1) | |
499 | std r11,_NIP(r1) | |
500 | std r12,_MSR(r1) | |
501 | mfspr r11,SPRN_DAR | |
502 | mfspr r12,SPRN_DSISR | |
503 | std r11,_DAR(r1) | |
504 | std r12,_DSISR(r1) | |
505 | mflr r10 | |
506 | mfctr r11 | |
507 | mfxer r12 | |
508 | std r10,_LINK(r1) | |
509 | std r11,_CTR(r1) | |
510 | std r12,_XER(r1) | |
511 | SAVE_GPR(0,r1) | |
512 | SAVE_GPR(2,r1) | |
1977b502 PM |
513 | ld r10,EX_R3(r3) |
514 | std r10,GPR3(r1) | |
515 | SAVE_GPR(4,r1) | |
516 | SAVE_4GPRS(5,r1) | |
517 | ld r9,EX_R9(r3) | |
518 | ld r10,EX_R10(r3) | |
519 | SAVE_2GPRS(9,r1) | |
520 | ld r9,EX_R11(r3) | |
521 | ld r10,EX_R12(r3) | |
522 | ld r11,EX_R13(r3) | |
523 | std r9,GPR11(r1) | |
524 | std r10,GPR12(r1) | |
525 | std r11,GPR13(r1) | |
48404f2e PM |
526 | BEGIN_FTR_SECTION |
527 | ld r10,EX_CFAR(r3) | |
528 | std r10,ORIG_GPR3(r1) | |
529 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
1977b502 | 530 | SAVE_8GPRS(14,r1) |
0ebc4cda BH |
531 | SAVE_10GPRS(22,r1) |
532 | lhz r12,PACA_TRAP_SAVE(r13) | |
533 | std r12,_TRAP(r1) | |
534 | addi r11,r1,INT_FRAME_SIZE | |
535 | std r11,0(r1) | |
536 | li r12,0 | |
537 | std r12,0(r11) | |
538 | ld r2,PACATOC(r13) | |
1977b502 PM |
539 | ld r11,exception_marker@toc(r2) |
540 | std r12,RESULT(r1) | |
541 | std r11,STACK_FRAME_OVERHEAD-16(r1) | |
0ebc4cda BH |
542 | 1: addi r3,r1,STACK_FRAME_OVERHEAD |
543 | bl .kernel_bad_stack | |
544 | b 1b | |
545 | ||
546 | /* | |
547 | * Here r13 points to the paca, r9 contains the saved CR, | |
548 | * SRR0 and SRR1 are saved in r11 and r12, | |
549 | * r9 - r13 are saved in paca->exgen. | |
550 | */ | |
551 | .align 7 | |
552 | .globl data_access_common | |
553 | data_access_common: | |
554 | mfspr r10,SPRN_DAR | |
555 | std r10,PACA_EXGEN+EX_DAR(r13) | |
556 | mfspr r10,SPRN_DSISR | |
557 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
558 | EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) | |
559 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
560 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
561 | li r5,0x300 | |
562 | b .do_hash_page /* Try to handle as hpte fault */ | |
563 | ||
b3e6b5df BH |
564 | .align 7 |
565 | .globl h_data_storage_common | |
566 | h_data_storage_common: | |
567 | mfspr r10,SPRN_HDAR | |
568 | std r10,PACA_EXGEN+EX_DAR(r13) | |
569 | mfspr r10,SPRN_HDSISR | |
570 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
571 | EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) | |
572 | bl .save_nvgprs | |
573 | addi r3,r1,STACK_FRAME_OVERHEAD | |
574 | bl .unknown_exception | |
575 | b .ret_from_except | |
576 | ||
0ebc4cda BH |
577 | .align 7 |
578 | .globl instruction_access_common | |
579 | instruction_access_common: | |
580 | EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) | |
581 | ld r3,_NIP(r1) | |
582 | andis. r4,r12,0x5820 | |
583 | li r5,0x400 | |
584 | b .do_hash_page /* Try to handle as hpte fault */ | |
585 | ||
b3e6b5df BH |
586 | STD_EXCEPTION_COMMON(0xe20, h_instr_storage, .unknown_exception) |
587 | ||
0ebc4cda BH |
588 | /* |
589 | * Here is the common SLB miss user that is used when going to virtual | |
590 | * mode for SLB misses, that is currently not used | |
591 | */ | |
592 | #ifdef __DISABLED__ | |
593 | .align 7 | |
594 | .globl slb_miss_user_common | |
595 | slb_miss_user_common: | |
596 | mflr r10 | |
597 | std r3,PACA_EXGEN+EX_DAR(r13) | |
598 | stw r9,PACA_EXGEN+EX_CCR(r13) | |
599 | std r10,PACA_EXGEN+EX_LR(r13) | |
600 | std r11,PACA_EXGEN+EX_SRR0(r13) | |
601 | bl .slb_allocate_user | |
602 | ||
603 | ld r10,PACA_EXGEN+EX_LR(r13) | |
604 | ld r3,PACA_EXGEN+EX_R3(r13) | |
605 | lwz r9,PACA_EXGEN+EX_CCR(r13) | |
606 | ld r11,PACA_EXGEN+EX_SRR0(r13) | |
607 | mtlr r10 | |
608 | beq- slb_miss_fault | |
609 | ||
610 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | |
611 | beq- unrecov_user_slb | |
612 | mfmsr r10 | |
613 | ||
614 | .machine push | |
615 | .machine "power4" | |
616 | mtcrf 0x80,r9 | |
617 | .machine pop | |
618 | ||
619 | clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */ | |
620 | mtmsrd r10,1 | |
621 | ||
622 | mtspr SRR0,r11 | |
623 | mtspr SRR1,r12 | |
624 | ||
625 | ld r9,PACA_EXGEN+EX_R9(r13) | |
626 | ld r10,PACA_EXGEN+EX_R10(r13) | |
627 | ld r11,PACA_EXGEN+EX_R11(r13) | |
628 | ld r12,PACA_EXGEN+EX_R12(r13) | |
629 | ld r13,PACA_EXGEN+EX_R13(r13) | |
630 | rfid | |
631 | b . | |
632 | ||
633 | slb_miss_fault: | |
634 | EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN) | |
635 | ld r4,PACA_EXGEN+EX_DAR(r13) | |
636 | li r5,0 | |
637 | std r4,_DAR(r1) | |
638 | std r5,_DSISR(r1) | |
639 | b handle_page_fault | |
640 | ||
641 | unrecov_user_slb: | |
642 | EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN) | |
643 | DISABLE_INTS | |
644 | bl .save_nvgprs | |
645 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
646 | bl .unrecoverable_exception | |
647 | b 1b | |
648 | ||
649 | #endif /* __DISABLED__ */ | |
650 | ||
651 | ||
652 | /* | |
653 | * r13 points to the PACA, r9 contains the saved CR, | |
654 | * r12 contain the saved SRR1, SRR0 is still ready for return | |
655 | * r3 has the faulting address | |
656 | * r9 - r13 are saved in paca->exslb. | |
657 | * r3 is saved in paca->slb_r3 | |
658 | * We assume we aren't going to take any exceptions during this procedure. | |
659 | */ | |
660 | _GLOBAL(slb_miss_realmode) | |
661 | mflr r10 | |
662 | #ifdef CONFIG_RELOCATABLE | |
663 | mtctr r11 | |
664 | #endif | |
665 | ||
666 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | |
667 | std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ | |
668 | ||
669 | bl .slb_allocate_realmode | |
670 | ||
671 | /* All done -- return from exception. */ | |
672 | ||
673 | ld r10,PACA_EXSLB+EX_LR(r13) | |
674 | ld r3,PACA_EXSLB+EX_R3(r13) | |
675 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | |
0ebc4cda BH |
676 | |
677 | mtlr r10 | |
678 | ||
679 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | |
680 | beq- 2f | |
681 | ||
682 | .machine push | |
683 | .machine "power4" | |
684 | mtcrf 0x80,r9 | |
685 | mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ | |
686 | .machine pop | |
687 | ||
0ebc4cda BH |
688 | ld r9,PACA_EXSLB+EX_R9(r13) |
689 | ld r10,PACA_EXSLB+EX_R10(r13) | |
690 | ld r11,PACA_EXSLB+EX_R11(r13) | |
691 | ld r12,PACA_EXSLB+EX_R12(r13) | |
692 | ld r13,PACA_EXSLB+EX_R13(r13) | |
693 | rfid | |
694 | b . /* prevent speculative execution */ | |
695 | ||
4f8cf36f | 696 | 2: mfspr r11,SPRN_SRR0 |
0ebc4cda BH |
697 | ld r10,PACAKBASE(r13) |
698 | LOAD_HANDLER(r10,unrecov_slb) | |
699 | mtspr SPRN_SRR0,r10 | |
700 | ld r10,PACAKMSR(r13) | |
701 | mtspr SPRN_SRR1,r10 | |
702 | rfid | |
703 | b . | |
704 | ||
705 | unrecov_slb: | |
706 | EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) | |
707 | DISABLE_INTS | |
708 | bl .save_nvgprs | |
709 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
710 | bl .unrecoverable_exception | |
711 | b 1b | |
712 | ||
0ebc4cda BH |
713 | |
714 | #ifdef CONFIG_PPC_970_NAP | |
715 | power4_fixup_nap: | |
716 | andc r9,r9,r10 | |
717 | std r9,TI_LOCAL_FLAGS(r11) | |
718 | ld r10,_LINK(r1) /* make idle task do the */ | |
719 | std r10,_NIP(r1) /* equivalent of a blr */ | |
720 | blr | |
721 | #endif | |
722 | ||
723 | .align 7 | |
724 | .globl alignment_common | |
725 | alignment_common: | |
726 | mfspr r10,SPRN_DAR | |
727 | std r10,PACA_EXGEN+EX_DAR(r13) | |
728 | mfspr r10,SPRN_DSISR | |
729 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
730 | EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) | |
731 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
732 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
733 | std r3,_DAR(r1) | |
734 | std r4,_DSISR(r1) | |
735 | bl .save_nvgprs | |
736 | addi r3,r1,STACK_FRAME_OVERHEAD | |
737 | ENABLE_INTS | |
738 | bl .alignment_exception | |
739 | b .ret_from_except | |
740 | ||
741 | .align 7 | |
742 | .globl program_check_common | |
743 | program_check_common: | |
744 | EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) | |
745 | bl .save_nvgprs | |
54321242 | 746 | DISABLE_INTS |
922b9f86 | 747 | addi r3,r1,STACK_FRAME_OVERHEAD |
0ebc4cda BH |
748 | bl .program_check_exception |
749 | b .ret_from_except | |
750 | ||
751 | .align 7 | |
752 | .globl fp_unavailable_common | |
753 | fp_unavailable_common: | |
754 | EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) | |
755 | bne 1f /* if from user, just load it up */ | |
756 | bl .save_nvgprs | |
757 | addi r3,r1,STACK_FRAME_OVERHEAD | |
758 | ENABLE_INTS | |
759 | bl .kernel_fp_unavailable_exception | |
760 | BUG_OPCODE | |
761 | 1: bl .load_up_fpu | |
762 | b fast_exception_return | |
763 | ||
764 | .align 7 | |
765 | .globl altivec_unavailable_common | |
766 | altivec_unavailable_common: | |
767 | EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) | |
768 | #ifdef CONFIG_ALTIVEC | |
769 | BEGIN_FTR_SECTION | |
770 | beq 1f | |
771 | bl .load_up_altivec | |
772 | b fast_exception_return | |
773 | 1: | |
774 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
775 | #endif | |
776 | bl .save_nvgprs | |
777 | addi r3,r1,STACK_FRAME_OVERHEAD | |
778 | ENABLE_INTS | |
779 | bl .altivec_unavailable_exception | |
780 | b .ret_from_except | |
781 | ||
782 | .align 7 | |
783 | .globl vsx_unavailable_common | |
784 | vsx_unavailable_common: | |
785 | EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) | |
786 | #ifdef CONFIG_VSX | |
787 | BEGIN_FTR_SECTION | |
788 | bne .load_up_vsx | |
789 | 1: | |
790 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
791 | #endif | |
792 | bl .save_nvgprs | |
793 | addi r3,r1,STACK_FRAME_OVERHEAD | |
794 | ENABLE_INTS | |
795 | bl .vsx_unavailable_exception | |
796 | b .ret_from_except | |
797 | ||
798 | .align 7 | |
799 | .globl __end_handlers | |
800 | __end_handlers: | |
801 | ||
802 | /* | |
803 | * Return from an exception with minimal checks. | |
804 | * The caller is assumed to have done EXCEPTION_PROLOG_COMMON. | |
805 | * If interrupts have been enabled, or anything has been | |
806 | * done that might have changed the scheduling status of | |
807 | * any task or sent any task a signal, you should use | |
808 | * ret_from_except or ret_from_except_lite instead of this. | |
809 | */ | |
810 | fast_exc_return_irq: /* restores irq state too */ | |
811 | ld r3,SOFTE(r1) | |
812 | TRACE_AND_RESTORE_IRQ(r3); | |
813 | ld r12,_MSR(r1) | |
814 | rldicl r4,r12,49,63 /* get MSR_EE to LSB */ | |
815 | stb r4,PACAHARDIRQEN(r13) /* restore paca->hard_enabled */ | |
816 | b 1f | |
817 | ||
818 | .globl fast_exception_return | |
819 | fast_exception_return: | |
820 | ld r12,_MSR(r1) | |
821 | 1: ld r11,_NIP(r1) | |
822 | andi. r3,r12,MSR_RI /* check if RI is set */ | |
823 | beq- unrecov_fer | |
824 | ||
825 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING | |
826 | andi. r3,r12,MSR_PR | |
827 | beq 2f | |
828 | ACCOUNT_CPU_USER_EXIT(r3, r4) | |
829 | 2: | |
830 | #endif | |
831 | ||
832 | ld r3,_CCR(r1) | |
833 | ld r4,_LINK(r1) | |
834 | ld r5,_CTR(r1) | |
835 | ld r6,_XER(r1) | |
836 | mtcr r3 | |
837 | mtlr r4 | |
838 | mtctr r5 | |
839 | mtxer r6 | |
840 | REST_GPR(0, r1) | |
841 | REST_8GPRS(2, r1) | |
842 | ||
843 | mfmsr r10 | |
844 | rldicl r10,r10,48,1 /* clear EE */ | |
845 | rldicr r10,r10,16,61 /* clear RI (LE is 0 already) */ | |
846 | mtmsrd r10,1 | |
847 | ||
848 | mtspr SPRN_SRR1,r12 | |
849 | mtspr SPRN_SRR0,r11 | |
850 | REST_4GPRS(10, r1) | |
851 | ld r1,GPR1(r1) | |
852 | rfid | |
853 | b . /* prevent speculative execution */ | |
854 | ||
855 | unrecov_fer: | |
856 | bl .save_nvgprs | |
857 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
858 | bl .unrecoverable_exception | |
859 | b 1b | |
860 | ||
861 | ||
862 | /* | |
863 | * Hash table stuff | |
864 | */ | |
865 | .align 7 | |
866 | _STATIC(do_hash_page) | |
867 | std r3,_DAR(r1) | |
868 | std r4,_DSISR(r1) | |
869 | ||
9c7cc234 | 870 | andis. r0,r4,0xa410 /* weird error? */ |
0ebc4cda | 871 | bne- handle_page_fault /* if not, try to insert a HPTE */ |
9c7cc234 P |
872 | andis. r0,r4,DSISR_DABRMATCH@h |
873 | bne- handle_dabr_fault | |
874 | ||
0ebc4cda BH |
875 | BEGIN_FTR_SECTION |
876 | andis. r0,r4,0x0020 /* Is it a segment table fault? */ | |
877 | bne- do_ste_alloc /* If so handle it */ | |
44ae3ab3 | 878 | END_MMU_FTR_SECTION_IFCLR(MMU_FTR_SLB) |
0ebc4cda | 879 | |
9c1e1052 PM |
880 | clrrdi r11,r1,THREAD_SHIFT |
881 | lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ | |
882 | andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ | |
883 | bne 77f /* then don't call hash_page now */ | |
884 | ||
4f8cf36f | 885 | /* We run with interrupts both soft and hard disabled */ |
0ebc4cda BH |
886 | DISABLE_INTS |
887 | ||
888 | /* | |
889 | * Currently, trace_hardirqs_off() will be called by DISABLE_INTS | |
890 | * and will clobber volatile registers when irq tracing is enabled | |
891 | * so we need to reload them. It may be possible to be smarter here | |
892 | * and move the irq tracing elsewhere but let's keep it simple for | |
893 | * now | |
894 | */ | |
895 | #ifdef CONFIG_TRACE_IRQFLAGS | |
896 | ld r3,_DAR(r1) | |
897 | ld r4,_DSISR(r1) | |
898 | ld r5,_TRAP(r1) | |
899 | ld r12,_MSR(r1) | |
900 | clrrdi r5,r5,4 | |
901 | #endif /* CONFIG_TRACE_IRQFLAGS */ | |
902 | /* | |
903 | * We need to set the _PAGE_USER bit if MSR_PR is set or if we are | |
904 | * accessing a userspace segment (even from the kernel). We assume | |
905 | * kernel addresses always have the high bit set. | |
906 | */ | |
907 | rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */ | |
908 | rotldi r0,r3,15 /* Move high bit into MSR_PR posn */ | |
909 | orc r0,r12,r0 /* MSR_PR | ~high_bit */ | |
910 | rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */ | |
911 | ori r4,r4,1 /* add _PAGE_PRESENT */ | |
912 | rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */ | |
913 | ||
914 | /* | |
915 | * r3 contains the faulting address | |
916 | * r4 contains the required access permissions | |
917 | * r5 contains the trap number | |
918 | * | |
919 | * at return r3 = 0 for success | |
920 | */ | |
921 | bl .hash_page /* build HPTE if possible */ | |
922 | cmpdi r3,0 /* see if hash_page succeeded */ | |
923 | ||
0ebc4cda BH |
924 | /* |
925 | * Here we have interrupts hard-disabled, so it is sufficient | |
926 | * to restore paca->{soft,hard}_enable and get out. | |
927 | */ | |
928 | beq fast_exc_return_irq /* Return from exception on success */ | |
0ebc4cda BH |
929 | |
930 | /* For a hash failure, we don't bother re-enabling interrupts */ | |
931 | ble- 12f | |
932 | ||
933 | /* | |
934 | * hash_page couldn't handle it, set soft interrupt enable back | |
df9ee292 | 935 | * to what it was before the trap. Note that .arch_local_irq_restore |
0ebc4cda BH |
936 | * handles any interrupts pending at this point. |
937 | */ | |
938 | ld r3,SOFTE(r1) | |
939 | TRACE_AND_RESTORE_IRQ_PARTIAL(r3, 11f) | |
df9ee292 | 940 | bl .arch_local_irq_restore |
0ebc4cda BH |
941 | b 11f |
942 | ||
9c7cc234 P |
943 | /* We have a data breakpoint exception - handle it */ |
944 | handle_dabr_fault: | |
5aae8a53 | 945 | bl .save_nvgprs |
9c7cc234 P |
946 | ld r4,_DAR(r1) |
947 | ld r5,_DSISR(r1) | |
948 | addi r3,r1,STACK_FRAME_OVERHEAD | |
949 | bl .do_dabr | |
950 | b .ret_from_except_lite | |
951 | ||
0ebc4cda BH |
952 | /* Here we have a page fault that hash_page can't handle. */ |
953 | handle_page_fault: | |
954 | ENABLE_INTS | |
955 | 11: ld r4,_DAR(r1) | |
956 | ld r5,_DSISR(r1) | |
957 | addi r3,r1,STACK_FRAME_OVERHEAD | |
958 | bl .do_page_fault | |
959 | cmpdi r3,0 | |
960 | beq+ 13f | |
961 | bl .save_nvgprs | |
962 | mr r5,r3 | |
963 | addi r3,r1,STACK_FRAME_OVERHEAD | |
964 | lwz r4,_DAR(r1) | |
965 | bl .bad_page_fault | |
966 | b .ret_from_except | |
967 | ||
968 | 13: b .ret_from_except_lite | |
969 | ||
970 | /* We have a page fault that hash_page could handle but HV refused | |
971 | * the PTE insertion | |
972 | */ | |
973 | 12: bl .save_nvgprs | |
974 | mr r5,r3 | |
975 | addi r3,r1,STACK_FRAME_OVERHEAD | |
976 | ld r4,_DAR(r1) | |
977 | bl .low_hash_fault | |
978 | b .ret_from_except | |
979 | ||
9c1e1052 PM |
980 | /* |
981 | * We come here as a result of a DSI at a point where we don't want | |
982 | * to call hash_page, such as when we are accessing memory (possibly | |
983 | * user memory) inside a PMU interrupt that occurred while interrupts | |
984 | * were soft-disabled. We want to invoke the exception handler for | |
985 | * the access, or panic if there isn't a handler. | |
986 | */ | |
987 | 77: bl .save_nvgprs | |
988 | mr r4,r3 | |
989 | addi r3,r1,STACK_FRAME_OVERHEAD | |
990 | li r5,SIGSEGV | |
991 | bl .bad_page_fault | |
992 | b .ret_from_except | |
993 | ||
0ebc4cda BH |
994 | /* here we have a segment miss */ |
995 | do_ste_alloc: | |
996 | bl .ste_allocate /* try to insert stab entry */ | |
997 | cmpdi r3,0 | |
998 | bne- handle_page_fault | |
999 | b fast_exception_return | |
1000 | ||
1001 | /* | |
1002 | * r13 points to the PACA, r9 contains the saved CR, | |
1003 | * r11 and r12 contain the saved SRR0 and SRR1. | |
1004 | * r9 - r13 are saved in paca->exslb. | |
1005 | * We assume we aren't going to take any exceptions during this procedure. | |
1006 | * We assume (DAR >> 60) == 0xc. | |
1007 | */ | |
1008 | .align 7 | |
1009 | _GLOBAL(do_stab_bolted) | |
1010 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | |
1011 | std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */ | |
1012 | ||
1013 | /* Hash to the primary group */ | |
1014 | ld r10,PACASTABVIRT(r13) | |
1015 | mfspr r11,SPRN_DAR | |
1016 | srdi r11,r11,28 | |
1017 | rldimi r10,r11,7,52 /* r10 = first ste of the group */ | |
1018 | ||
1019 | /* Calculate VSID */ | |
1020 | /* This is a kernel address, so protovsid = ESID */ | |
1021 | ASM_VSID_SCRAMBLE(r11, r9, 256M) | |
1022 | rldic r9,r11,12,16 /* r9 = vsid << 12 */ | |
1023 | ||
1024 | /* Search the primary group for a free entry */ | |
1025 | 1: ld r11,0(r10) /* Test valid bit of the current ste */ | |
1026 | andi. r11,r11,0x80 | |
1027 | beq 2f | |
1028 | addi r10,r10,16 | |
1029 | andi. r11,r10,0x70 | |
1030 | bne 1b | |
1031 | ||
1032 | /* Stick for only searching the primary group for now. */ | |
1033 | /* At least for now, we use a very simple random castout scheme */ | |
1034 | /* Use the TB as a random number ; OR in 1 to avoid entry 0 */ | |
1035 | mftb r11 | |
1036 | rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */ | |
1037 | ori r11,r11,0x10 | |
1038 | ||
1039 | /* r10 currently points to an ste one past the group of interest */ | |
1040 | /* make it point to the randomly selected entry */ | |
1041 | subi r10,r10,128 | |
1042 | or r10,r10,r11 /* r10 is the entry to invalidate */ | |
1043 | ||
1044 | isync /* mark the entry invalid */ | |
1045 | ld r11,0(r10) | |
1046 | rldicl r11,r11,56,1 /* clear the valid bit */ | |
1047 | rotldi r11,r11,8 | |
1048 | std r11,0(r10) | |
1049 | sync | |
1050 | ||
1051 | clrrdi r11,r11,28 /* Get the esid part of the ste */ | |
1052 | slbie r11 | |
1053 | ||
1054 | 2: std r9,8(r10) /* Store the vsid part of the ste */ | |
1055 | eieio | |
1056 | ||
1057 | mfspr r11,SPRN_DAR /* Get the new esid */ | |
1058 | clrrdi r11,r11,28 /* Permits a full 32b of ESID */ | |
1059 | ori r11,r11,0x90 /* Turn on valid and kp */ | |
1060 | std r11,0(r10) /* Put new entry back into the stab */ | |
1061 | ||
1062 | sync | |
1063 | ||
1064 | /* All done -- return from exception. */ | |
1065 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | |
1066 | ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */ | |
1067 | ||
1068 | andi. r10,r12,MSR_RI | |
1069 | beq- unrecov_slb | |
1070 | ||
1071 | mtcrf 0x80,r9 /* restore CR */ | |
1072 | ||
1073 | mfmsr r10 | |
1074 | clrrdi r10,r10,2 | |
1075 | mtmsrd r10,1 | |
1076 | ||
1077 | mtspr SPRN_SRR0,r11 | |
1078 | mtspr SPRN_SRR1,r12 | |
1079 | ld r9,PACA_EXSLB+EX_R9(r13) | |
1080 | ld r10,PACA_EXSLB+EX_R10(r13) | |
1081 | ld r11,PACA_EXSLB+EX_R11(r13) | |
1082 | ld r12,PACA_EXSLB+EX_R12(r13) | |
1083 | ld r13,PACA_EXSLB+EX_R13(r13) | |
1084 | rfid | |
1085 | b . /* prevent speculative execution */ | |
1086 | ||
ed79ba9e | 1087 | #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) |
0ebc4cda BH |
1088 | /* |
1089 | * Data area reserved for FWNMI option. | |
1090 | * This address (0x7000) is fixed by the RPA. | |
1091 | */ | |
1092 | .= 0x7000 | |
1093 | .globl fwnmi_data_area | |
1094 | fwnmi_data_area: | |
0ebc4cda | 1095 | |
ed79ba9e BH |
1096 | /* pseries and powernv need to keep the whole page from |
1097 | * 0x7000 to 0x8000 free for use by the firmware | |
1098 | */ | |
0ebc4cda | 1099 | . = 0x8000 |
ed79ba9e | 1100 | #endif /* defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) */ |
84493804 | 1101 | |
4f8cf36f BH |
1102 | /* Space for CPU0's segment table */ |
1103 | .balign 4096 | |
84493804 BH |
1104 | .globl initial_stab |
1105 | initial_stab: | |
1106 | .space 4096 | |
4f8cf36f | 1107 | |
ed79ba9e BH |
1108 | #ifdef CONFIG_PPC_POWERNV |
1109 | _GLOBAL(opal_mc_secondary_handler) | |
1110 | HMT_MEDIUM | |
1111 | SET_SCRATCH0(r13) | |
1112 | GET_PACA(r13) | |
1113 | clrldi r3,r3,2 | |
1114 | tovirt(r3,r3) | |
1115 | std r3,PACA_OPAL_MC_EVT(r13) | |
1116 | ld r13,OPAL_MC_SRR0(r3) | |
1117 | mtspr SPRN_SRR0,r13 | |
1118 | ld r13,OPAL_MC_SRR1(r3) | |
1119 | mtspr SPRN_SRR1,r13 | |
1120 | ld r3,OPAL_MC_GPR3(r3) | |
1121 | GET_SCRATCH0(r13) | |
1122 | b machine_check_pSeries | |
1123 | #endif /* CONFIG_PPC_POWERNV */ |