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14cf11af PM |
1 | /* |
2 | * arch/ppc64/kernel/head.S | |
3 | * | |
4 | * PowerPC version | |
5 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
6 | * | |
7 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP | |
8 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> | |
9 | * Adapted for Power Macintosh by Paul Mackerras. | |
10 | * Low-level exception handlers and MMU support | |
11 | * rewritten by Paul Mackerras. | |
12 | * Copyright (C) 1996 Paul Mackerras. | |
13 | * | |
14 | * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and | |
15 | * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com | |
16 | * | |
17 | * This file contains the low-level support and setup for the | |
18 | * PowerPC-64 platform, including trap and interrupt dispatch. | |
19 | * | |
20 | * This program is free software; you can redistribute it and/or | |
21 | * modify it under the terms of the GNU General Public License | |
22 | * as published by the Free Software Foundation; either version | |
23 | * 2 of the License, or (at your option) any later version. | |
24 | */ | |
25 | ||
26 | #include <linux/config.h> | |
27 | #include <linux/threads.h> | |
b5bbeb23 | 28 | #include <asm/reg.h> |
14cf11af PM |
29 | #include <asm/page.h> |
30 | #include <asm/mmu.h> | |
14cf11af PM |
31 | #include <asm/ppc_asm.h> |
32 | #include <asm/asm-offsets.h> | |
33 | #include <asm/bug.h> | |
34 | #include <asm/cputable.h> | |
35 | #include <asm/setup.h> | |
36 | #include <asm/hvcall.h> | |
c43a55ff | 37 | #include <asm/iseries/lpar_map.h> |
6cb7bfeb | 38 | #include <asm/thread_info.h> |
14cf11af PM |
39 | |
40 | #ifdef CONFIG_PPC_ISERIES | |
41 | #define DO_SOFT_DISABLE | |
42 | #endif | |
43 | ||
44 | /* | |
45 | * We layout physical memory as follows: | |
46 | * 0x0000 - 0x00ff : Secondary processor spin code | |
47 | * 0x0100 - 0x2fff : pSeries Interrupt prologs | |
48 | * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs | |
49 | * 0x6000 - 0x6fff : Initial (CPU0) segment table | |
50 | * 0x7000 - 0x7fff : FWNMI data area | |
51 | * 0x8000 - : Early init and support code | |
52 | */ | |
53 | ||
54 | /* | |
55 | * SPRG Usage | |
56 | * | |
57 | * Register Definition | |
58 | * | |
59 | * SPRG0 reserved for hypervisor | |
60 | * SPRG1 temp - used to save gpr | |
61 | * SPRG2 temp - used to save gpr | |
62 | * SPRG3 virt addr of paca | |
63 | */ | |
64 | ||
65 | /* | |
66 | * Entering into this code we make the following assumptions: | |
67 | * For pSeries: | |
68 | * 1. The MMU is off & open firmware is running in real mode. | |
69 | * 2. The kernel is entered at __start | |
70 | * | |
71 | * For iSeries: | |
72 | * 1. The MMU is on (as it always is for iSeries) | |
73 | * 2. The kernel is entered at system_reset_iSeries | |
74 | */ | |
75 | ||
76 | .text | |
77 | .globl _stext | |
78 | _stext: | |
79 | #ifdef CONFIG_PPC_MULTIPLATFORM | |
80 | _GLOBAL(__start) | |
81 | /* NOP this out unconditionally */ | |
82 | BEGIN_FTR_SECTION | |
b85a046a | 83 | b .__start_initialization_multiplatform |
14cf11af PM |
84 | END_FTR_SECTION(0, 1) |
85 | #endif /* CONFIG_PPC_MULTIPLATFORM */ | |
86 | ||
87 | /* Catch branch to 0 in real mode */ | |
88 | trap | |
89 | ||
90 | #ifdef CONFIG_PPC_ISERIES | |
91 | /* | |
92 | * At offset 0x20, there is a pointer to iSeries LPAR data. | |
93 | * This is required by the hypervisor | |
94 | */ | |
95 | . = 0x20 | |
96 | .llong hvReleaseData-KERNELBASE | |
97 | ||
98 | /* | |
99 | * At offset 0x28 and 0x30 are offsets to the mschunks_map | |
100 | * array (used by the iSeries LPAR debugger to do translation | |
101 | * between physical addresses and absolute addresses) and | |
102 | * to the pidhash table (also used by the debugger) | |
103 | */ | |
104 | .llong mschunks_map-KERNELBASE | |
105 | .llong 0 /* pidhash-KERNELBASE SFRXXX */ | |
106 | ||
107 | /* Offset 0x38 - Pointer to start of embedded System.map */ | |
108 | .globl embedded_sysmap_start | |
109 | embedded_sysmap_start: | |
110 | .llong 0 | |
111 | /* Offset 0x40 - Pointer to end of embedded System.map */ | |
112 | .globl embedded_sysmap_end | |
113 | embedded_sysmap_end: | |
114 | .llong 0 | |
115 | ||
116 | #endif /* CONFIG_PPC_ISERIES */ | |
117 | ||
118 | /* Secondary processors spin on this value until it goes to 1. */ | |
119 | .globl __secondary_hold_spinloop | |
120 | __secondary_hold_spinloop: | |
121 | .llong 0x0 | |
122 | ||
123 | /* Secondary processors write this value with their cpu # */ | |
124 | /* after they enter the spin loop immediately below. */ | |
125 | .globl __secondary_hold_acknowledge | |
126 | __secondary_hold_acknowledge: | |
127 | .llong 0x0 | |
128 | ||
129 | . = 0x60 | |
130 | /* | |
131 | * The following code is used on pSeries to hold secondary processors | |
132 | * in a spin loop after they have been freed from OpenFirmware, but | |
133 | * before the bulk of the kernel has been relocated. This code | |
134 | * is relocated to physical address 0x60 before prom_init is run. | |
135 | * All of it must fit below the first exception vector at 0x100. | |
136 | */ | |
137 | _GLOBAL(__secondary_hold) | |
138 | mfmsr r24 | |
139 | ori r24,r24,MSR_RI | |
140 | mtmsrd r24 /* RI on */ | |
141 | ||
142 | /* Grab our linux cpu number */ | |
143 | mr r24,r3 | |
144 | ||
145 | /* Tell the master cpu we're here */ | |
146 | /* Relocation is off & we are located at an address less */ | |
147 | /* than 0x100, so only need to grab low order offset. */ | |
148 | std r24,__secondary_hold_acknowledge@l(0) | |
149 | sync | |
150 | ||
151 | /* All secondary cpus wait here until told to start. */ | |
152 | 100: ld r4,__secondary_hold_spinloop@l(0) | |
153 | cmpdi 0,r4,1 | |
154 | bne 100b | |
155 | ||
156 | #ifdef CONFIG_HMT | |
e58c3495 | 157 | SET_REG_IMMEDIATE(r4, .hmt_init) |
758438a7 ME |
158 | mtctr r4 |
159 | bctr | |
14cf11af PM |
160 | #else |
161 | #ifdef CONFIG_SMP | |
e58c3495 | 162 | LOAD_REG_IMMEDIATE(r4, .pSeries_secondary_smp_init) |
758438a7 | 163 | mtctr r4 |
14cf11af | 164 | mr r3,r24 |
758438a7 | 165 | bctr |
14cf11af PM |
166 | #else |
167 | BUG_OPCODE | |
168 | #endif | |
169 | #endif | |
170 | ||
171 | /* This value is used to mark exception frames on the stack. */ | |
172 | .section ".toc","aw" | |
173 | exception_marker: | |
174 | .tc ID_72656773_68657265[TC],0x7265677368657265 | |
175 | .text | |
176 | ||
177 | /* | |
178 | * The following macros define the code that appears as | |
179 | * the prologue to each of the exception handlers. They | |
180 | * are split into two parts to allow a single kernel binary | |
181 | * to be used for pSeries and iSeries. | |
182 | * LOL. One day... - paulus | |
183 | */ | |
184 | ||
185 | /* | |
186 | * We make as much of the exception code common between native | |
187 | * exception handlers (including pSeries LPAR) and iSeries LPAR | |
188 | * implementations as possible. | |
189 | */ | |
190 | ||
191 | /* | |
192 | * This is the start of the interrupt handlers for pSeries | |
193 | * This code runs with relocation off. | |
194 | */ | |
195 | #define EX_R9 0 | |
196 | #define EX_R10 8 | |
197 | #define EX_R11 16 | |
198 | #define EX_R12 24 | |
199 | #define EX_R13 32 | |
200 | #define EX_SRR0 40 | |
14cf11af | 201 | #define EX_DAR 48 |
14cf11af PM |
202 | #define EX_DSISR 56 |
203 | #define EX_CCR 60 | |
3c726f8d BH |
204 | #define EX_R3 64 |
205 | #define EX_LR 72 | |
14cf11af | 206 | |
758438a7 | 207 | /* |
e58c3495 DG |
208 | * We're short on space and time in the exception prolog, so we can't |
209 | * use the normal SET_REG_IMMEDIATE macro. Normally we just need the | |
210 | * low halfword of the address, but for Kdump we need the whole low | |
211 | * word. | |
758438a7 ME |
212 | */ |
213 | #ifdef CONFIG_CRASH_DUMP | |
214 | #define LOAD_HANDLER(reg, label) \ | |
215 | oris reg,reg,(label)@h; /* virt addr of handler ... */ \ | |
216 | ori reg,reg,(label)@l; /* .. and the rest */ | |
217 | #else | |
218 | #define LOAD_HANDLER(reg, label) \ | |
219 | ori reg,reg,(label)@l; /* virt addr of handler ... */ | |
220 | #endif | |
221 | ||
14cf11af | 222 | #define EXCEPTION_PROLOG_PSERIES(area, label) \ |
b5bbeb23 | 223 | mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ |
14cf11af PM |
224 | std r9,area+EX_R9(r13); /* save r9 - r12 */ \ |
225 | std r10,area+EX_R10(r13); \ | |
226 | std r11,area+EX_R11(r13); \ | |
227 | std r12,area+EX_R12(r13); \ | |
b5bbeb23 | 228 | mfspr r9,SPRN_SPRG1; \ |
14cf11af PM |
229 | std r9,area+EX_R13(r13); \ |
230 | mfcr r9; \ | |
231 | clrrdi r12,r13,32; /* get high part of &label */ \ | |
232 | mfmsr r10; \ | |
b5bbeb23 | 233 | mfspr r11,SPRN_SRR0; /* save SRR0 */ \ |
758438a7 | 234 | LOAD_HANDLER(r12,label) \ |
14cf11af | 235 | ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ |
b5bbeb23 PM |
236 | mtspr SPRN_SRR0,r12; \ |
237 | mfspr r12,SPRN_SRR1; /* and SRR1 */ \ | |
238 | mtspr SPRN_SRR1,r10; \ | |
14cf11af PM |
239 | rfid; \ |
240 | b . /* prevent speculative execution */ | |
241 | ||
242 | /* | |
243 | * This is the start of the interrupt handlers for iSeries | |
244 | * This code runs with relocation on. | |
245 | */ | |
246 | #define EXCEPTION_PROLOG_ISERIES_1(area) \ | |
b5bbeb23 | 247 | mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ |
14cf11af PM |
248 | std r9,area+EX_R9(r13); /* save r9 - r12 */ \ |
249 | std r10,area+EX_R10(r13); \ | |
250 | std r11,area+EX_R11(r13); \ | |
251 | std r12,area+EX_R12(r13); \ | |
b5bbeb23 | 252 | mfspr r9,SPRN_SPRG1; \ |
14cf11af PM |
253 | std r9,area+EX_R13(r13); \ |
254 | mfcr r9 | |
255 | ||
256 | #define EXCEPTION_PROLOG_ISERIES_2 \ | |
257 | mfmsr r10; \ | |
3356bb9f DG |
258 | ld r12,PACALPPACAPTR(r13); \ |
259 | ld r11,LPPACASRR0(r12); \ | |
260 | ld r12,LPPACASRR1(r12); \ | |
14cf11af PM |
261 | ori r10,r10,MSR_RI; \ |
262 | mtmsrd r10,1 | |
263 | ||
264 | /* | |
265 | * The common exception prolog is used for all except a few exceptions | |
266 | * such as a segment miss on a kernel address. We have to be prepared | |
267 | * to take another exception from the point where we first touch the | |
268 | * kernel stack onwards. | |
269 | * | |
270 | * On entry r13 points to the paca, r9-r13 are saved in the paca, | |
271 | * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and | |
272 | * SRR1, and relocation is on. | |
273 | */ | |
274 | #define EXCEPTION_PROLOG_COMMON(n, area) \ | |
275 | andi. r10,r12,MSR_PR; /* See if coming from user */ \ | |
276 | mr r10,r1; /* Save r1 */ \ | |
277 | subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ | |
278 | beq- 1f; \ | |
279 | ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ | |
280 | 1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \ | |
281 | bge- cr1,bad_stack; /* abort if it is */ \ | |
282 | std r9,_CCR(r1); /* save CR in stackframe */ \ | |
283 | std r11,_NIP(r1); /* save SRR0 in stackframe */ \ | |
284 | std r12,_MSR(r1); /* save SRR1 in stackframe */ \ | |
285 | std r10,0(r1); /* make stack chain pointer */ \ | |
286 | std r0,GPR0(r1); /* save r0 in stackframe */ \ | |
287 | std r10,GPR1(r1); /* save r1 in stackframe */ \ | |
288 | std r2,GPR2(r1); /* save r2 in stackframe */ \ | |
289 | SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ | |
290 | SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ | |
291 | ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ | |
292 | ld r10,area+EX_R10(r13); \ | |
293 | std r9,GPR9(r1); \ | |
294 | std r10,GPR10(r1); \ | |
295 | ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ | |
296 | ld r10,area+EX_R12(r13); \ | |
297 | ld r11,area+EX_R13(r13); \ | |
298 | std r9,GPR11(r1); \ | |
299 | std r10,GPR12(r1); \ | |
300 | std r11,GPR13(r1); \ | |
301 | ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ | |
302 | mflr r9; /* save LR in stackframe */ \ | |
303 | std r9,_LINK(r1); \ | |
304 | mfctr r10; /* save CTR in stackframe */ \ | |
305 | std r10,_CTR(r1); \ | |
b5bbeb23 | 306 | mfspr r11,SPRN_XER; /* save XER in stackframe */ \ |
14cf11af PM |
307 | std r11,_XER(r1); \ |
308 | li r9,(n)+1; \ | |
309 | std r9,_TRAP(r1); /* set trap number */ \ | |
310 | li r10,0; \ | |
311 | ld r11,exception_marker@toc(r2); \ | |
312 | std r10,RESULT(r1); /* clear regs->result */ \ | |
313 | std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ | |
314 | ||
315 | /* | |
316 | * Exception vectors. | |
317 | */ | |
318 | #define STD_EXCEPTION_PSERIES(n, label) \ | |
319 | . = n; \ | |
320 | .globl label##_pSeries; \ | |
321 | label##_pSeries: \ | |
322 | HMT_MEDIUM; \ | |
b5bbeb23 | 323 | mtspr SPRN_SPRG1,r13; /* save r13 */ \ |
14cf11af PM |
324 | RUNLATCH_ON(r13); \ |
325 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common) | |
326 | ||
327 | #define STD_EXCEPTION_ISERIES(n, label, area) \ | |
328 | .globl label##_iSeries; \ | |
329 | label##_iSeries: \ | |
330 | HMT_MEDIUM; \ | |
b5bbeb23 | 331 | mtspr SPRN_SPRG1,r13; /* save r13 */ \ |
14cf11af PM |
332 | RUNLATCH_ON(r13); \ |
333 | EXCEPTION_PROLOG_ISERIES_1(area); \ | |
334 | EXCEPTION_PROLOG_ISERIES_2; \ | |
335 | b label##_common | |
336 | ||
337 | #define MASKABLE_EXCEPTION_ISERIES(n, label) \ | |
338 | .globl label##_iSeries; \ | |
339 | label##_iSeries: \ | |
340 | HMT_MEDIUM; \ | |
b5bbeb23 | 341 | mtspr SPRN_SPRG1,r13; /* save r13 */ \ |
14cf11af PM |
342 | RUNLATCH_ON(r13); \ |
343 | EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \ | |
344 | lbz r10,PACAPROCENABLED(r13); \ | |
345 | cmpwi 0,r10,0; \ | |
346 | beq- label##_iSeries_masked; \ | |
347 | EXCEPTION_PROLOG_ISERIES_2; \ | |
348 | b label##_common; \ | |
349 | ||
350 | #ifdef DO_SOFT_DISABLE | |
351 | #define DISABLE_INTS \ | |
352 | lbz r10,PACAPROCENABLED(r13); \ | |
353 | li r11,0; \ | |
354 | std r10,SOFTE(r1); \ | |
355 | mfmsr r10; \ | |
356 | stb r11,PACAPROCENABLED(r13); \ | |
357 | ori r10,r10,MSR_EE; \ | |
358 | mtmsrd r10,1 | |
359 | ||
360 | #define ENABLE_INTS \ | |
361 | lbz r10,PACAPROCENABLED(r13); \ | |
362 | mfmsr r11; \ | |
363 | std r10,SOFTE(r1); \ | |
364 | ori r11,r11,MSR_EE; \ | |
365 | mtmsrd r11,1 | |
366 | ||
367 | #else /* hard enable/disable interrupts */ | |
368 | #define DISABLE_INTS | |
369 | ||
370 | #define ENABLE_INTS \ | |
371 | ld r12,_MSR(r1); \ | |
372 | mfmsr r11; \ | |
373 | rlwimi r11,r12,0,MSR_EE; \ | |
374 | mtmsrd r11,1 | |
375 | ||
376 | #endif | |
377 | ||
378 | #define STD_EXCEPTION_COMMON(trap, label, hdlr) \ | |
379 | .align 7; \ | |
380 | .globl label##_common; \ | |
381 | label##_common: \ | |
382 | EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ | |
383 | DISABLE_INTS; \ | |
384 | bl .save_nvgprs; \ | |
385 | addi r3,r1,STACK_FRAME_OVERHEAD; \ | |
386 | bl hdlr; \ | |
387 | b .ret_from_except | |
388 | ||
389 | #define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \ | |
390 | .align 7; \ | |
391 | .globl label##_common; \ | |
392 | label##_common: \ | |
393 | EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ | |
394 | DISABLE_INTS; \ | |
395 | addi r3,r1,STACK_FRAME_OVERHEAD; \ | |
396 | bl hdlr; \ | |
397 | b .ret_from_except_lite | |
398 | ||
399 | /* | |
400 | * Start of pSeries system interrupt routines | |
401 | */ | |
402 | . = 0x100 | |
403 | .globl __start_interrupts | |
404 | __start_interrupts: | |
405 | ||
406 | STD_EXCEPTION_PSERIES(0x100, system_reset) | |
407 | ||
408 | . = 0x200 | |
409 | _machine_check_pSeries: | |
410 | HMT_MEDIUM | |
b5bbeb23 | 411 | mtspr SPRN_SPRG1,r13 /* save r13 */ |
14cf11af PM |
412 | RUNLATCH_ON(r13) |
413 | EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) | |
414 | ||
415 | . = 0x300 | |
416 | .globl data_access_pSeries | |
417 | data_access_pSeries: | |
418 | HMT_MEDIUM | |
b5bbeb23 | 419 | mtspr SPRN_SPRG1,r13 |
14cf11af | 420 | BEGIN_FTR_SECTION |
b5bbeb23 PM |
421 | mtspr SPRN_SPRG2,r12 |
422 | mfspr r13,SPRN_DAR | |
423 | mfspr r12,SPRN_DSISR | |
14cf11af PM |
424 | srdi r13,r13,60 |
425 | rlwimi r13,r12,16,0x20 | |
426 | mfcr r12 | |
427 | cmpwi r13,0x2c | |
428 | beq .do_stab_bolted_pSeries | |
429 | mtcrf 0x80,r12 | |
b5bbeb23 | 430 | mfspr r12,SPRN_SPRG2 |
14cf11af PM |
431 | END_FTR_SECTION_IFCLR(CPU_FTR_SLB) |
432 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common) | |
433 | ||
434 | . = 0x380 | |
435 | .globl data_access_slb_pSeries | |
436 | data_access_slb_pSeries: | |
437 | HMT_MEDIUM | |
b5bbeb23 | 438 | mtspr SPRN_SPRG1,r13 |
14cf11af | 439 | RUNLATCH_ON(r13) |
b5bbeb23 | 440 | mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ |
3c726f8d BH |
441 | std r3,PACA_EXSLB+EX_R3(r13) |
442 | mfspr r3,SPRN_DAR | |
14cf11af | 443 | std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ |
3c726f8d BH |
444 | mfcr r9 |
445 | #ifdef __DISABLED__ | |
446 | /* Keep that around for when we re-implement dynamic VSIDs */ | |
447 | cmpdi r3,0 | |
448 | bge slb_miss_user_pseries | |
449 | #endif /* __DISABLED__ */ | |
14cf11af PM |
450 | std r10,PACA_EXSLB+EX_R10(r13) |
451 | std r11,PACA_EXSLB+EX_R11(r13) | |
452 | std r12,PACA_EXSLB+EX_R12(r13) | |
3c726f8d BH |
453 | mfspr r10,SPRN_SPRG1 |
454 | std r10,PACA_EXSLB+EX_R13(r13) | |
b5bbeb23 | 455 | mfspr r12,SPRN_SRR1 /* and SRR1 */ |
3c726f8d | 456 | b .slb_miss_realmode /* Rel. branch works in real mode */ |
14cf11af PM |
457 | |
458 | STD_EXCEPTION_PSERIES(0x400, instruction_access) | |
459 | ||
460 | . = 0x480 | |
461 | .globl instruction_access_slb_pSeries | |
462 | instruction_access_slb_pSeries: | |
463 | HMT_MEDIUM | |
b5bbeb23 | 464 | mtspr SPRN_SPRG1,r13 |
14cf11af | 465 | RUNLATCH_ON(r13) |
b5bbeb23 | 466 | mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ |
3c726f8d BH |
467 | std r3,PACA_EXSLB+EX_R3(r13) |
468 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
14cf11af | 469 | std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ |
3c726f8d BH |
470 | mfcr r9 |
471 | #ifdef __DISABLED__ | |
472 | /* Keep that around for when we re-implement dynamic VSIDs */ | |
473 | cmpdi r3,0 | |
474 | bge slb_miss_user_pseries | |
475 | #endif /* __DISABLED__ */ | |
14cf11af PM |
476 | std r10,PACA_EXSLB+EX_R10(r13) |
477 | std r11,PACA_EXSLB+EX_R11(r13) | |
478 | std r12,PACA_EXSLB+EX_R12(r13) | |
3c726f8d BH |
479 | mfspr r10,SPRN_SPRG1 |
480 | std r10,PACA_EXSLB+EX_R13(r13) | |
b5bbeb23 | 481 | mfspr r12,SPRN_SRR1 /* and SRR1 */ |
3c726f8d | 482 | b .slb_miss_realmode /* Rel. branch works in real mode */ |
14cf11af PM |
483 | |
484 | STD_EXCEPTION_PSERIES(0x500, hardware_interrupt) | |
485 | STD_EXCEPTION_PSERIES(0x600, alignment) | |
486 | STD_EXCEPTION_PSERIES(0x700, program_check) | |
487 | STD_EXCEPTION_PSERIES(0x800, fp_unavailable) | |
488 | STD_EXCEPTION_PSERIES(0x900, decrementer) | |
489 | STD_EXCEPTION_PSERIES(0xa00, trap_0a) | |
490 | STD_EXCEPTION_PSERIES(0xb00, trap_0b) | |
491 | ||
492 | . = 0xc00 | |
493 | .globl system_call_pSeries | |
494 | system_call_pSeries: | |
495 | HMT_MEDIUM | |
496 | RUNLATCH_ON(r9) | |
497 | mr r9,r13 | |
498 | mfmsr r10 | |
b5bbeb23 PM |
499 | mfspr r13,SPRN_SPRG3 |
500 | mfspr r11,SPRN_SRR0 | |
14cf11af PM |
501 | clrrdi r12,r13,32 |
502 | oris r12,r12,system_call_common@h | |
503 | ori r12,r12,system_call_common@l | |
b5bbeb23 | 504 | mtspr SPRN_SRR0,r12 |
14cf11af | 505 | ori r10,r10,MSR_IR|MSR_DR|MSR_RI |
b5bbeb23 PM |
506 | mfspr r12,SPRN_SRR1 |
507 | mtspr SPRN_SRR1,r10 | |
14cf11af PM |
508 | rfid |
509 | b . /* prevent speculative execution */ | |
510 | ||
511 | STD_EXCEPTION_PSERIES(0xd00, single_step) | |
512 | STD_EXCEPTION_PSERIES(0xe00, trap_0e) | |
513 | ||
514 | /* We need to deal with the Altivec unavailable exception | |
515 | * here which is at 0xf20, thus in the middle of the | |
516 | * prolog code of the PerformanceMonitor one. A little | |
517 | * trickery is thus necessary | |
518 | */ | |
519 | . = 0xf00 | |
520 | b performance_monitor_pSeries | |
521 | ||
522 | STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable) | |
523 | ||
524 | STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint) | |
525 | STD_EXCEPTION_PSERIES(0x1700, altivec_assist) | |
526 | ||
527 | . = 0x3000 | |
528 | ||
529 | /*** pSeries interrupt support ***/ | |
530 | ||
531 | /* moved from 0xf00 */ | |
532 | STD_EXCEPTION_PSERIES(., performance_monitor) | |
533 | ||
534 | .align 7 | |
535 | _GLOBAL(do_stab_bolted_pSeries) | |
536 | mtcrf 0x80,r12 | |
b5bbeb23 | 537 | mfspr r12,SPRN_SPRG2 |
14cf11af PM |
538 | EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted) |
539 | ||
3c726f8d BH |
540 | /* |
541 | * We have some room here we use that to put | |
542 | * the peries slb miss user trampoline code so it's reasonably | |
543 | * away from slb_miss_user_common to avoid problems with rfid | |
544 | * | |
545 | * This is used for when the SLB miss handler has to go virtual, | |
546 | * which doesn't happen for now anymore but will once we re-implement | |
547 | * dynamic VSIDs for shared page tables | |
548 | */ | |
549 | #ifdef __DISABLED__ | |
550 | slb_miss_user_pseries: | |
551 | std r10,PACA_EXGEN+EX_R10(r13) | |
552 | std r11,PACA_EXGEN+EX_R11(r13) | |
553 | std r12,PACA_EXGEN+EX_R12(r13) | |
554 | mfspr r10,SPRG1 | |
555 | ld r11,PACA_EXSLB+EX_R9(r13) | |
556 | ld r12,PACA_EXSLB+EX_R3(r13) | |
557 | std r10,PACA_EXGEN+EX_R13(r13) | |
558 | std r11,PACA_EXGEN+EX_R9(r13) | |
559 | std r12,PACA_EXGEN+EX_R3(r13) | |
560 | clrrdi r12,r13,32 | |
561 | mfmsr r10 | |
562 | mfspr r11,SRR0 /* save SRR0 */ | |
563 | ori r12,r12,slb_miss_user_common@l /* virt addr of handler */ | |
564 | ori r10,r10,MSR_IR|MSR_DR|MSR_RI | |
565 | mtspr SRR0,r12 | |
566 | mfspr r12,SRR1 /* and SRR1 */ | |
567 | mtspr SRR1,r10 | |
568 | rfid | |
569 | b . /* prevent spec. execution */ | |
570 | #endif /* __DISABLED__ */ | |
571 | ||
14cf11af PM |
572 | /* |
573 | * Vectors for the FWNMI option. Share common code. | |
574 | */ | |
b5bbeb23 | 575 | .globl system_reset_fwnmi |
8c4f1f29 | 576 | .align 7 |
14cf11af | 577 | system_reset_fwnmi: |
b5bbeb23 PM |
578 | HMT_MEDIUM |
579 | mtspr SPRN_SPRG1,r13 /* save r13 */ | |
580 | RUNLATCH_ON(r13) | |
581 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common) | |
14cf11af | 582 | |
b5bbeb23 | 583 | .globl machine_check_fwnmi |
8c4f1f29 | 584 | .align 7 |
14cf11af | 585 | machine_check_fwnmi: |
b5bbeb23 PM |
586 | HMT_MEDIUM |
587 | mtspr SPRN_SPRG1,r13 /* save r13 */ | |
588 | RUNLATCH_ON(r13) | |
589 | EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) | |
14cf11af PM |
590 | |
591 | #ifdef CONFIG_PPC_ISERIES | |
592 | /*** ISeries-LPAR interrupt handlers ***/ | |
593 | ||
594 | STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC) | |
595 | ||
596 | .globl data_access_iSeries | |
597 | data_access_iSeries: | |
b5bbeb23 | 598 | mtspr SPRN_SPRG1,r13 |
14cf11af | 599 | BEGIN_FTR_SECTION |
b5bbeb23 PM |
600 | mtspr SPRN_SPRG2,r12 |
601 | mfspr r13,SPRN_DAR | |
602 | mfspr r12,SPRN_DSISR | |
14cf11af PM |
603 | srdi r13,r13,60 |
604 | rlwimi r13,r12,16,0x20 | |
605 | mfcr r12 | |
606 | cmpwi r13,0x2c | |
607 | beq .do_stab_bolted_iSeries | |
608 | mtcrf 0x80,r12 | |
b5bbeb23 | 609 | mfspr r12,SPRN_SPRG2 |
14cf11af PM |
610 | END_FTR_SECTION_IFCLR(CPU_FTR_SLB) |
611 | EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN) | |
612 | EXCEPTION_PROLOG_ISERIES_2 | |
613 | b data_access_common | |
614 | ||
615 | .do_stab_bolted_iSeries: | |
616 | mtcrf 0x80,r12 | |
b5bbeb23 | 617 | mfspr r12,SPRN_SPRG2 |
14cf11af PM |
618 | EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB) |
619 | EXCEPTION_PROLOG_ISERIES_2 | |
620 | b .do_stab_bolted | |
621 | ||
622 | .globl data_access_slb_iSeries | |
623 | data_access_slb_iSeries: | |
b5bbeb23 | 624 | mtspr SPRN_SPRG1,r13 /* save r13 */ |
3c726f8d | 625 | mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ |
14cf11af | 626 | std r3,PACA_EXSLB+EX_R3(r13) |
b5bbeb23 | 627 | mfspr r3,SPRN_DAR |
3c726f8d BH |
628 | std r9,PACA_EXSLB+EX_R9(r13) |
629 | mfcr r9 | |
630 | #ifdef __DISABLED__ | |
631 | cmpdi r3,0 | |
632 | bge slb_miss_user_iseries | |
633 | #endif | |
634 | std r10,PACA_EXSLB+EX_R10(r13) | |
635 | std r11,PACA_EXSLB+EX_R11(r13) | |
636 | std r12,PACA_EXSLB+EX_R12(r13) | |
637 | mfspr r10,SPRN_SPRG1 | |
638 | std r10,PACA_EXSLB+EX_R13(r13) | |
3356bb9f DG |
639 | ld r12,PACALPPACAPTR(r13) |
640 | ld r12,LPPACASRR1(r12) | |
3c726f8d | 641 | b .slb_miss_realmode |
14cf11af PM |
642 | |
643 | STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN) | |
644 | ||
645 | .globl instruction_access_slb_iSeries | |
646 | instruction_access_slb_iSeries: | |
b5bbeb23 | 647 | mtspr SPRN_SPRG1,r13 /* save r13 */ |
3c726f8d | 648 | mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ |
14cf11af | 649 | std r3,PACA_EXSLB+EX_R3(r13) |
3356bb9f DG |
650 | ld r3,PACALPPACAPTR(r13) |
651 | ld r3,LPPACASRR0(r3) /* get SRR0 value */ | |
3c726f8d BH |
652 | std r9,PACA_EXSLB+EX_R9(r13) |
653 | mfcr r9 | |
654 | #ifdef __DISABLED__ | |
655 | cmpdi r3,0 | |
656 | bge .slb_miss_user_iseries | |
657 | #endif | |
658 | std r10,PACA_EXSLB+EX_R10(r13) | |
659 | std r11,PACA_EXSLB+EX_R11(r13) | |
660 | std r12,PACA_EXSLB+EX_R12(r13) | |
661 | mfspr r10,SPRN_SPRG1 | |
662 | std r10,PACA_EXSLB+EX_R13(r13) | |
3356bb9f DG |
663 | ld r12,PACALPPACAPTR(r13) |
664 | ld r12,LPPACASRR1(r12) | |
3c726f8d BH |
665 | b .slb_miss_realmode |
666 | ||
667 | #ifdef __DISABLED__ | |
668 | slb_miss_user_iseries: | |
669 | std r10,PACA_EXGEN+EX_R10(r13) | |
670 | std r11,PACA_EXGEN+EX_R11(r13) | |
671 | std r12,PACA_EXGEN+EX_R12(r13) | |
672 | mfspr r10,SPRG1 | |
673 | ld r11,PACA_EXSLB+EX_R9(r13) | |
674 | ld r12,PACA_EXSLB+EX_R3(r13) | |
675 | std r10,PACA_EXGEN+EX_R13(r13) | |
676 | std r11,PACA_EXGEN+EX_R9(r13) | |
677 | std r12,PACA_EXGEN+EX_R3(r13) | |
678 | EXCEPTION_PROLOG_ISERIES_2 | |
679 | b slb_miss_user_common | |
680 | #endif | |
14cf11af PM |
681 | |
682 | MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt) | |
683 | STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN) | |
684 | STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN) | |
685 | STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN) | |
686 | MASKABLE_EXCEPTION_ISERIES(0x900, decrementer) | |
687 | STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN) | |
688 | STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN) | |
689 | ||
690 | .globl system_call_iSeries | |
691 | system_call_iSeries: | |
692 | mr r9,r13 | |
b5bbeb23 | 693 | mfspr r13,SPRN_SPRG3 |
14cf11af PM |
694 | EXCEPTION_PROLOG_ISERIES_2 |
695 | b system_call_common | |
696 | ||
697 | STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN) | |
698 | STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN) | |
699 | STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN) | |
700 | ||
701 | .globl system_reset_iSeries | |
702 | system_reset_iSeries: | |
b5bbeb23 | 703 | mfspr r13,SPRN_SPRG3 /* Get paca address */ |
14cf11af PM |
704 | mfmsr r24 |
705 | ori r24,r24,MSR_RI | |
706 | mtmsrd r24 /* RI on */ | |
707 | lhz r24,PACAPACAINDEX(r13) /* Get processor # */ | |
708 | cmpwi 0,r24,0 /* Are we processor 0? */ | |
709 | beq .__start_initialization_iSeries /* Start up the first processor */ | |
710 | mfspr r4,SPRN_CTRLF | |
711 | li r5,CTRL_RUNLATCH /* Turn off the run light */ | |
712 | andc r4,r4,r5 | |
713 | mtspr SPRN_CTRLT,r4 | |
714 | ||
715 | 1: | |
716 | HMT_LOW | |
717 | #ifdef CONFIG_SMP | |
718 | lbz r23,PACAPROCSTART(r13) /* Test if this processor | |
719 | * should start */ | |
720 | sync | |
e58c3495 | 721 | LOAD_REG_IMMEDIATE(r3,current_set) |
14cf11af PM |
722 | sldi r28,r24,3 /* get current_set[cpu#] */ |
723 | ldx r3,r3,r28 | |
724 | addi r1,r3,THREAD_SIZE | |
725 | subi r1,r1,STACK_FRAME_OVERHEAD | |
726 | ||
727 | cmpwi 0,r23,0 | |
728 | beq iSeries_secondary_smp_loop /* Loop until told to go */ | |
729 | bne .__secondary_start /* Loop until told to go */ | |
730 | iSeries_secondary_smp_loop: | |
731 | /* Let the Hypervisor know we are alive */ | |
732 | /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */ | |
733 | lis r3,0x8002 | |
734 | rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */ | |
735 | #else /* CONFIG_SMP */ | |
736 | /* Yield the processor. This is required for non-SMP kernels | |
737 | which are running on multi-threaded machines. */ | |
738 | lis r3,0x8000 | |
739 | rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */ | |
740 | addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */ | |
741 | li r4,0 /* "yield timed" */ | |
742 | li r5,-1 /* "yield forever" */ | |
743 | #endif /* CONFIG_SMP */ | |
744 | li r0,-1 /* r0=-1 indicates a Hypervisor call */ | |
745 | sc /* Invoke the hypervisor via a system call */ | |
b5bbeb23 | 746 | mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */ |
14cf11af PM |
747 | b 1b /* If SMP not configured, secondaries |
748 | * loop forever */ | |
749 | ||
750 | .globl decrementer_iSeries_masked | |
751 | decrementer_iSeries_masked: | |
752 | li r11,1 | |
3356bb9f DG |
753 | ld r12,PACALPPACAPTR(r13) |
754 | stb r11,LPPACADECRINT(r12) | |
e58c3495 DG |
755 | LOAD_REG_ADDRBASE(r12,tb_ticks_per_jiffy) |
756 | lwz r12,ADDROFF(tb_ticks_per_jiffy)(r12) | |
14cf11af PM |
757 | mtspr SPRN_DEC,r12 |
758 | /* fall through */ | |
759 | ||
760 | .globl hardware_interrupt_iSeries_masked | |
761 | hardware_interrupt_iSeries_masked: | |
762 | mtcrf 0x80,r9 /* Restore regs */ | |
3356bb9f DG |
763 | ld r12,PACALPPACAPTR(r13) |
764 | ld r11,LPPACASRR0(r12) | |
765 | ld r12,LPPACASRR1(r12) | |
b5bbeb23 PM |
766 | mtspr SPRN_SRR0,r11 |
767 | mtspr SPRN_SRR1,r12 | |
14cf11af PM |
768 | ld r9,PACA_EXGEN+EX_R9(r13) |
769 | ld r10,PACA_EXGEN+EX_R10(r13) | |
770 | ld r11,PACA_EXGEN+EX_R11(r13) | |
771 | ld r12,PACA_EXGEN+EX_R12(r13) | |
772 | ld r13,PACA_EXGEN+EX_R13(r13) | |
773 | rfid | |
774 | b . /* prevent speculative execution */ | |
775 | #endif /* CONFIG_PPC_ISERIES */ | |
776 | ||
777 | /*** Common interrupt handlers ***/ | |
778 | ||
779 | STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception) | |
780 | ||
781 | /* | |
782 | * Machine check is different because we use a different | |
783 | * save area: PACA_EXMC instead of PACA_EXGEN. | |
784 | */ | |
785 | .align 7 | |
786 | .globl machine_check_common | |
787 | machine_check_common: | |
788 | EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) | |
789 | DISABLE_INTS | |
790 | bl .save_nvgprs | |
791 | addi r3,r1,STACK_FRAME_OVERHEAD | |
792 | bl .machine_check_exception | |
793 | b .ret_from_except | |
794 | ||
795 | STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt) | |
796 | STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception) | |
797 | STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception) | |
798 | STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception) | |
799 | STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception) | |
800 | STD_EXCEPTION_COMMON(0xf00, performance_monitor, .performance_monitor_exception) | |
801 | STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception) | |
802 | #ifdef CONFIG_ALTIVEC | |
803 | STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception) | |
804 | #else | |
805 | STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception) | |
806 | #endif | |
807 | ||
808 | /* | |
809 | * Here we have detected that the kernel stack pointer is bad. | |
810 | * R9 contains the saved CR, r13 points to the paca, | |
811 | * r10 contains the (bad) kernel stack pointer, | |
812 | * r11 and r12 contain the saved SRR0 and SRR1. | |
813 | * We switch to using an emergency stack, save the registers there, | |
814 | * and call kernel_bad_stack(), which panics. | |
815 | */ | |
816 | bad_stack: | |
817 | ld r1,PACAEMERGSP(r13) | |
818 | subi r1,r1,64+INT_FRAME_SIZE | |
819 | std r9,_CCR(r1) | |
820 | std r10,GPR1(r1) | |
821 | std r11,_NIP(r1) | |
822 | std r12,_MSR(r1) | |
b5bbeb23 PM |
823 | mfspr r11,SPRN_DAR |
824 | mfspr r12,SPRN_DSISR | |
14cf11af PM |
825 | std r11,_DAR(r1) |
826 | std r12,_DSISR(r1) | |
827 | mflr r10 | |
828 | mfctr r11 | |
829 | mfxer r12 | |
830 | std r10,_LINK(r1) | |
831 | std r11,_CTR(r1) | |
832 | std r12,_XER(r1) | |
833 | SAVE_GPR(0,r1) | |
834 | SAVE_GPR(2,r1) | |
835 | SAVE_4GPRS(3,r1) | |
836 | SAVE_2GPRS(7,r1) | |
837 | SAVE_10GPRS(12,r1) | |
838 | SAVE_10GPRS(22,r1) | |
839 | addi r11,r1,INT_FRAME_SIZE | |
840 | std r11,0(r1) | |
841 | li r12,0 | |
842 | std r12,0(r11) | |
843 | ld r2,PACATOC(r13) | |
844 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
845 | bl .kernel_bad_stack | |
846 | b 1b | |
847 | ||
848 | /* | |
849 | * Return from an exception with minimal checks. | |
850 | * The caller is assumed to have done EXCEPTION_PROLOG_COMMON. | |
851 | * If interrupts have been enabled, or anything has been | |
852 | * done that might have changed the scheduling status of | |
853 | * any task or sent any task a signal, you should use | |
854 | * ret_from_except or ret_from_except_lite instead of this. | |
855 | */ | |
40ef8cbc | 856 | .globl fast_exception_return |
14cf11af PM |
857 | fast_exception_return: |
858 | ld r12,_MSR(r1) | |
859 | ld r11,_NIP(r1) | |
860 | andi. r3,r12,MSR_RI /* check if RI is set */ | |
861 | beq- unrecov_fer | |
862 | ld r3,_CCR(r1) | |
863 | ld r4,_LINK(r1) | |
864 | ld r5,_CTR(r1) | |
865 | ld r6,_XER(r1) | |
866 | mtcr r3 | |
867 | mtlr r4 | |
868 | mtctr r5 | |
869 | mtxer r6 | |
870 | REST_GPR(0, r1) | |
871 | REST_8GPRS(2, r1) | |
872 | ||
873 | mfmsr r10 | |
874 | clrrdi r10,r10,2 /* clear RI (LE is 0 already) */ | |
875 | mtmsrd r10,1 | |
876 | ||
b5bbeb23 PM |
877 | mtspr SPRN_SRR1,r12 |
878 | mtspr SPRN_SRR0,r11 | |
14cf11af PM |
879 | REST_4GPRS(10, r1) |
880 | ld r1,GPR1(r1) | |
881 | rfid | |
882 | b . /* prevent speculative execution */ | |
883 | ||
884 | unrecov_fer: | |
885 | bl .save_nvgprs | |
886 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
887 | bl .unrecoverable_exception | |
888 | b 1b | |
889 | ||
890 | /* | |
891 | * Here r13 points to the paca, r9 contains the saved CR, | |
892 | * SRR0 and SRR1 are saved in r11 and r12, | |
893 | * r9 - r13 are saved in paca->exgen. | |
894 | */ | |
895 | .align 7 | |
896 | .globl data_access_common | |
897 | data_access_common: | |
898 | RUNLATCH_ON(r10) /* It wont fit in the 0x300 handler */ | |
b5bbeb23 | 899 | mfspr r10,SPRN_DAR |
14cf11af | 900 | std r10,PACA_EXGEN+EX_DAR(r13) |
b5bbeb23 | 901 | mfspr r10,SPRN_DSISR |
14cf11af PM |
902 | stw r10,PACA_EXGEN+EX_DSISR(r13) |
903 | EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) | |
904 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
905 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
906 | li r5,0x300 | |
907 | b .do_hash_page /* Try to handle as hpte fault */ | |
908 | ||
909 | .align 7 | |
910 | .globl instruction_access_common | |
911 | instruction_access_common: | |
912 | EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) | |
913 | ld r3,_NIP(r1) | |
914 | andis. r4,r12,0x5820 | |
915 | li r5,0x400 | |
916 | b .do_hash_page /* Try to handle as hpte fault */ | |
917 | ||
3c726f8d BH |
918 | /* |
919 | * Here is the common SLB miss user that is used when going to virtual | |
920 | * mode for SLB misses, that is currently not used | |
921 | */ | |
922 | #ifdef __DISABLED__ | |
923 | .align 7 | |
924 | .globl slb_miss_user_common | |
925 | slb_miss_user_common: | |
926 | mflr r10 | |
927 | std r3,PACA_EXGEN+EX_DAR(r13) | |
928 | stw r9,PACA_EXGEN+EX_CCR(r13) | |
929 | std r10,PACA_EXGEN+EX_LR(r13) | |
930 | std r11,PACA_EXGEN+EX_SRR0(r13) | |
931 | bl .slb_allocate_user | |
932 | ||
933 | ld r10,PACA_EXGEN+EX_LR(r13) | |
934 | ld r3,PACA_EXGEN+EX_R3(r13) | |
935 | lwz r9,PACA_EXGEN+EX_CCR(r13) | |
936 | ld r11,PACA_EXGEN+EX_SRR0(r13) | |
937 | mtlr r10 | |
938 | beq- slb_miss_fault | |
939 | ||
940 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | |
941 | beq- unrecov_user_slb | |
942 | mfmsr r10 | |
943 | ||
944 | .machine push | |
945 | .machine "power4" | |
946 | mtcrf 0x80,r9 | |
947 | .machine pop | |
948 | ||
949 | clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */ | |
950 | mtmsrd r10,1 | |
951 | ||
952 | mtspr SRR0,r11 | |
953 | mtspr SRR1,r12 | |
954 | ||
955 | ld r9,PACA_EXGEN+EX_R9(r13) | |
956 | ld r10,PACA_EXGEN+EX_R10(r13) | |
957 | ld r11,PACA_EXGEN+EX_R11(r13) | |
958 | ld r12,PACA_EXGEN+EX_R12(r13) | |
959 | ld r13,PACA_EXGEN+EX_R13(r13) | |
960 | rfid | |
961 | b . | |
962 | ||
963 | slb_miss_fault: | |
964 | EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN) | |
965 | ld r4,PACA_EXGEN+EX_DAR(r13) | |
966 | li r5,0 | |
967 | std r4,_DAR(r1) | |
968 | std r5,_DSISR(r1) | |
969 | b .handle_page_fault | |
970 | ||
971 | unrecov_user_slb: | |
972 | EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN) | |
973 | DISABLE_INTS | |
974 | bl .save_nvgprs | |
975 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
976 | bl .unrecoverable_exception | |
977 | b 1b | |
978 | ||
979 | #endif /* __DISABLED__ */ | |
980 | ||
981 | ||
982 | /* | |
983 | * r13 points to the PACA, r9 contains the saved CR, | |
984 | * r12 contain the saved SRR1, SRR0 is still ready for return | |
985 | * r3 has the faulting address | |
986 | * r9 - r13 are saved in paca->exslb. | |
987 | * r3 is saved in paca->slb_r3 | |
988 | * We assume we aren't going to take any exceptions during this procedure. | |
989 | */ | |
990 | _GLOBAL(slb_miss_realmode) | |
991 | mflr r10 | |
992 | ||
993 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | |
994 | std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ | |
995 | ||
996 | bl .slb_allocate_realmode | |
997 | ||
998 | /* All done -- return from exception. */ | |
999 | ||
1000 | ld r10,PACA_EXSLB+EX_LR(r13) | |
1001 | ld r3,PACA_EXSLB+EX_R3(r13) | |
1002 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | |
1003 | #ifdef CONFIG_PPC_ISERIES | |
3356bb9f DG |
1004 | ld r11,PACALPPACAPTR(r13) |
1005 | ld r11,LPPACASRR0(r11) /* get SRR0 value */ | |
3c726f8d BH |
1006 | #endif /* CONFIG_PPC_ISERIES */ |
1007 | ||
1008 | mtlr r10 | |
1009 | ||
1010 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | |
1011 | beq- unrecov_slb | |
1012 | ||
1013 | .machine push | |
1014 | .machine "power4" | |
1015 | mtcrf 0x80,r9 | |
1016 | mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ | |
1017 | .machine pop | |
1018 | ||
1019 | #ifdef CONFIG_PPC_ISERIES | |
1020 | mtspr SPRN_SRR0,r11 | |
1021 | mtspr SPRN_SRR1,r12 | |
1022 | #endif /* CONFIG_PPC_ISERIES */ | |
1023 | ld r9,PACA_EXSLB+EX_R9(r13) | |
1024 | ld r10,PACA_EXSLB+EX_R10(r13) | |
1025 | ld r11,PACA_EXSLB+EX_R11(r13) | |
1026 | ld r12,PACA_EXSLB+EX_R12(r13) | |
1027 | ld r13,PACA_EXSLB+EX_R13(r13) | |
1028 | rfid | |
1029 | b . /* prevent speculative execution */ | |
1030 | ||
1031 | unrecov_slb: | |
1032 | EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) | |
1033 | DISABLE_INTS | |
1034 | bl .save_nvgprs | |
1035 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
1036 | bl .unrecoverable_exception | |
1037 | b 1b | |
1038 | ||
14cf11af PM |
1039 | .align 7 |
1040 | .globl hardware_interrupt_common | |
1041 | .globl hardware_interrupt_entry | |
1042 | hardware_interrupt_common: | |
1043 | EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN) | |
1044 | hardware_interrupt_entry: | |
1045 | DISABLE_INTS | |
1046 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1047 | bl .do_IRQ | |
1048 | b .ret_from_except_lite | |
1049 | ||
1050 | .align 7 | |
1051 | .globl alignment_common | |
1052 | alignment_common: | |
b5bbeb23 | 1053 | mfspr r10,SPRN_DAR |
14cf11af | 1054 | std r10,PACA_EXGEN+EX_DAR(r13) |
b5bbeb23 | 1055 | mfspr r10,SPRN_DSISR |
14cf11af PM |
1056 | stw r10,PACA_EXGEN+EX_DSISR(r13) |
1057 | EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) | |
1058 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
1059 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
1060 | std r3,_DAR(r1) | |
1061 | std r4,_DSISR(r1) | |
1062 | bl .save_nvgprs | |
1063 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1064 | ENABLE_INTS | |
1065 | bl .alignment_exception | |
1066 | b .ret_from_except | |
1067 | ||
1068 | .align 7 | |
1069 | .globl program_check_common | |
1070 | program_check_common: | |
1071 | EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) | |
1072 | bl .save_nvgprs | |
1073 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1074 | ENABLE_INTS | |
1075 | bl .program_check_exception | |
1076 | b .ret_from_except | |
1077 | ||
1078 | .align 7 | |
1079 | .globl fp_unavailable_common | |
1080 | fp_unavailable_common: | |
1081 | EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) | |
1082 | bne .load_up_fpu /* if from user, just load it up */ | |
1083 | bl .save_nvgprs | |
1084 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1085 | ENABLE_INTS | |
1086 | bl .kernel_fp_unavailable_exception | |
1087 | BUG_OPCODE | |
1088 | ||
14cf11af PM |
1089 | .align 7 |
1090 | .globl altivec_unavailable_common | |
1091 | altivec_unavailable_common: | |
1092 | EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) | |
1093 | #ifdef CONFIG_ALTIVEC | |
1094 | BEGIN_FTR_SECTION | |
1095 | bne .load_up_altivec /* if from user, just load it up */ | |
1096 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1097 | #endif | |
1098 | bl .save_nvgprs | |
1099 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1100 | ENABLE_INTS | |
1101 | bl .altivec_unavailable_exception | |
1102 | b .ret_from_except | |
1103 | ||
1104 | #ifdef CONFIG_ALTIVEC | |
1105 | /* | |
1106 | * load_up_altivec(unused, unused, tsk) | |
1107 | * Disable VMX for the task which had it previously, | |
1108 | * and save its vector registers in its thread_struct. | |
1109 | * Enables the VMX for use in the kernel on return. | |
1110 | * On SMP we know the VMX is free, since we give it up every | |
1111 | * switch (ie, no lazy save of the vector registers). | |
1112 | * On entry: r13 == 'current' && last_task_used_altivec != 'current' | |
1113 | */ | |
1114 | _STATIC(load_up_altivec) | |
1115 | mfmsr r5 /* grab the current MSR */ | |
1116 | oris r5,r5,MSR_VEC@h | |
1117 | mtmsrd r5 /* enable use of VMX now */ | |
1118 | isync | |
1119 | ||
1120 | /* | |
1121 | * For SMP, we don't do lazy VMX switching because it just gets too | |
1122 | * horrendously complex, especially when a task switches from one CPU | |
1123 | * to another. Instead we call giveup_altvec in switch_to. | |
1124 | * VRSAVE isn't dealt with here, that is done in the normal context | |
1125 | * switch code. Note that we could rely on vrsave value to eventually | |
1126 | * avoid saving all of the VREGs here... | |
1127 | */ | |
1128 | #ifndef CONFIG_SMP | |
1129 | ld r3,last_task_used_altivec@got(r2) | |
1130 | ld r4,0(r3) | |
1131 | cmpdi 0,r4,0 | |
1132 | beq 1f | |
1133 | /* Save VMX state to last_task_used_altivec's THREAD struct */ | |
1134 | addi r4,r4,THREAD | |
1135 | SAVE_32VRS(0,r5,r4) | |
1136 | mfvscr vr0 | |
1137 | li r10,THREAD_VSCR | |
1138 | stvx vr0,r10,r4 | |
1139 | /* Disable VMX for last_task_used_altivec */ | |
1140 | ld r5,PT_REGS(r4) | |
1141 | ld r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
1142 | lis r6,MSR_VEC@h | |
1143 | andc r4,r4,r6 | |
1144 | std r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
1145 | 1: | |
1146 | #endif /* CONFIG_SMP */ | |
1147 | /* Hack: if we get an altivec unavailable trap with VRSAVE | |
1148 | * set to all zeros, we assume this is a broken application | |
1149 | * that fails to set it properly, and thus we switch it to | |
1150 | * all 1's | |
1151 | */ | |
1152 | mfspr r4,SPRN_VRSAVE | |
1153 | cmpdi 0,r4,0 | |
1154 | bne+ 1f | |
1155 | li r4,-1 | |
1156 | mtspr SPRN_VRSAVE,r4 | |
1157 | 1: | |
1158 | /* enable use of VMX after return */ | |
1159 | ld r4,PACACURRENT(r13) | |
1160 | addi r5,r4,THREAD /* Get THREAD */ | |
1161 | oris r12,r12,MSR_VEC@h | |
1162 | std r12,_MSR(r1) | |
1163 | li r4,1 | |
1164 | li r10,THREAD_VSCR | |
1165 | stw r4,THREAD_USED_VR(r5) | |
1166 | lvx vr0,r10,r5 | |
1167 | mtvscr vr0 | |
1168 | REST_32VRS(0,r4,r5) | |
1169 | #ifndef CONFIG_SMP | |
1170 | /* Update last_task_used_math to 'current' */ | |
1171 | subi r4,r5,THREAD /* Back to 'current' */ | |
1172 | std r4,0(r3) | |
1173 | #endif /* CONFIG_SMP */ | |
1174 | /* restore registers and return */ | |
1175 | b fast_exception_return | |
1176 | #endif /* CONFIG_ALTIVEC */ | |
1177 | ||
1178 | /* | |
1179 | * Hash table stuff | |
1180 | */ | |
1181 | .align 7 | |
1182 | _GLOBAL(do_hash_page) | |
1183 | std r3,_DAR(r1) | |
1184 | std r4,_DSISR(r1) | |
1185 | ||
1186 | andis. r0,r4,0xa450 /* weird error? */ | |
1187 | bne- .handle_page_fault /* if not, try to insert a HPTE */ | |
1188 | BEGIN_FTR_SECTION | |
1189 | andis. r0,r4,0x0020 /* Is it a segment table fault? */ | |
1190 | bne- .do_ste_alloc /* If so handle it */ | |
1191 | END_FTR_SECTION_IFCLR(CPU_FTR_SLB) | |
1192 | ||
1193 | /* | |
1194 | * We need to set the _PAGE_USER bit if MSR_PR is set or if we are | |
1195 | * accessing a userspace segment (even from the kernel). We assume | |
1196 | * kernel addresses always have the high bit set. | |
1197 | */ | |
1198 | rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */ | |
1199 | rotldi r0,r3,15 /* Move high bit into MSR_PR posn */ | |
1200 | orc r0,r12,r0 /* MSR_PR | ~high_bit */ | |
1201 | rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */ | |
1202 | ori r4,r4,1 /* add _PAGE_PRESENT */ | |
1203 | rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */ | |
1204 | ||
1205 | /* | |
1206 | * On iSeries, we soft-disable interrupts here, then | |
1207 | * hard-enable interrupts so that the hash_page code can spin on | |
1208 | * the hash_table_lock without problems on a shared processor. | |
1209 | */ | |
1210 | DISABLE_INTS | |
1211 | ||
1212 | /* | |
1213 | * r3 contains the faulting address | |
1214 | * r4 contains the required access permissions | |
1215 | * r5 contains the trap number | |
1216 | * | |
1217 | * at return r3 = 0 for success | |
1218 | */ | |
1219 | bl .hash_page /* build HPTE if possible */ | |
1220 | cmpdi r3,0 /* see if hash_page succeeded */ | |
1221 | ||
1222 | #ifdef DO_SOFT_DISABLE | |
1223 | /* | |
1224 | * If we had interrupts soft-enabled at the point where the | |
1225 | * DSI/ISI occurred, and an interrupt came in during hash_page, | |
1226 | * handle it now. | |
1227 | * We jump to ret_from_except_lite rather than fast_exception_return | |
1228 | * because ret_from_except_lite will check for and handle pending | |
1229 | * interrupts if necessary. | |
1230 | */ | |
1231 | beq .ret_from_except_lite | |
1232 | /* For a hash failure, we don't bother re-enabling interrupts */ | |
1233 | ble- 12f | |
1234 | ||
1235 | /* | |
1236 | * hash_page couldn't handle it, set soft interrupt enable back | |
1237 | * to what it was before the trap. Note that .local_irq_restore | |
1238 | * handles any interrupts pending at this point. | |
1239 | */ | |
1240 | ld r3,SOFTE(r1) | |
1241 | bl .local_irq_restore | |
1242 | b 11f | |
1243 | #else | |
1244 | beq fast_exception_return /* Return from exception on success */ | |
1245 | ble- 12f /* Failure return from hash_page */ | |
1246 | ||
1247 | /* fall through */ | |
1248 | #endif | |
1249 | ||
1250 | /* Here we have a page fault that hash_page can't handle. */ | |
1251 | _GLOBAL(handle_page_fault) | |
1252 | ENABLE_INTS | |
1253 | 11: ld r4,_DAR(r1) | |
1254 | ld r5,_DSISR(r1) | |
1255 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1256 | bl .do_page_fault | |
1257 | cmpdi r3,0 | |
1258 | beq+ .ret_from_except_lite | |
1259 | bl .save_nvgprs | |
1260 | mr r5,r3 | |
1261 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1262 | lwz r4,_DAR(r1) | |
1263 | bl .bad_page_fault | |
1264 | b .ret_from_except | |
1265 | ||
1266 | /* We have a page fault that hash_page could handle but HV refused | |
1267 | * the PTE insertion | |
1268 | */ | |
1269 | 12: bl .save_nvgprs | |
1270 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1271 | lwz r4,_DAR(r1) | |
1272 | bl .low_hash_fault | |
1273 | b .ret_from_except | |
1274 | ||
1275 | /* here we have a segment miss */ | |
1276 | _GLOBAL(do_ste_alloc) | |
1277 | bl .ste_allocate /* try to insert stab entry */ | |
1278 | cmpdi r3,0 | |
1279 | beq+ fast_exception_return | |
1280 | b .handle_page_fault | |
1281 | ||
1282 | /* | |
1283 | * r13 points to the PACA, r9 contains the saved CR, | |
1284 | * r11 and r12 contain the saved SRR0 and SRR1. | |
1285 | * r9 - r13 are saved in paca->exslb. | |
1286 | * We assume we aren't going to take any exceptions during this procedure. | |
1287 | * We assume (DAR >> 60) == 0xc. | |
1288 | */ | |
1289 | .align 7 | |
1290 | _GLOBAL(do_stab_bolted) | |
1291 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | |
1292 | std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */ | |
1293 | ||
1294 | /* Hash to the primary group */ | |
1295 | ld r10,PACASTABVIRT(r13) | |
b5bbeb23 | 1296 | mfspr r11,SPRN_DAR |
14cf11af PM |
1297 | srdi r11,r11,28 |
1298 | rldimi r10,r11,7,52 /* r10 = first ste of the group */ | |
1299 | ||
1300 | /* Calculate VSID */ | |
1301 | /* This is a kernel address, so protovsid = ESID */ | |
1302 | ASM_VSID_SCRAMBLE(r11, r9) | |
1303 | rldic r9,r11,12,16 /* r9 = vsid << 12 */ | |
1304 | ||
1305 | /* Search the primary group for a free entry */ | |
1306 | 1: ld r11,0(r10) /* Test valid bit of the current ste */ | |
1307 | andi. r11,r11,0x80 | |
1308 | beq 2f | |
1309 | addi r10,r10,16 | |
1310 | andi. r11,r10,0x70 | |
1311 | bne 1b | |
1312 | ||
1313 | /* Stick for only searching the primary group for now. */ | |
1314 | /* At least for now, we use a very simple random castout scheme */ | |
1315 | /* Use the TB as a random number ; OR in 1 to avoid entry 0 */ | |
1316 | mftb r11 | |
1317 | rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */ | |
1318 | ori r11,r11,0x10 | |
1319 | ||
1320 | /* r10 currently points to an ste one past the group of interest */ | |
1321 | /* make it point to the randomly selected entry */ | |
1322 | subi r10,r10,128 | |
1323 | or r10,r10,r11 /* r10 is the entry to invalidate */ | |
1324 | ||
1325 | isync /* mark the entry invalid */ | |
1326 | ld r11,0(r10) | |
1327 | rldicl r11,r11,56,1 /* clear the valid bit */ | |
1328 | rotldi r11,r11,8 | |
1329 | std r11,0(r10) | |
1330 | sync | |
1331 | ||
1332 | clrrdi r11,r11,28 /* Get the esid part of the ste */ | |
1333 | slbie r11 | |
1334 | ||
1335 | 2: std r9,8(r10) /* Store the vsid part of the ste */ | |
1336 | eieio | |
1337 | ||
b5bbeb23 | 1338 | mfspr r11,SPRN_DAR /* Get the new esid */ |
14cf11af PM |
1339 | clrrdi r11,r11,28 /* Permits a full 32b of ESID */ |
1340 | ori r11,r11,0x90 /* Turn on valid and kp */ | |
1341 | std r11,0(r10) /* Put new entry back into the stab */ | |
1342 | ||
1343 | sync | |
1344 | ||
1345 | /* All done -- return from exception. */ | |
1346 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | |
1347 | ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */ | |
1348 | ||
1349 | andi. r10,r12,MSR_RI | |
1350 | beq- unrecov_slb | |
1351 | ||
1352 | mtcrf 0x80,r9 /* restore CR */ | |
1353 | ||
1354 | mfmsr r10 | |
1355 | clrrdi r10,r10,2 | |
1356 | mtmsrd r10,1 | |
1357 | ||
b5bbeb23 PM |
1358 | mtspr SPRN_SRR0,r11 |
1359 | mtspr SPRN_SRR1,r12 | |
14cf11af PM |
1360 | ld r9,PACA_EXSLB+EX_R9(r13) |
1361 | ld r10,PACA_EXSLB+EX_R10(r13) | |
1362 | ld r11,PACA_EXSLB+EX_R11(r13) | |
1363 | ld r12,PACA_EXSLB+EX_R12(r13) | |
1364 | ld r13,PACA_EXSLB+EX_R13(r13) | |
1365 | rfid | |
1366 | b . /* prevent speculative execution */ | |
1367 | ||
14cf11af PM |
1368 | /* |
1369 | * Space for CPU0's segment table. | |
1370 | * | |
1371 | * On iSeries, the hypervisor must fill in at least one entry before | |
1372 | * we get control (with relocate on). The address is give to the hv | |
ee400b63 | 1373 | * as a page number (see xLparMap in lpardata.c), so this must be at a |
14cf11af PM |
1374 | * fixed address (the linker can't compute (u64)&initial_stab >> |
1375 | * PAGE_SHIFT). | |
1376 | */ | |
758438a7 | 1377 | . = STAB0_OFFSET /* 0x6000 */ |
14cf11af PM |
1378 | .globl initial_stab |
1379 | initial_stab: | |
1380 | .space 4096 | |
1381 | ||
1382 | /* | |
1383 | * Data area reserved for FWNMI option. | |
1384 | * This address (0x7000) is fixed by the RPA. | |
1385 | */ | |
1386 | .= 0x7000 | |
1387 | .globl fwnmi_data_area | |
1388 | fwnmi_data_area: | |
1389 | ||
1390 | /* iSeries does not use the FWNMI stuff, so it is safe to put | |
1391 | * this here, even if we later allow kernels that will boot on | |
1392 | * both pSeries and iSeries */ | |
1393 | #ifdef CONFIG_PPC_ISERIES | |
1394 | . = LPARMAP_PHYS | |
1395 | #include "lparmap.s" | |
1396 | /* | |
1397 | * This ".text" is here for old compilers that generate a trailing | |
1398 | * .note section when compiling .c files to .s | |
1399 | */ | |
1400 | .text | |
1401 | #endif /* CONFIG_PPC_ISERIES */ | |
1402 | ||
1403 | . = 0x8000 | |
1404 | ||
1405 | /* | |
1406 | * On pSeries, secondary processors spin in the following code. | |
1407 | * At entry, r3 = this processor's number (physical cpu id) | |
1408 | */ | |
1409 | _GLOBAL(pSeries_secondary_smp_init) | |
1410 | mr r24,r3 | |
1411 | ||
1412 | /* turn on 64-bit mode */ | |
1413 | bl .enable_64b_mode | |
1414 | isync | |
1415 | ||
1416 | /* Copy some CPU settings from CPU 0 */ | |
1417 | bl .__restore_cpu_setup | |
1418 | ||
1419 | /* Set up a paca value for this processor. Since we have the | |
1420 | * physical cpu id in r24, we need to search the pacas to find | |
1421 | * which logical id maps to our physical one. | |
1422 | */ | |
e58c3495 | 1423 | LOAD_REG_IMMEDIATE(r13, paca) /* Get base vaddr of paca array */ |
14cf11af PM |
1424 | li r5,0 /* logical cpu id */ |
1425 | 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ | |
1426 | cmpw r6,r24 /* Compare to our id */ | |
1427 | beq 2f | |
1428 | addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */ | |
1429 | addi r5,r5,1 | |
1430 | cmpwi r5,NR_CPUS | |
1431 | blt 1b | |
1432 | ||
1433 | mr r3,r24 /* not found, copy phys to r3 */ | |
1434 | b .kexec_wait /* next kernel might do better */ | |
1435 | ||
b5bbeb23 | 1436 | 2: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */ |
14cf11af PM |
1437 | /* From now on, r24 is expected to be logical cpuid */ |
1438 | mr r24,r5 | |
1439 | 3: HMT_LOW | |
1440 | lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ | |
1441 | /* start. */ | |
1442 | sync | |
1443 | ||
1444 | /* Create a temp kernel stack for use before relocation is on. */ | |
1445 | ld r1,PACAEMERGSP(r13) | |
1446 | subi r1,r1,STACK_FRAME_OVERHEAD | |
1447 | ||
1448 | cmpwi 0,r23,0 | |
1449 | #ifdef CONFIG_SMP | |
1450 | bne .__secondary_start | |
1451 | #endif | |
1452 | b 3b /* Loop until told to go */ | |
1453 | ||
1454 | #ifdef CONFIG_PPC_ISERIES | |
1455 | _STATIC(__start_initialization_iSeries) | |
1456 | /* Clear out the BSS */ | |
e58c3495 DG |
1457 | LOAD_REG_IMMEDIATE(r11,__bss_stop) |
1458 | LOAD_REG_IMMEDIATE(r8,__bss_start) | |
14cf11af PM |
1459 | sub r11,r11,r8 /* bss size */ |
1460 | addi r11,r11,7 /* round up to an even double word */ | |
1461 | rldicl. r11,r11,61,3 /* shift right by 3 */ | |
1462 | beq 4f | |
1463 | addi r8,r8,-8 | |
1464 | li r0,0 | |
1465 | mtctr r11 /* zero this many doublewords */ | |
1466 | 3: stdu r0,8(r8) | |
1467 | bdnz 3b | |
1468 | 4: | |
e58c3495 | 1469 | LOAD_REG_IMMEDIATE(r1,init_thread_union) |
14cf11af PM |
1470 | addi r1,r1,THREAD_SIZE |
1471 | li r0,0 | |
1472 | stdu r0,-STACK_FRAME_OVERHEAD(r1) | |
1473 | ||
e58c3495 DG |
1474 | LOAD_REG_IMMEDIATE(r3,cpu_specs) |
1475 | LOAD_REG_IMMEDIATE(r4,cur_cpu_spec) | |
14cf11af PM |
1476 | li r5,0 |
1477 | bl .identify_cpu | |
1478 | ||
e58c3495 | 1479 | LOAD_REG_IMMEDIATE(r2,__toc_start) |
14cf11af PM |
1480 | addi r2,r2,0x4000 |
1481 | addi r2,r2,0x4000 | |
1482 | ||
1483 | bl .iSeries_early_setup | |
ee400b63 | 1484 | bl .early_setup |
14cf11af PM |
1485 | |
1486 | /* relocation is on at this point */ | |
1487 | ||
1488 | b .start_here_common | |
1489 | #endif /* CONFIG_PPC_ISERIES */ | |
1490 | ||
1491 | #ifdef CONFIG_PPC_MULTIPLATFORM | |
1492 | ||
1493 | _STATIC(__mmu_off) | |
1494 | mfmsr r3 | |
1495 | andi. r0,r3,MSR_IR|MSR_DR | |
1496 | beqlr | |
1497 | andc r3,r3,r0 | |
1498 | mtspr SPRN_SRR0,r4 | |
1499 | mtspr SPRN_SRR1,r3 | |
1500 | sync | |
1501 | rfid | |
1502 | b . /* prevent speculative execution */ | |
1503 | ||
1504 | ||
1505 | /* | |
1506 | * Here is our main kernel entry point. We support currently 2 kind of entries | |
1507 | * depending on the value of r5. | |
1508 | * | |
1509 | * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content | |
1510 | * in r3...r7 | |
1511 | * | |
1512 | * r5 == NULL -> kexec style entry. r3 is a physical pointer to the | |
1513 | * DT block, r4 is a physical pointer to the kernel itself | |
1514 | * | |
1515 | */ | |
1516 | _GLOBAL(__start_initialization_multiplatform) | |
be42d5fa | 1517 | #ifdef CONFIG_PPC_MULTIPLATFORM |
14cf11af PM |
1518 | /* |
1519 | * Are we booted from a PROM Of-type client-interface ? | |
1520 | */ | |
1521 | cmpldi cr0,r5,0 | |
1522 | bne .__boot_from_prom /* yes -> prom */ | |
be42d5fa | 1523 | #endif |
14cf11af PM |
1524 | |
1525 | /* Save parameters */ | |
1526 | mr r31,r3 | |
1527 | mr r30,r4 | |
1528 | ||
1529 | /* Make sure we are running in 64 bits mode */ | |
1530 | bl .enable_64b_mode | |
1531 | ||
1532 | /* Setup some critical 970 SPRs before switching MMU off */ | |
1533 | bl .__970_cpu_preinit | |
1534 | ||
1535 | /* cpu # */ | |
1536 | li r24,0 | |
1537 | ||
1538 | /* Switch off MMU if not already */ | |
e58c3495 | 1539 | LOAD_REG_IMMEDIATE(r4, .__after_prom_start - KERNELBASE) |
14cf11af PM |
1540 | add r4,r4,r30 |
1541 | bl .__mmu_off | |
1542 | b .__after_prom_start | |
1543 | ||
be42d5fa | 1544 | #ifdef CONFIG_PPC_MULTIPLATFORM |
14cf11af PM |
1545 | _STATIC(__boot_from_prom) |
1546 | /* Save parameters */ | |
1547 | mr r31,r3 | |
1548 | mr r30,r4 | |
1549 | mr r29,r5 | |
1550 | mr r28,r6 | |
1551 | mr r27,r7 | |
1552 | ||
1553 | /* Make sure we are running in 64 bits mode */ | |
1554 | bl .enable_64b_mode | |
1555 | ||
1556 | /* put a relocation offset into r3 */ | |
1557 | bl .reloc_offset | |
1558 | ||
e58c3495 | 1559 | LOAD_REG_IMMEDIATE(r2,__toc_start) |
14cf11af PM |
1560 | addi r2,r2,0x4000 |
1561 | addi r2,r2,0x4000 | |
1562 | ||
1563 | /* Relocate the TOC from a virt addr to a real addr */ | |
5a408329 | 1564 | add r2,r2,r3 |
14cf11af PM |
1565 | |
1566 | /* Restore parameters */ | |
1567 | mr r3,r31 | |
1568 | mr r4,r30 | |
1569 | mr r5,r29 | |
1570 | mr r6,r28 | |
1571 | mr r7,r27 | |
1572 | ||
1573 | /* Do all of the interaction with OF client interface */ | |
1574 | bl .prom_init | |
1575 | /* We never return */ | |
1576 | trap | |
be42d5fa | 1577 | #endif |
14cf11af PM |
1578 | |
1579 | /* | |
1580 | * At this point, r3 contains the physical address we are running at, | |
1581 | * returned by prom_init() | |
1582 | */ | |
1583 | _STATIC(__after_prom_start) | |
1584 | ||
1585 | /* | |
758438a7 | 1586 | * We need to run with __start at physical address PHYSICAL_START. |
14cf11af PM |
1587 | * This will leave some code in the first 256B of |
1588 | * real memory, which are reserved for software use. | |
1589 | * The remainder of the first page is loaded with the fixed | |
1590 | * interrupt vectors. The next two pages are filled with | |
1591 | * unknown exception placeholders. | |
1592 | * | |
1593 | * Note: This process overwrites the OF exception vectors. | |
1594 | * r26 == relocation offset | |
1595 | * r27 == KERNELBASE | |
1596 | */ | |
1597 | bl .reloc_offset | |
1598 | mr r26,r3 | |
e58c3495 | 1599 | LOAD_REG_IMMEDIATE(r27, KERNELBASE) |
14cf11af | 1600 | |
e58c3495 | 1601 | LOAD_REG_IMMEDIATE(r3, PHYSICAL_START) /* target addr */ |
14cf11af PM |
1602 | |
1603 | // XXX FIXME: Use phys returned by OF (r30) | |
5a408329 | 1604 | add r4,r27,r26 /* source addr */ |
14cf11af PM |
1605 | /* current address of _start */ |
1606 | /* i.e. where we are running */ | |
1607 | /* the source addr */ | |
1608 | ||
e58c3495 | 1609 | LOAD_REG_IMMEDIATE(r5,copy_to_here) /* # bytes of memory to copy */ |
14cf11af PM |
1610 | sub r5,r5,r27 |
1611 | ||
1612 | li r6,0x100 /* Start offset, the first 0x100 */ | |
1613 | /* bytes were copied earlier. */ | |
1614 | ||
1615 | bl .copy_and_flush /* copy the first n bytes */ | |
1616 | /* this includes the code being */ | |
1617 | /* executed here. */ | |
1618 | ||
e58c3495 | 1619 | LOAD_REG_IMMEDIATE(r0, 4f) /* Jump to the copy of this code */ |
14cf11af PM |
1620 | mtctr r0 /* that we just made/relocated */ |
1621 | bctr | |
1622 | ||
e58c3495 | 1623 | 4: LOAD_REG_IMMEDIATE(r5,klimit) |
5a408329 | 1624 | add r5,r5,r26 |
14cf11af PM |
1625 | ld r5,0(r5) /* get the value of klimit */ |
1626 | sub r5,r5,r27 | |
1627 | bl .copy_and_flush /* copy the rest */ | |
1628 | b .start_here_multiplatform | |
1629 | ||
1630 | #endif /* CONFIG_PPC_MULTIPLATFORM */ | |
1631 | ||
1632 | /* | |
1633 | * Copy routine used to copy the kernel to start at physical address 0 | |
1634 | * and flush and invalidate the caches as needed. | |
1635 | * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset | |
1636 | * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. | |
1637 | * | |
1638 | * Note: this routine *only* clobbers r0, r6 and lr | |
1639 | */ | |
1640 | _GLOBAL(copy_and_flush) | |
1641 | addi r5,r5,-8 | |
1642 | addi r6,r6,-8 | |
1643 | 4: li r0,16 /* Use the least common */ | |
1644 | /* denominator cache line */ | |
1645 | /* size. This results in */ | |
1646 | /* extra cache line flushes */ | |
1647 | /* but operation is correct. */ | |
1648 | /* Can't get cache line size */ | |
1649 | /* from NACA as it is being */ | |
1650 | /* moved too. */ | |
1651 | ||
1652 | mtctr r0 /* put # words/line in ctr */ | |
1653 | 3: addi r6,r6,8 /* copy a cache line */ | |
1654 | ldx r0,r6,r4 | |
1655 | stdx r0,r6,r3 | |
1656 | bdnz 3b | |
1657 | dcbst r6,r3 /* write it to memory */ | |
1658 | sync | |
1659 | icbi r6,r3 /* flush the icache line */ | |
1660 | cmpld 0,r6,r5 | |
1661 | blt 4b | |
1662 | sync | |
1663 | addi r5,r5,8 | |
1664 | addi r6,r6,8 | |
1665 | blr | |
1666 | ||
1667 | .align 8 | |
1668 | copy_to_here: | |
1669 | ||
1670 | #ifdef CONFIG_SMP | |
1671 | #ifdef CONFIG_PPC_PMAC | |
1672 | /* | |
1673 | * On PowerMac, secondary processors starts from the reset vector, which | |
1674 | * is temporarily turned into a call to one of the functions below. | |
1675 | */ | |
1676 | .section ".text"; | |
1677 | .align 2 ; | |
1678 | ||
35499c01 PM |
1679 | .globl __secondary_start_pmac_0 |
1680 | __secondary_start_pmac_0: | |
1681 | /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ | |
1682 | li r24,0 | |
1683 | b 1f | |
1684 | li r24,1 | |
1685 | b 1f | |
1686 | li r24,2 | |
1687 | b 1f | |
1688 | li r24,3 | |
1689 | 1: | |
14cf11af PM |
1690 | |
1691 | _GLOBAL(pmac_secondary_start) | |
1692 | /* turn on 64-bit mode */ | |
1693 | bl .enable_64b_mode | |
1694 | isync | |
1695 | ||
1696 | /* Copy some CPU settings from CPU 0 */ | |
1697 | bl .__restore_cpu_setup | |
1698 | ||
1699 | /* pSeries do that early though I don't think we really need it */ | |
1700 | mfmsr r3 | |
1701 | ori r3,r3,MSR_RI | |
1702 | mtmsrd r3 /* RI on */ | |
1703 | ||
1704 | /* Set up a paca value for this processor. */ | |
e58c3495 | 1705 | LOAD_REG_IMMEDIATE(r4, paca) /* Get base vaddr of paca array */ |
14cf11af PM |
1706 | mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ |
1707 | add r13,r13,r4 /* for this processor. */ | |
b5bbeb23 | 1708 | mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */ |
14cf11af PM |
1709 | |
1710 | /* Create a temp kernel stack for use before relocation is on. */ | |
1711 | ld r1,PACAEMERGSP(r13) | |
1712 | subi r1,r1,STACK_FRAME_OVERHEAD | |
1713 | ||
1714 | b .__secondary_start | |
1715 | ||
1716 | #endif /* CONFIG_PPC_PMAC */ | |
1717 | ||
1718 | /* | |
1719 | * This function is called after the master CPU has released the | |
1720 | * secondary processors. The execution environment is relocation off. | |
1721 | * The paca for this processor has the following fields initialized at | |
1722 | * this point: | |
1723 | * 1. Processor number | |
1724 | * 2. Segment table pointer (virtual address) | |
1725 | * On entry the following are set: | |
1726 | * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries | |
1727 | * r24 = cpu# (in Linux terms) | |
1728 | * r13 = paca virtual address | |
1729 | * SPRG3 = paca virtual address | |
1730 | */ | |
1731 | _GLOBAL(__secondary_start) | |
799d6046 PM |
1732 | /* Set thread priority to MEDIUM */ |
1733 | HMT_MEDIUM | |
14cf11af | 1734 | |
799d6046 | 1735 | /* Load TOC */ |
14cf11af | 1736 | ld r2,PACATOC(r13) |
799d6046 PM |
1737 | |
1738 | /* Do early setup for that CPU (stab, slb, hash table pointer) */ | |
1739 | bl .early_setup_secondary | |
14cf11af PM |
1740 | |
1741 | /* Initialize the kernel stack. Just a repeat for iSeries. */ | |
e58c3495 | 1742 | LOAD_REG_ADDR(r3, current_set) |
14cf11af PM |
1743 | sldi r28,r24,3 /* get current_set[cpu#] */ |
1744 | ldx r1,r3,r28 | |
1745 | addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD | |
1746 | std r1,PACAKSAVE(r13) | |
1747 | ||
799d6046 | 1748 | /* Clear backchain so we get nice backtraces */ |
14cf11af PM |
1749 | li r7,0 |
1750 | mtlr r7 | |
1751 | ||
1752 | /* enable MMU and jump to start_secondary */ | |
e58c3495 DG |
1753 | LOAD_REG_ADDR(r3, .start_secondary_prolog) |
1754 | LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) | |
14cf11af PM |
1755 | #ifdef DO_SOFT_DISABLE |
1756 | ori r4,r4,MSR_EE | |
1757 | #endif | |
b5bbeb23 PM |
1758 | mtspr SPRN_SRR0,r3 |
1759 | mtspr SPRN_SRR1,r4 | |
14cf11af PM |
1760 | rfid |
1761 | b . /* prevent speculative execution */ | |
1762 | ||
1763 | /* | |
1764 | * Running with relocation on at this point. All we want to do is | |
1765 | * zero the stack back-chain pointer before going into C code. | |
1766 | */ | |
1767 | _GLOBAL(start_secondary_prolog) | |
1768 | li r3,0 | |
1769 | std r3,0(r1) /* Zero the stack frame pointer */ | |
1770 | bl .start_secondary | |
799d6046 | 1771 | b . |
14cf11af PM |
1772 | #endif |
1773 | ||
1774 | /* | |
1775 | * This subroutine clobbers r11 and r12 | |
1776 | */ | |
1777 | _GLOBAL(enable_64b_mode) | |
1778 | mfmsr r11 /* grab the current MSR */ | |
1779 | li r12,1 | |
1780 | rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG) | |
1781 | or r11,r11,r12 | |
1782 | li r12,1 | |
1783 | rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG) | |
1784 | or r11,r11,r12 | |
1785 | mtmsrd r11 | |
1786 | isync | |
1787 | blr | |
1788 | ||
1789 | #ifdef CONFIG_PPC_MULTIPLATFORM | |
1790 | /* | |
1791 | * This is where the main kernel code starts. | |
1792 | */ | |
1793 | _STATIC(start_here_multiplatform) | |
1794 | /* get a new offset, now that the kernel has moved. */ | |
1795 | bl .reloc_offset | |
1796 | mr r26,r3 | |
1797 | ||
1798 | /* Clear out the BSS. It may have been done in prom_init, | |
1799 | * already but that's irrelevant since prom_init will soon | |
1800 | * be detached from the kernel completely. Besides, we need | |
1801 | * to clear it now for kexec-style entry. | |
1802 | */ | |
e58c3495 DG |
1803 | LOAD_REG_IMMEDIATE(r11,__bss_stop) |
1804 | LOAD_REG_IMMEDIATE(r8,__bss_start) | |
14cf11af PM |
1805 | sub r11,r11,r8 /* bss size */ |
1806 | addi r11,r11,7 /* round up to an even double word */ | |
1807 | rldicl. r11,r11,61,3 /* shift right by 3 */ | |
1808 | beq 4f | |
1809 | addi r8,r8,-8 | |
1810 | li r0,0 | |
1811 | mtctr r11 /* zero this many doublewords */ | |
1812 | 3: stdu r0,8(r8) | |
1813 | bdnz 3b | |
1814 | 4: | |
1815 | ||
1816 | mfmsr r6 | |
1817 | ori r6,r6,MSR_RI | |
1818 | mtmsrd r6 /* RI on */ | |
1819 | ||
1820 | #ifdef CONFIG_HMT | |
1821 | /* Start up the second thread on cpu 0 */ | |
b5bbeb23 | 1822 | mfspr r3,SPRN_PVR |
14cf11af PM |
1823 | srwi r3,r3,16 |
1824 | cmpwi r3,0x34 /* Pulsar */ | |
1825 | beq 90f | |
1826 | cmpwi r3,0x36 /* Icestar */ | |
1827 | beq 90f | |
1828 | cmpwi r3,0x37 /* SStar */ | |
1829 | beq 90f | |
1830 | b 91f /* HMT not supported */ | |
1831 | 90: li r3,0 | |
1832 | bl .hmt_start_secondary | |
1833 | 91: | |
1834 | #endif | |
1835 | ||
1836 | /* The following gets the stack and TOC set up with the regs */ | |
1837 | /* pointing to the real addr of the kernel stack. This is */ | |
1838 | /* all done to support the C function call below which sets */ | |
1839 | /* up the htab. This is done because we have relocated the */ | |
1840 | /* kernel but are still running in real mode. */ | |
1841 | ||
e58c3495 | 1842 | LOAD_REG_IMMEDIATE(r3,init_thread_union) |
5a408329 | 1843 | add r3,r3,r26 |
14cf11af PM |
1844 | |
1845 | /* set up a stack pointer (physical address) */ | |
1846 | addi r1,r3,THREAD_SIZE | |
1847 | li r0,0 | |
1848 | stdu r0,-STACK_FRAME_OVERHEAD(r1) | |
1849 | ||
1850 | /* set up the TOC (physical address) */ | |
e58c3495 | 1851 | LOAD_REG_IMMEDIATE(r2,__toc_start) |
14cf11af PM |
1852 | addi r2,r2,0x4000 |
1853 | addi r2,r2,0x4000 | |
5a408329 | 1854 | add r2,r2,r26 |
14cf11af | 1855 | |
e58c3495 | 1856 | LOAD_REG_IMMEDIATE(r3, cpu_specs) |
5a408329 | 1857 | add r3,r3,r26 |
e58c3495 | 1858 | LOAD_REG_IMMEDIATE(r4,cur_cpu_spec) |
5a408329 | 1859 | add r4,r4,r26 |
14cf11af PM |
1860 | mr r5,r26 |
1861 | bl .identify_cpu | |
1862 | ||
1863 | /* Save some low level config HIDs of CPU0 to be copied to | |
1864 | * other CPUs later on, or used for suspend/resume | |
1865 | */ | |
1866 | bl .__save_cpu_setup | |
1867 | sync | |
1868 | ||
1869 | /* Setup a valid physical PACA pointer in SPRG3 for early_setup | |
1870 | * note that boot_cpuid can always be 0 nowadays since there is | |
1871 | * nowhere it can be initialized differently before we reach this | |
1872 | * code | |
1873 | */ | |
e58c3495 | 1874 | LOAD_REG_IMMEDIATE(r27, boot_cpuid) |
5a408329 | 1875 | add r27,r27,r26 |
14cf11af PM |
1876 | lwz r27,0(r27) |
1877 | ||
e58c3495 | 1878 | LOAD_REG_IMMEDIATE(r24, paca) /* Get base vaddr of paca array */ |
14cf11af PM |
1879 | mulli r13,r27,PACA_SIZE /* Calculate vaddr of right paca */ |
1880 | add r13,r13,r24 /* for this processor. */ | |
5a408329 | 1881 | add r13,r13,r26 /* convert to physical addr */ |
448b2719 | 1882 | mtspr SPRN_SPRG3,r13 |
14cf11af PM |
1883 | |
1884 | /* Do very early kernel initializations, including initial hash table, | |
1885 | * stab and slb setup before we turn on relocation. */ | |
1886 | ||
1887 | /* Restore parameters passed from prom_init/kexec */ | |
1888 | mr r3,r31 | |
1889 | bl .early_setup | |
1890 | ||
e58c3495 DG |
1891 | LOAD_REG_IMMEDIATE(r3, .start_here_common) |
1892 | LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) | |
b5bbeb23 PM |
1893 | mtspr SPRN_SRR0,r3 |
1894 | mtspr SPRN_SRR1,r4 | |
14cf11af PM |
1895 | rfid |
1896 | b . /* prevent speculative execution */ | |
1897 | #endif /* CONFIG_PPC_MULTIPLATFORM */ | |
1898 | ||
1899 | /* This is where all platforms converge execution */ | |
1900 | _STATIC(start_here_common) | |
1901 | /* relocation is on at this point */ | |
1902 | ||
1903 | /* The following code sets up the SP and TOC now that we are */ | |
1904 | /* running with translation enabled. */ | |
1905 | ||
e58c3495 | 1906 | LOAD_REG_IMMEDIATE(r3,init_thread_union) |
14cf11af PM |
1907 | |
1908 | /* set up the stack */ | |
1909 | addi r1,r3,THREAD_SIZE | |
1910 | li r0,0 | |
1911 | stdu r0,-STACK_FRAME_OVERHEAD(r1) | |
1912 | ||
1913 | /* Apply the CPUs-specific fixups (nop out sections not relevant | |
1914 | * to this CPU | |
1915 | */ | |
1916 | li r3,0 | |
1917 | bl .do_cpu_ftr_fixups | |
1918 | ||
e58c3495 | 1919 | LOAD_REG_IMMEDIATE(r26, boot_cpuid) |
14cf11af PM |
1920 | lwz r26,0(r26) |
1921 | ||
e58c3495 | 1922 | LOAD_REG_IMMEDIATE(r24, paca) /* Get base vaddr of paca array */ |
14cf11af PM |
1923 | mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */ |
1924 | add r13,r13,r24 /* for this processor. */ | |
b5bbeb23 | 1925 | mtspr SPRN_SPRG3,r13 |
14cf11af PM |
1926 | |
1927 | /* ptr to current */ | |
e58c3495 | 1928 | LOAD_REG_IMMEDIATE(r4, init_task) |
14cf11af PM |
1929 | std r4,PACACURRENT(r13) |
1930 | ||
1931 | /* Load the TOC */ | |
1932 | ld r2,PACATOC(r13) | |
1933 | std r1,PACAKSAVE(r13) | |
1934 | ||
1935 | bl .setup_system | |
1936 | ||
1937 | /* Load up the kernel context */ | |
1938 | 5: | |
1939 | #ifdef DO_SOFT_DISABLE | |
1940 | li r5,0 | |
1941 | stb r5,PACAPROCENABLED(r13) /* Soft Disabled */ | |
1942 | mfmsr r5 | |
1943 | ori r5,r5,MSR_EE /* Hard Enabled */ | |
1944 | mtmsrd r5 | |
1945 | #endif | |
1946 | ||
1947 | bl .start_kernel | |
1948 | ||
1949 | _GLOBAL(hmt_init) | |
1950 | #ifdef CONFIG_HMT | |
e58c3495 | 1951 | LOAD_REG_IMMEDIATE(r5, hmt_thread_data) |
b5bbeb23 | 1952 | mfspr r7,SPRN_PVR |
14cf11af PM |
1953 | srwi r7,r7,16 |
1954 | cmpwi r7,0x34 /* Pulsar */ | |
1955 | beq 90f | |
1956 | cmpwi r7,0x36 /* Icestar */ | |
1957 | beq 91f | |
1958 | cmpwi r7,0x37 /* SStar */ | |
1959 | beq 91f | |
1960 | b 101f | |
b5bbeb23 | 1961 | 90: mfspr r6,SPRN_PIR |
14cf11af PM |
1962 | andi. r6,r6,0x1f |
1963 | b 92f | |
b5bbeb23 | 1964 | 91: mfspr r6,SPRN_PIR |
14cf11af PM |
1965 | andi. r6,r6,0x3ff |
1966 | 92: sldi r4,r24,3 | |
1967 | stwx r6,r5,r4 | |
1968 | bl .hmt_start_secondary | |
1969 | b 101f | |
1970 | ||
1971 | __hmt_secondary_hold: | |
e58c3495 | 1972 | LOAD_REG_IMMEDIATE(r5, hmt_thread_data) |
14cf11af PM |
1973 | clrldi r5,r5,4 |
1974 | li r7,0 | |
b5bbeb23 PM |
1975 | mfspr r6,SPRN_PIR |
1976 | mfspr r8,SPRN_PVR | |
14cf11af PM |
1977 | srwi r8,r8,16 |
1978 | cmpwi r8,0x34 | |
1979 | bne 93f | |
1980 | andi. r6,r6,0x1f | |
1981 | b 103f | |
1982 | 93: andi. r6,r6,0x3f | |
1983 | ||
1984 | 103: lwzx r8,r5,r7 | |
1985 | cmpw r8,r6 | |
1986 | beq 104f | |
1987 | addi r7,r7,8 | |
1988 | b 103b | |
1989 | ||
1990 | 104: addi r7,r7,4 | |
1991 | lwzx r9,r5,r7 | |
1992 | mr r24,r9 | |
1993 | 101: | |
1994 | #endif | |
1995 | mr r3,r24 | |
1996 | b .pSeries_secondary_smp_init | |
1997 | ||
1998 | #ifdef CONFIG_HMT | |
1999 | _GLOBAL(hmt_start_secondary) | |
e58c3495 | 2000 | LOAD_REG_IMMEDIATE(r4,__hmt_secondary_hold) |
14cf11af | 2001 | clrldi r4,r4,4 |
b5bbeb23 PM |
2002 | mtspr SPRN_NIADORM, r4 |
2003 | mfspr r4, SPRN_MSRDORM | |
14cf11af PM |
2004 | li r5, -65 |
2005 | and r4, r4, r5 | |
b5bbeb23 | 2006 | mtspr SPRN_MSRDORM, r4 |
14cf11af PM |
2007 | lis r4,0xffef |
2008 | ori r4,r4,0x7403 | |
b5bbeb23 | 2009 | mtspr SPRN_TSC, r4 |
14cf11af | 2010 | li r4,0x1f4 |
b5bbeb23 PM |
2011 | mtspr SPRN_TST, r4 |
2012 | mfspr r4, SPRN_HID0 | |
14cf11af | 2013 | ori r4, r4, 0x1 |
b5bbeb23 | 2014 | mtspr SPRN_HID0, r4 |
14cf11af PM |
2015 | mfspr r4, SPRN_CTRLF |
2016 | oris r4, r4, 0x40 | |
2017 | mtspr SPRN_CTRLT, r4 | |
2018 | blr | |
2019 | #endif | |
2020 | ||
14cf11af PM |
2021 | /* |
2022 | * We put a few things here that have to be page-aligned. | |
2023 | * This stuff goes at the beginning of the bss, which is page-aligned. | |
2024 | */ | |
2025 | .section ".bss" | |
2026 | ||
2027 | .align PAGE_SHIFT | |
2028 | ||
2029 | .globl empty_zero_page | |
2030 | empty_zero_page: | |
2031 | .space PAGE_SIZE | |
2032 | ||
2033 | .globl swapper_pg_dir | |
2034 | swapper_pg_dir: | |
2035 | .space PAGE_SIZE | |
2036 | ||
2037 | /* | |
2038 | * This space gets a copy of optional info passed to us by the bootstrap | |
2039 | * Used to pass parameters into the kernel like root=/dev/sda1, etc. | |
2040 | */ | |
2041 | .globl cmd_line | |
2042 | cmd_line: | |
2043 | .space COMMAND_LINE_SIZE |