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14cf11af | 1 | /* |
14cf11af PM |
2 | * PowerPC version |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * | |
5 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP | |
6 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> | |
7 | * Adapted for Power Macintosh by Paul Mackerras. | |
8 | * Low-level exception handlers and MMU support | |
9 | * rewritten by Paul Mackerras. | |
10 | * Copyright (C) 1996 Paul Mackerras. | |
11 | * | |
12 | * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and | |
13 | * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com | |
14 | * | |
15 | * This file contains the low-level support and setup for the | |
16 | * PowerPC-64 platform, including trap and interrupt dispatch. | |
17 | * | |
18 | * This program is free software; you can redistribute it and/or | |
19 | * modify it under the terms of the GNU General Public License | |
20 | * as published by the Free Software Foundation; either version | |
21 | * 2 of the License, or (at your option) any later version. | |
22 | */ | |
23 | ||
14cf11af | 24 | #include <linux/threads.h> |
b5bbeb23 | 25 | #include <asm/reg.h> |
14cf11af PM |
26 | #include <asm/page.h> |
27 | #include <asm/mmu.h> | |
14cf11af PM |
28 | #include <asm/ppc_asm.h> |
29 | #include <asm/asm-offsets.h> | |
30 | #include <asm/bug.h> | |
31 | #include <asm/cputable.h> | |
32 | #include <asm/setup.h> | |
33 | #include <asm/hvcall.h> | |
c43a55ff | 34 | #include <asm/iseries/lpar_map.h> |
6cb7bfeb | 35 | #include <asm/thread_info.h> |
3f639ee8 | 36 | #include <asm/firmware.h> |
16a15a30 | 37 | #include <asm/page_64.h> |
f9ff0f30 | 38 | #include <asm/exception.h> |
14cf11af | 39 | |
14cf11af | 40 | #define DO_SOFT_DISABLE |
14cf11af PM |
41 | |
42 | /* | |
43 | * We layout physical memory as follows: | |
44 | * 0x0000 - 0x00ff : Secondary processor spin code | |
45 | * 0x0100 - 0x2fff : pSeries Interrupt prologs | |
46 | * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs | |
47 | * 0x6000 - 0x6fff : Initial (CPU0) segment table | |
48 | * 0x7000 - 0x7fff : FWNMI data area | |
49 | * 0x8000 - : Early init and support code | |
50 | */ | |
51 | ||
52 | /* | |
53 | * SPRG Usage | |
54 | * | |
55 | * Register Definition | |
56 | * | |
57 | * SPRG0 reserved for hypervisor | |
58 | * SPRG1 temp - used to save gpr | |
59 | * SPRG2 temp - used to save gpr | |
60 | * SPRG3 virt addr of paca | |
61 | */ | |
62 | ||
63 | /* | |
64 | * Entering into this code we make the following assumptions: | |
65 | * For pSeries: | |
66 | * 1. The MMU is off & open firmware is running in real mode. | |
67 | * 2. The kernel is entered at __start | |
68 | * | |
69 | * For iSeries: | |
70 | * 1. The MMU is on (as it always is for iSeries) | |
71 | * 2. The kernel is entered at system_reset_iSeries | |
72 | */ | |
73 | ||
74 | .text | |
75 | .globl _stext | |
76 | _stext: | |
14cf11af PM |
77 | _GLOBAL(__start) |
78 | /* NOP this out unconditionally */ | |
79 | BEGIN_FTR_SECTION | |
b85a046a | 80 | b .__start_initialization_multiplatform |
14cf11af | 81 | END_FTR_SECTION(0, 1) |
14cf11af PM |
82 | |
83 | /* Catch branch to 0 in real mode */ | |
84 | trap | |
85 | ||
14cf11af PM |
86 | /* Secondary processors spin on this value until it goes to 1. */ |
87 | .globl __secondary_hold_spinloop | |
88 | __secondary_hold_spinloop: | |
89 | .llong 0x0 | |
90 | ||
91 | /* Secondary processors write this value with their cpu # */ | |
92 | /* after they enter the spin loop immediately below. */ | |
93 | .globl __secondary_hold_acknowledge | |
94 | __secondary_hold_acknowledge: | |
95 | .llong 0x0 | |
96 | ||
1dce0e30 ME |
97 | #ifdef CONFIG_PPC_ISERIES |
98 | /* | |
99 | * At offset 0x20, there is a pointer to iSeries LPAR data. | |
100 | * This is required by the hypervisor | |
101 | */ | |
102 | . = 0x20 | |
103 | .llong hvReleaseData-KERNELBASE | |
104 | #endif /* CONFIG_PPC_ISERIES */ | |
105 | ||
14cf11af PM |
106 | . = 0x60 |
107 | /* | |
75423b7b GL |
108 | * The following code is used to hold secondary processors |
109 | * in a spin loop after they have entered the kernel, but | |
14cf11af PM |
110 | * before the bulk of the kernel has been relocated. This code |
111 | * is relocated to physical address 0x60 before prom_init is run. | |
112 | * All of it must fit below the first exception vector at 0x100. | |
113 | */ | |
114 | _GLOBAL(__secondary_hold) | |
115 | mfmsr r24 | |
116 | ori r24,r24,MSR_RI | |
117 | mtmsrd r24 /* RI on */ | |
118 | ||
f1870f77 | 119 | /* Grab our physical cpu number */ |
14cf11af PM |
120 | mr r24,r3 |
121 | ||
122 | /* Tell the master cpu we're here */ | |
123 | /* Relocation is off & we are located at an address less */ | |
124 | /* than 0x100, so only need to grab low order offset. */ | |
125 | std r24,__secondary_hold_acknowledge@l(0) | |
126 | sync | |
127 | ||
128 | /* All secondary cpus wait here until told to start. */ | |
129 | 100: ld r4,__secondary_hold_spinloop@l(0) | |
130 | cmpdi 0,r4,1 | |
131 | bne 100b | |
132 | ||
f1870f77 | 133 | #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) |
f39b7a55 | 134 | LOAD_REG_IMMEDIATE(r4, .generic_secondary_smp_init) |
758438a7 | 135 | mtctr r4 |
14cf11af | 136 | mr r3,r24 |
758438a7 | 137 | bctr |
14cf11af PM |
138 | #else |
139 | BUG_OPCODE | |
140 | #endif | |
14cf11af PM |
141 | |
142 | /* This value is used to mark exception frames on the stack. */ | |
143 | .section ".toc","aw" | |
144 | exception_marker: | |
145 | .tc ID_72656773_68657265[TC],0x7265677368657265 | |
146 | .text | |
147 | ||
14cf11af PM |
148 | /* |
149 | * This is the start of the interrupt handlers for pSeries | |
150 | * This code runs with relocation off. | |
14cf11af PM |
151 | */ |
152 | . = 0x100 | |
153 | .globl __start_interrupts | |
154 | __start_interrupts: | |
155 | ||
156 | STD_EXCEPTION_PSERIES(0x100, system_reset) | |
157 | ||
158 | . = 0x200 | |
159 | _machine_check_pSeries: | |
160 | HMT_MEDIUM | |
b5bbeb23 | 161 | mtspr SPRN_SPRG1,r13 /* save r13 */ |
14cf11af PM |
162 | EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) |
163 | ||
164 | . = 0x300 | |
165 | .globl data_access_pSeries | |
166 | data_access_pSeries: | |
167 | HMT_MEDIUM | |
b5bbeb23 | 168 | mtspr SPRN_SPRG1,r13 |
14cf11af | 169 | BEGIN_FTR_SECTION |
b5bbeb23 PM |
170 | mtspr SPRN_SPRG2,r12 |
171 | mfspr r13,SPRN_DAR | |
172 | mfspr r12,SPRN_DSISR | |
14cf11af PM |
173 | srdi r13,r13,60 |
174 | rlwimi r13,r12,16,0x20 | |
175 | mfcr r12 | |
176 | cmpwi r13,0x2c | |
3ccfc65c | 177 | beq do_stab_bolted_pSeries |
14cf11af | 178 | mtcrf 0x80,r12 |
b5bbeb23 | 179 | mfspr r12,SPRN_SPRG2 |
14cf11af PM |
180 | END_FTR_SECTION_IFCLR(CPU_FTR_SLB) |
181 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common) | |
182 | ||
183 | . = 0x380 | |
184 | .globl data_access_slb_pSeries | |
185 | data_access_slb_pSeries: | |
186 | HMT_MEDIUM | |
b5bbeb23 | 187 | mtspr SPRN_SPRG1,r13 |
b5bbeb23 | 188 | mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ |
3c726f8d BH |
189 | std r3,PACA_EXSLB+EX_R3(r13) |
190 | mfspr r3,SPRN_DAR | |
14cf11af | 191 | std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ |
3c726f8d BH |
192 | mfcr r9 |
193 | #ifdef __DISABLED__ | |
194 | /* Keep that around for when we re-implement dynamic VSIDs */ | |
195 | cmpdi r3,0 | |
196 | bge slb_miss_user_pseries | |
197 | #endif /* __DISABLED__ */ | |
14cf11af PM |
198 | std r10,PACA_EXSLB+EX_R10(r13) |
199 | std r11,PACA_EXSLB+EX_R11(r13) | |
200 | std r12,PACA_EXSLB+EX_R12(r13) | |
3c726f8d BH |
201 | mfspr r10,SPRN_SPRG1 |
202 | std r10,PACA_EXSLB+EX_R13(r13) | |
b5bbeb23 | 203 | mfspr r12,SPRN_SRR1 /* and SRR1 */ |
3c726f8d | 204 | b .slb_miss_realmode /* Rel. branch works in real mode */ |
14cf11af PM |
205 | |
206 | STD_EXCEPTION_PSERIES(0x400, instruction_access) | |
207 | ||
208 | . = 0x480 | |
209 | .globl instruction_access_slb_pSeries | |
210 | instruction_access_slb_pSeries: | |
211 | HMT_MEDIUM | |
b5bbeb23 | 212 | mtspr SPRN_SPRG1,r13 |
b5bbeb23 | 213 | mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ |
3c726f8d BH |
214 | std r3,PACA_EXSLB+EX_R3(r13) |
215 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
14cf11af | 216 | std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ |
3c726f8d BH |
217 | mfcr r9 |
218 | #ifdef __DISABLED__ | |
219 | /* Keep that around for when we re-implement dynamic VSIDs */ | |
220 | cmpdi r3,0 | |
221 | bge slb_miss_user_pseries | |
222 | #endif /* __DISABLED__ */ | |
14cf11af PM |
223 | std r10,PACA_EXSLB+EX_R10(r13) |
224 | std r11,PACA_EXSLB+EX_R11(r13) | |
225 | std r12,PACA_EXSLB+EX_R12(r13) | |
3c726f8d BH |
226 | mfspr r10,SPRN_SPRG1 |
227 | std r10,PACA_EXSLB+EX_R13(r13) | |
b5bbeb23 | 228 | mfspr r12,SPRN_SRR1 /* and SRR1 */ |
3c726f8d | 229 | b .slb_miss_realmode /* Rel. branch works in real mode */ |
14cf11af | 230 | |
d04c56f7 | 231 | MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt) |
14cf11af PM |
232 | STD_EXCEPTION_PSERIES(0x600, alignment) |
233 | STD_EXCEPTION_PSERIES(0x700, program_check) | |
234 | STD_EXCEPTION_PSERIES(0x800, fp_unavailable) | |
d04c56f7 | 235 | MASKABLE_EXCEPTION_PSERIES(0x900, decrementer) |
14cf11af PM |
236 | STD_EXCEPTION_PSERIES(0xa00, trap_0a) |
237 | STD_EXCEPTION_PSERIES(0xb00, trap_0b) | |
238 | ||
239 | . = 0xc00 | |
240 | .globl system_call_pSeries | |
241 | system_call_pSeries: | |
242 | HMT_MEDIUM | |
14cf11af PM |
243 | mr r9,r13 |
244 | mfmsr r10 | |
b5bbeb23 PM |
245 | mfspr r13,SPRN_SPRG3 |
246 | mfspr r11,SPRN_SRR0 | |
14cf11af PM |
247 | clrrdi r12,r13,32 |
248 | oris r12,r12,system_call_common@h | |
249 | ori r12,r12,system_call_common@l | |
b5bbeb23 | 250 | mtspr SPRN_SRR0,r12 |
14cf11af | 251 | ori r10,r10,MSR_IR|MSR_DR|MSR_RI |
b5bbeb23 PM |
252 | mfspr r12,SPRN_SRR1 |
253 | mtspr SPRN_SRR1,r10 | |
14cf11af PM |
254 | rfid |
255 | b . /* prevent speculative execution */ | |
256 | ||
257 | STD_EXCEPTION_PSERIES(0xd00, single_step) | |
258 | STD_EXCEPTION_PSERIES(0xe00, trap_0e) | |
259 | ||
260 | /* We need to deal with the Altivec unavailable exception | |
261 | * here which is at 0xf20, thus in the middle of the | |
262 | * prolog code of the PerformanceMonitor one. A little | |
263 | * trickery is thus necessary | |
264 | */ | |
265 | . = 0xf00 | |
266 | b performance_monitor_pSeries | |
267 | ||
268 | STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable) | |
269 | ||
acf7d768 BH |
270 | #ifdef CONFIG_CBE_RAS |
271 | HSTD_EXCEPTION_PSERIES(0x1200, cbe_system_error) | |
272 | #endif /* CONFIG_CBE_RAS */ | |
14cf11af | 273 | STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint) |
acf7d768 BH |
274 | #ifdef CONFIG_CBE_RAS |
275 | HSTD_EXCEPTION_PSERIES(0x1600, cbe_maintenance) | |
276 | #endif /* CONFIG_CBE_RAS */ | |
14cf11af | 277 | STD_EXCEPTION_PSERIES(0x1700, altivec_assist) |
acf7d768 BH |
278 | #ifdef CONFIG_CBE_RAS |
279 | HSTD_EXCEPTION_PSERIES(0x1800, cbe_thermal) | |
280 | #endif /* CONFIG_CBE_RAS */ | |
14cf11af PM |
281 | |
282 | . = 0x3000 | |
283 | ||
284 | /*** pSeries interrupt support ***/ | |
285 | ||
286 | /* moved from 0xf00 */ | |
449d846d | 287 | STD_EXCEPTION_PSERIES(., performance_monitor) |
d04c56f7 PM |
288 | |
289 | /* | |
290 | * An interrupt came in while soft-disabled; clear EE in SRR1, | |
291 | * clear paca->hard_enabled and return. | |
292 | */ | |
293 | masked_interrupt: | |
294 | stb r10,PACAHARDIRQEN(r13) | |
295 | mtcrf 0x80,r9 | |
296 | ld r9,PACA_EXGEN+EX_R9(r13) | |
297 | mfspr r10,SPRN_SRR1 | |
298 | rldicl r10,r10,48,1 /* clear MSR_EE */ | |
299 | rotldi r10,r10,16 | |
300 | mtspr SPRN_SRR1,r10 | |
301 | ld r10,PACA_EXGEN+EX_R10(r13) | |
302 | mfspr r13,SPRN_SPRG1 | |
303 | rfid | |
304 | b . | |
14cf11af PM |
305 | |
306 | .align 7 | |
3ccfc65c | 307 | do_stab_bolted_pSeries: |
14cf11af | 308 | mtcrf 0x80,r12 |
b5bbeb23 | 309 | mfspr r12,SPRN_SPRG2 |
14cf11af PM |
310 | EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted) |
311 | ||
3c726f8d BH |
312 | /* |
313 | * We have some room here we use that to put | |
314 | * the peries slb miss user trampoline code so it's reasonably | |
315 | * away from slb_miss_user_common to avoid problems with rfid | |
316 | * | |
317 | * This is used for when the SLB miss handler has to go virtual, | |
318 | * which doesn't happen for now anymore but will once we re-implement | |
319 | * dynamic VSIDs for shared page tables | |
320 | */ | |
321 | #ifdef __DISABLED__ | |
322 | slb_miss_user_pseries: | |
323 | std r10,PACA_EXGEN+EX_R10(r13) | |
324 | std r11,PACA_EXGEN+EX_R11(r13) | |
325 | std r12,PACA_EXGEN+EX_R12(r13) | |
326 | mfspr r10,SPRG1 | |
327 | ld r11,PACA_EXSLB+EX_R9(r13) | |
328 | ld r12,PACA_EXSLB+EX_R3(r13) | |
329 | std r10,PACA_EXGEN+EX_R13(r13) | |
330 | std r11,PACA_EXGEN+EX_R9(r13) | |
331 | std r12,PACA_EXGEN+EX_R3(r13) | |
332 | clrrdi r12,r13,32 | |
333 | mfmsr r10 | |
334 | mfspr r11,SRR0 /* save SRR0 */ | |
335 | ori r12,r12,slb_miss_user_common@l /* virt addr of handler */ | |
336 | ori r10,r10,MSR_IR|MSR_DR|MSR_RI | |
337 | mtspr SRR0,r12 | |
338 | mfspr r12,SRR1 /* and SRR1 */ | |
339 | mtspr SRR1,r10 | |
340 | rfid | |
341 | b . /* prevent spec. execution */ | |
342 | #endif /* __DISABLED__ */ | |
343 | ||
14cf11af PM |
344 | /* |
345 | * Vectors for the FWNMI option. Share common code. | |
346 | */ | |
b5bbeb23 | 347 | .globl system_reset_fwnmi |
8c4f1f29 | 348 | .align 7 |
14cf11af | 349 | system_reset_fwnmi: |
b5bbeb23 PM |
350 | HMT_MEDIUM |
351 | mtspr SPRN_SPRG1,r13 /* save r13 */ | |
9fc0a92c | 352 | EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXGEN, system_reset_common) |
14cf11af | 353 | |
b5bbeb23 | 354 | .globl machine_check_fwnmi |
8c4f1f29 | 355 | .align 7 |
14cf11af | 356 | machine_check_fwnmi: |
b5bbeb23 PM |
357 | HMT_MEDIUM |
358 | mtspr SPRN_SPRG1,r13 /* save r13 */ | |
9fc0a92c | 359 | EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXMC, machine_check_common) |
14cf11af | 360 | |
14cf11af PM |
361 | /*** Common interrupt handlers ***/ |
362 | ||
363 | STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception) | |
364 | ||
365 | /* | |
366 | * Machine check is different because we use a different | |
367 | * save area: PACA_EXMC instead of PACA_EXGEN. | |
368 | */ | |
369 | .align 7 | |
370 | .globl machine_check_common | |
371 | machine_check_common: | |
372 | EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) | |
f39224a8 | 373 | FINISH_NAP |
14cf11af PM |
374 | DISABLE_INTS |
375 | bl .save_nvgprs | |
376 | addi r3,r1,STACK_FRAME_OVERHEAD | |
377 | bl .machine_check_exception | |
378 | b .ret_from_except | |
379 | ||
380 | STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt) | |
381 | STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception) | |
382 | STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception) | |
383 | STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception) | |
384 | STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception) | |
f39224a8 | 385 | STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception) |
14cf11af PM |
386 | STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception) |
387 | #ifdef CONFIG_ALTIVEC | |
388 | STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception) | |
389 | #else | |
390 | STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception) | |
391 | #endif | |
acf7d768 BH |
392 | #ifdef CONFIG_CBE_RAS |
393 | STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception) | |
394 | STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception) | |
395 | STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception) | |
396 | #endif /* CONFIG_CBE_RAS */ | |
14cf11af PM |
397 | |
398 | /* | |
399 | * Here we have detected that the kernel stack pointer is bad. | |
400 | * R9 contains the saved CR, r13 points to the paca, | |
401 | * r10 contains the (bad) kernel stack pointer, | |
402 | * r11 and r12 contain the saved SRR0 and SRR1. | |
403 | * We switch to using an emergency stack, save the registers there, | |
404 | * and call kernel_bad_stack(), which panics. | |
405 | */ | |
406 | bad_stack: | |
407 | ld r1,PACAEMERGSP(r13) | |
408 | subi r1,r1,64+INT_FRAME_SIZE | |
409 | std r9,_CCR(r1) | |
410 | std r10,GPR1(r1) | |
411 | std r11,_NIP(r1) | |
412 | std r12,_MSR(r1) | |
b5bbeb23 PM |
413 | mfspr r11,SPRN_DAR |
414 | mfspr r12,SPRN_DSISR | |
14cf11af PM |
415 | std r11,_DAR(r1) |
416 | std r12,_DSISR(r1) | |
417 | mflr r10 | |
418 | mfctr r11 | |
419 | mfxer r12 | |
420 | std r10,_LINK(r1) | |
421 | std r11,_CTR(r1) | |
422 | std r12,_XER(r1) | |
423 | SAVE_GPR(0,r1) | |
424 | SAVE_GPR(2,r1) | |
425 | SAVE_4GPRS(3,r1) | |
426 | SAVE_2GPRS(7,r1) | |
427 | SAVE_10GPRS(12,r1) | |
428 | SAVE_10GPRS(22,r1) | |
68730401 OJ |
429 | lhz r12,PACA_TRAP_SAVE(r13) |
430 | std r12,_TRAP(r1) | |
14cf11af PM |
431 | addi r11,r1,INT_FRAME_SIZE |
432 | std r11,0(r1) | |
433 | li r12,0 | |
434 | std r12,0(r11) | |
435 | ld r2,PACATOC(r13) | |
436 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
437 | bl .kernel_bad_stack | |
438 | b 1b | |
439 | ||
440 | /* | |
441 | * Return from an exception with minimal checks. | |
442 | * The caller is assumed to have done EXCEPTION_PROLOG_COMMON. | |
443 | * If interrupts have been enabled, or anything has been | |
444 | * done that might have changed the scheduling status of | |
445 | * any task or sent any task a signal, you should use | |
446 | * ret_from_except or ret_from_except_lite instead of this. | |
447 | */ | |
b0a779de PM |
448 | fast_exc_return_irq: /* restores irq state too */ |
449 | ld r3,SOFTE(r1) | |
450 | ld r12,_MSR(r1) | |
451 | stb r3,PACASOFTIRQEN(r13) /* restore paca->soft_enabled */ | |
452 | rldicl r4,r12,49,63 /* get MSR_EE to LSB */ | |
453 | stb r4,PACAHARDIRQEN(r13) /* restore paca->hard_enabled */ | |
454 | b 1f | |
455 | ||
40ef8cbc | 456 | .globl fast_exception_return |
14cf11af PM |
457 | fast_exception_return: |
458 | ld r12,_MSR(r1) | |
b0a779de | 459 | 1: ld r11,_NIP(r1) |
14cf11af PM |
460 | andi. r3,r12,MSR_RI /* check if RI is set */ |
461 | beq- unrecov_fer | |
c6622f63 PM |
462 | |
463 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING | |
464 | andi. r3,r12,MSR_PR | |
465 | beq 2f | |
466 | ACCOUNT_CPU_USER_EXIT(r3, r4) | |
467 | 2: | |
468 | #endif | |
469 | ||
14cf11af PM |
470 | ld r3,_CCR(r1) |
471 | ld r4,_LINK(r1) | |
472 | ld r5,_CTR(r1) | |
473 | ld r6,_XER(r1) | |
474 | mtcr r3 | |
475 | mtlr r4 | |
476 | mtctr r5 | |
477 | mtxer r6 | |
478 | REST_GPR(0, r1) | |
479 | REST_8GPRS(2, r1) | |
480 | ||
481 | mfmsr r10 | |
d04c56f7 PM |
482 | rldicl r10,r10,48,1 /* clear EE */ |
483 | rldicr r10,r10,16,61 /* clear RI (LE is 0 already) */ | |
14cf11af PM |
484 | mtmsrd r10,1 |
485 | ||
b5bbeb23 PM |
486 | mtspr SPRN_SRR1,r12 |
487 | mtspr SPRN_SRR0,r11 | |
14cf11af PM |
488 | REST_4GPRS(10, r1) |
489 | ld r1,GPR1(r1) | |
490 | rfid | |
491 | b . /* prevent speculative execution */ | |
492 | ||
493 | unrecov_fer: | |
494 | bl .save_nvgprs | |
495 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
496 | bl .unrecoverable_exception | |
497 | b 1b | |
498 | ||
499 | /* | |
500 | * Here r13 points to the paca, r9 contains the saved CR, | |
501 | * SRR0 and SRR1 are saved in r11 and r12, | |
502 | * r9 - r13 are saved in paca->exgen. | |
503 | */ | |
504 | .align 7 | |
505 | .globl data_access_common | |
506 | data_access_common: | |
b5bbeb23 | 507 | mfspr r10,SPRN_DAR |
14cf11af | 508 | std r10,PACA_EXGEN+EX_DAR(r13) |
b5bbeb23 | 509 | mfspr r10,SPRN_DSISR |
14cf11af PM |
510 | stw r10,PACA_EXGEN+EX_DSISR(r13) |
511 | EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) | |
512 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
513 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
514 | li r5,0x300 | |
515 | b .do_hash_page /* Try to handle as hpte fault */ | |
516 | ||
517 | .align 7 | |
518 | .globl instruction_access_common | |
519 | instruction_access_common: | |
520 | EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) | |
521 | ld r3,_NIP(r1) | |
522 | andis. r4,r12,0x5820 | |
523 | li r5,0x400 | |
524 | b .do_hash_page /* Try to handle as hpte fault */ | |
525 | ||
3c726f8d BH |
526 | /* |
527 | * Here is the common SLB miss user that is used when going to virtual | |
528 | * mode for SLB misses, that is currently not used | |
529 | */ | |
530 | #ifdef __DISABLED__ | |
531 | .align 7 | |
532 | .globl slb_miss_user_common | |
533 | slb_miss_user_common: | |
534 | mflr r10 | |
535 | std r3,PACA_EXGEN+EX_DAR(r13) | |
536 | stw r9,PACA_EXGEN+EX_CCR(r13) | |
537 | std r10,PACA_EXGEN+EX_LR(r13) | |
538 | std r11,PACA_EXGEN+EX_SRR0(r13) | |
539 | bl .slb_allocate_user | |
540 | ||
541 | ld r10,PACA_EXGEN+EX_LR(r13) | |
542 | ld r3,PACA_EXGEN+EX_R3(r13) | |
543 | lwz r9,PACA_EXGEN+EX_CCR(r13) | |
544 | ld r11,PACA_EXGEN+EX_SRR0(r13) | |
545 | mtlr r10 | |
546 | beq- slb_miss_fault | |
547 | ||
548 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | |
549 | beq- unrecov_user_slb | |
550 | mfmsr r10 | |
551 | ||
552 | .machine push | |
553 | .machine "power4" | |
554 | mtcrf 0x80,r9 | |
555 | .machine pop | |
556 | ||
557 | clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */ | |
558 | mtmsrd r10,1 | |
559 | ||
560 | mtspr SRR0,r11 | |
561 | mtspr SRR1,r12 | |
562 | ||
563 | ld r9,PACA_EXGEN+EX_R9(r13) | |
564 | ld r10,PACA_EXGEN+EX_R10(r13) | |
565 | ld r11,PACA_EXGEN+EX_R11(r13) | |
566 | ld r12,PACA_EXGEN+EX_R12(r13) | |
567 | ld r13,PACA_EXGEN+EX_R13(r13) | |
568 | rfid | |
569 | b . | |
570 | ||
571 | slb_miss_fault: | |
572 | EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN) | |
573 | ld r4,PACA_EXGEN+EX_DAR(r13) | |
574 | li r5,0 | |
575 | std r4,_DAR(r1) | |
576 | std r5,_DSISR(r1) | |
3ccfc65c | 577 | b handle_page_fault |
3c726f8d BH |
578 | |
579 | unrecov_user_slb: | |
580 | EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN) | |
581 | DISABLE_INTS | |
582 | bl .save_nvgprs | |
583 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
584 | bl .unrecoverable_exception | |
585 | b 1b | |
586 | ||
587 | #endif /* __DISABLED__ */ | |
588 | ||
589 | ||
590 | /* | |
591 | * r13 points to the PACA, r9 contains the saved CR, | |
592 | * r12 contain the saved SRR1, SRR0 is still ready for return | |
593 | * r3 has the faulting address | |
594 | * r9 - r13 are saved in paca->exslb. | |
595 | * r3 is saved in paca->slb_r3 | |
596 | * We assume we aren't going to take any exceptions during this procedure. | |
597 | */ | |
598 | _GLOBAL(slb_miss_realmode) | |
599 | mflr r10 | |
600 | ||
601 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | |
602 | std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ | |
603 | ||
604 | bl .slb_allocate_realmode | |
605 | ||
606 | /* All done -- return from exception. */ | |
607 | ||
608 | ld r10,PACA_EXSLB+EX_LR(r13) | |
609 | ld r3,PACA_EXSLB+EX_R3(r13) | |
610 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | |
611 | #ifdef CONFIG_PPC_ISERIES | |
3f639ee8 | 612 | BEGIN_FW_FTR_SECTION |
3356bb9f DG |
613 | ld r11,PACALPPACAPTR(r13) |
614 | ld r11,LPPACASRR0(r11) /* get SRR0 value */ | |
3f639ee8 | 615 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) |
3c726f8d BH |
616 | #endif /* CONFIG_PPC_ISERIES */ |
617 | ||
618 | mtlr r10 | |
619 | ||
620 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | |
621 | beq- unrecov_slb | |
622 | ||
623 | .machine push | |
624 | .machine "power4" | |
625 | mtcrf 0x80,r9 | |
626 | mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ | |
627 | .machine pop | |
628 | ||
629 | #ifdef CONFIG_PPC_ISERIES | |
3f639ee8 | 630 | BEGIN_FW_FTR_SECTION |
3c726f8d BH |
631 | mtspr SPRN_SRR0,r11 |
632 | mtspr SPRN_SRR1,r12 | |
3f639ee8 | 633 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) |
3c726f8d BH |
634 | #endif /* CONFIG_PPC_ISERIES */ |
635 | ld r9,PACA_EXSLB+EX_R9(r13) | |
636 | ld r10,PACA_EXSLB+EX_R10(r13) | |
637 | ld r11,PACA_EXSLB+EX_R11(r13) | |
638 | ld r12,PACA_EXSLB+EX_R12(r13) | |
639 | ld r13,PACA_EXSLB+EX_R13(r13) | |
640 | rfid | |
641 | b . /* prevent speculative execution */ | |
642 | ||
643 | unrecov_slb: | |
644 | EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) | |
645 | DISABLE_INTS | |
646 | bl .save_nvgprs | |
647 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
648 | bl .unrecoverable_exception | |
649 | b 1b | |
650 | ||
14cf11af PM |
651 | .align 7 |
652 | .globl hardware_interrupt_common | |
653 | .globl hardware_interrupt_entry | |
654 | hardware_interrupt_common: | |
655 | EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN) | |
f39224a8 | 656 | FINISH_NAP |
14cf11af PM |
657 | hardware_interrupt_entry: |
658 | DISABLE_INTS | |
a416561b | 659 | BEGIN_FTR_SECTION |
cb2c9b27 | 660 | bl .ppc64_runlatch_on |
a416561b | 661 | END_FTR_SECTION_IFSET(CPU_FTR_CTRL) |
14cf11af PM |
662 | addi r3,r1,STACK_FRAME_OVERHEAD |
663 | bl .do_IRQ | |
664 | b .ret_from_except_lite | |
665 | ||
f39224a8 PM |
666 | #ifdef CONFIG_PPC_970_NAP |
667 | power4_fixup_nap: | |
668 | andc r9,r9,r10 | |
669 | std r9,TI_LOCAL_FLAGS(r11) | |
670 | ld r10,_LINK(r1) /* make idle task do the */ | |
671 | std r10,_NIP(r1) /* equivalent of a blr */ | |
672 | blr | |
673 | #endif | |
674 | ||
14cf11af PM |
675 | .align 7 |
676 | .globl alignment_common | |
677 | alignment_common: | |
b5bbeb23 | 678 | mfspr r10,SPRN_DAR |
14cf11af | 679 | std r10,PACA_EXGEN+EX_DAR(r13) |
b5bbeb23 | 680 | mfspr r10,SPRN_DSISR |
14cf11af PM |
681 | stw r10,PACA_EXGEN+EX_DSISR(r13) |
682 | EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) | |
683 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
684 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
685 | std r3,_DAR(r1) | |
686 | std r4,_DSISR(r1) | |
687 | bl .save_nvgprs | |
688 | addi r3,r1,STACK_FRAME_OVERHEAD | |
689 | ENABLE_INTS | |
690 | bl .alignment_exception | |
691 | b .ret_from_except | |
692 | ||
693 | .align 7 | |
694 | .globl program_check_common | |
695 | program_check_common: | |
696 | EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) | |
697 | bl .save_nvgprs | |
698 | addi r3,r1,STACK_FRAME_OVERHEAD | |
699 | ENABLE_INTS | |
700 | bl .program_check_exception | |
701 | b .ret_from_except | |
702 | ||
703 | .align 7 | |
704 | .globl fp_unavailable_common | |
705 | fp_unavailable_common: | |
706 | EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) | |
3ccfc65c | 707 | bne 1f /* if from user, just load it up */ |
14cf11af PM |
708 | bl .save_nvgprs |
709 | addi r3,r1,STACK_FRAME_OVERHEAD | |
710 | ENABLE_INTS | |
711 | bl .kernel_fp_unavailable_exception | |
712 | BUG_OPCODE | |
3ccfc65c | 713 | 1: b .load_up_fpu |
14cf11af | 714 | |
14cf11af PM |
715 | .align 7 |
716 | .globl altivec_unavailable_common | |
717 | altivec_unavailable_common: | |
718 | EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) | |
719 | #ifdef CONFIG_ALTIVEC | |
720 | BEGIN_FTR_SECTION | |
721 | bne .load_up_altivec /* if from user, just load it up */ | |
722 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
723 | #endif | |
724 | bl .save_nvgprs | |
725 | addi r3,r1,STACK_FRAME_OVERHEAD | |
726 | ENABLE_INTS | |
727 | bl .altivec_unavailable_exception | |
728 | b .ret_from_except | |
729 | ||
730 | #ifdef CONFIG_ALTIVEC | |
731 | /* | |
732 | * load_up_altivec(unused, unused, tsk) | |
733 | * Disable VMX for the task which had it previously, | |
734 | * and save its vector registers in its thread_struct. | |
735 | * Enables the VMX for use in the kernel on return. | |
736 | * On SMP we know the VMX is free, since we give it up every | |
737 | * switch (ie, no lazy save of the vector registers). | |
738 | * On entry: r13 == 'current' && last_task_used_altivec != 'current' | |
739 | */ | |
740 | _STATIC(load_up_altivec) | |
741 | mfmsr r5 /* grab the current MSR */ | |
742 | oris r5,r5,MSR_VEC@h | |
743 | mtmsrd r5 /* enable use of VMX now */ | |
744 | isync | |
745 | ||
746 | /* | |
747 | * For SMP, we don't do lazy VMX switching because it just gets too | |
748 | * horrendously complex, especially when a task switches from one CPU | |
749 | * to another. Instead we call giveup_altvec in switch_to. | |
750 | * VRSAVE isn't dealt with here, that is done in the normal context | |
751 | * switch code. Note that we could rely on vrsave value to eventually | |
752 | * avoid saving all of the VREGs here... | |
753 | */ | |
754 | #ifndef CONFIG_SMP | |
755 | ld r3,last_task_used_altivec@got(r2) | |
756 | ld r4,0(r3) | |
757 | cmpdi 0,r4,0 | |
758 | beq 1f | |
759 | /* Save VMX state to last_task_used_altivec's THREAD struct */ | |
760 | addi r4,r4,THREAD | |
761 | SAVE_32VRS(0,r5,r4) | |
762 | mfvscr vr0 | |
763 | li r10,THREAD_VSCR | |
764 | stvx vr0,r10,r4 | |
765 | /* Disable VMX for last_task_used_altivec */ | |
766 | ld r5,PT_REGS(r4) | |
767 | ld r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
768 | lis r6,MSR_VEC@h | |
769 | andc r4,r4,r6 | |
770 | std r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
771 | 1: | |
772 | #endif /* CONFIG_SMP */ | |
773 | /* Hack: if we get an altivec unavailable trap with VRSAVE | |
774 | * set to all zeros, we assume this is a broken application | |
775 | * that fails to set it properly, and thus we switch it to | |
776 | * all 1's | |
777 | */ | |
778 | mfspr r4,SPRN_VRSAVE | |
779 | cmpdi 0,r4,0 | |
780 | bne+ 1f | |
781 | li r4,-1 | |
782 | mtspr SPRN_VRSAVE,r4 | |
783 | 1: | |
784 | /* enable use of VMX after return */ | |
785 | ld r4,PACACURRENT(r13) | |
786 | addi r5,r4,THREAD /* Get THREAD */ | |
787 | oris r12,r12,MSR_VEC@h | |
788 | std r12,_MSR(r1) | |
789 | li r4,1 | |
790 | li r10,THREAD_VSCR | |
791 | stw r4,THREAD_USED_VR(r5) | |
792 | lvx vr0,r10,r5 | |
793 | mtvscr vr0 | |
794 | REST_32VRS(0,r4,r5) | |
795 | #ifndef CONFIG_SMP | |
796 | /* Update last_task_used_math to 'current' */ | |
797 | subi r4,r5,THREAD /* Back to 'current' */ | |
798 | std r4,0(r3) | |
799 | #endif /* CONFIG_SMP */ | |
800 | /* restore registers and return */ | |
801 | b fast_exception_return | |
802 | #endif /* CONFIG_ALTIVEC */ | |
803 | ||
804 | /* | |
805 | * Hash table stuff | |
806 | */ | |
807 | .align 7 | |
808 | _GLOBAL(do_hash_page) | |
809 | std r3,_DAR(r1) | |
810 | std r4,_DSISR(r1) | |
811 | ||
812 | andis. r0,r4,0xa450 /* weird error? */ | |
3ccfc65c | 813 | bne- handle_page_fault /* if not, try to insert a HPTE */ |
14cf11af PM |
814 | BEGIN_FTR_SECTION |
815 | andis. r0,r4,0x0020 /* Is it a segment table fault? */ | |
3ccfc65c | 816 | bne- do_ste_alloc /* If so handle it */ |
14cf11af PM |
817 | END_FTR_SECTION_IFCLR(CPU_FTR_SLB) |
818 | ||
819 | /* | |
820 | * We need to set the _PAGE_USER bit if MSR_PR is set or if we are | |
821 | * accessing a userspace segment (even from the kernel). We assume | |
822 | * kernel addresses always have the high bit set. | |
823 | */ | |
824 | rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */ | |
825 | rotldi r0,r3,15 /* Move high bit into MSR_PR posn */ | |
826 | orc r0,r12,r0 /* MSR_PR | ~high_bit */ | |
827 | rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */ | |
828 | ori r4,r4,1 /* add _PAGE_PRESENT */ | |
829 | rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */ | |
830 | ||
831 | /* | |
832 | * On iSeries, we soft-disable interrupts here, then | |
833 | * hard-enable interrupts so that the hash_page code can spin on | |
834 | * the hash_table_lock without problems on a shared processor. | |
835 | */ | |
836 | DISABLE_INTS | |
837 | ||
838 | /* | |
839 | * r3 contains the faulting address | |
840 | * r4 contains the required access permissions | |
841 | * r5 contains the trap number | |
842 | * | |
843 | * at return r3 = 0 for success | |
844 | */ | |
845 | bl .hash_page /* build HPTE if possible */ | |
846 | cmpdi r3,0 /* see if hash_page succeeded */ | |
847 | ||
848 | #ifdef DO_SOFT_DISABLE | |
3f639ee8 | 849 | BEGIN_FW_FTR_SECTION |
14cf11af PM |
850 | /* |
851 | * If we had interrupts soft-enabled at the point where the | |
852 | * DSI/ISI occurred, and an interrupt came in during hash_page, | |
853 | * handle it now. | |
854 | * We jump to ret_from_except_lite rather than fast_exception_return | |
855 | * because ret_from_except_lite will check for and handle pending | |
856 | * interrupts if necessary. | |
857 | */ | |
3ccfc65c | 858 | beq 13f |
b0a779de PM |
859 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) |
860 | #endif | |
861 | BEGIN_FW_FTR_SECTION | |
862 | /* | |
863 | * Here we have interrupts hard-disabled, so it is sufficient | |
864 | * to restore paca->{soft,hard}_enable and get out. | |
865 | */ | |
866 | beq fast_exc_return_irq /* Return from exception on success */ | |
867 | END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES) | |
868 | ||
14cf11af PM |
869 | /* For a hash failure, we don't bother re-enabling interrupts */ |
870 | ble- 12f | |
871 | ||
872 | /* | |
873 | * hash_page couldn't handle it, set soft interrupt enable back | |
874 | * to what it was before the trap. Note that .local_irq_restore | |
875 | * handles any interrupts pending at this point. | |
876 | */ | |
877 | ld r3,SOFTE(r1) | |
878 | bl .local_irq_restore | |
879 | b 11f | |
14cf11af PM |
880 | |
881 | /* Here we have a page fault that hash_page can't handle. */ | |
3ccfc65c | 882 | handle_page_fault: |
14cf11af PM |
883 | ENABLE_INTS |
884 | 11: ld r4,_DAR(r1) | |
885 | ld r5,_DSISR(r1) | |
886 | addi r3,r1,STACK_FRAME_OVERHEAD | |
887 | bl .do_page_fault | |
888 | cmpdi r3,0 | |
3ccfc65c | 889 | beq+ 13f |
14cf11af PM |
890 | bl .save_nvgprs |
891 | mr r5,r3 | |
892 | addi r3,r1,STACK_FRAME_OVERHEAD | |
893 | lwz r4,_DAR(r1) | |
894 | bl .bad_page_fault | |
895 | b .ret_from_except | |
896 | ||
79acbb3f PM |
897 | 13: b .ret_from_except_lite |
898 | ||
14cf11af PM |
899 | /* We have a page fault that hash_page could handle but HV refused |
900 | * the PTE insertion | |
901 | */ | |
902 | 12: bl .save_nvgprs | |
903 | addi r3,r1,STACK_FRAME_OVERHEAD | |
904 | lwz r4,_DAR(r1) | |
905 | bl .low_hash_fault | |
906 | b .ret_from_except | |
907 | ||
908 | /* here we have a segment miss */ | |
3ccfc65c | 909 | do_ste_alloc: |
14cf11af PM |
910 | bl .ste_allocate /* try to insert stab entry */ |
911 | cmpdi r3,0 | |
3ccfc65c PM |
912 | bne- handle_page_fault |
913 | b fast_exception_return | |
14cf11af PM |
914 | |
915 | /* | |
916 | * r13 points to the PACA, r9 contains the saved CR, | |
917 | * r11 and r12 contain the saved SRR0 and SRR1. | |
918 | * r9 - r13 are saved in paca->exslb. | |
919 | * We assume we aren't going to take any exceptions during this procedure. | |
920 | * We assume (DAR >> 60) == 0xc. | |
921 | */ | |
922 | .align 7 | |
923 | _GLOBAL(do_stab_bolted) | |
924 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | |
925 | std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */ | |
926 | ||
927 | /* Hash to the primary group */ | |
928 | ld r10,PACASTABVIRT(r13) | |
b5bbeb23 | 929 | mfspr r11,SPRN_DAR |
14cf11af PM |
930 | srdi r11,r11,28 |
931 | rldimi r10,r11,7,52 /* r10 = first ste of the group */ | |
932 | ||
933 | /* Calculate VSID */ | |
934 | /* This is a kernel address, so protovsid = ESID */ | |
935 | ASM_VSID_SCRAMBLE(r11, r9) | |
936 | rldic r9,r11,12,16 /* r9 = vsid << 12 */ | |
937 | ||
938 | /* Search the primary group for a free entry */ | |
939 | 1: ld r11,0(r10) /* Test valid bit of the current ste */ | |
940 | andi. r11,r11,0x80 | |
941 | beq 2f | |
942 | addi r10,r10,16 | |
943 | andi. r11,r10,0x70 | |
944 | bne 1b | |
945 | ||
946 | /* Stick for only searching the primary group for now. */ | |
947 | /* At least for now, we use a very simple random castout scheme */ | |
948 | /* Use the TB as a random number ; OR in 1 to avoid entry 0 */ | |
949 | mftb r11 | |
950 | rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */ | |
951 | ori r11,r11,0x10 | |
952 | ||
953 | /* r10 currently points to an ste one past the group of interest */ | |
954 | /* make it point to the randomly selected entry */ | |
955 | subi r10,r10,128 | |
956 | or r10,r10,r11 /* r10 is the entry to invalidate */ | |
957 | ||
958 | isync /* mark the entry invalid */ | |
959 | ld r11,0(r10) | |
960 | rldicl r11,r11,56,1 /* clear the valid bit */ | |
961 | rotldi r11,r11,8 | |
962 | std r11,0(r10) | |
963 | sync | |
964 | ||
965 | clrrdi r11,r11,28 /* Get the esid part of the ste */ | |
966 | slbie r11 | |
967 | ||
968 | 2: std r9,8(r10) /* Store the vsid part of the ste */ | |
969 | eieio | |
970 | ||
b5bbeb23 | 971 | mfspr r11,SPRN_DAR /* Get the new esid */ |
14cf11af PM |
972 | clrrdi r11,r11,28 /* Permits a full 32b of ESID */ |
973 | ori r11,r11,0x90 /* Turn on valid and kp */ | |
974 | std r11,0(r10) /* Put new entry back into the stab */ | |
975 | ||
976 | sync | |
977 | ||
978 | /* All done -- return from exception. */ | |
979 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | |
980 | ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */ | |
981 | ||
982 | andi. r10,r12,MSR_RI | |
983 | beq- unrecov_slb | |
984 | ||
985 | mtcrf 0x80,r9 /* restore CR */ | |
986 | ||
987 | mfmsr r10 | |
988 | clrrdi r10,r10,2 | |
989 | mtmsrd r10,1 | |
990 | ||
b5bbeb23 PM |
991 | mtspr SPRN_SRR0,r11 |
992 | mtspr SPRN_SRR1,r12 | |
14cf11af PM |
993 | ld r9,PACA_EXSLB+EX_R9(r13) |
994 | ld r10,PACA_EXSLB+EX_R10(r13) | |
995 | ld r11,PACA_EXSLB+EX_R11(r13) | |
996 | ld r12,PACA_EXSLB+EX_R12(r13) | |
997 | ld r13,PACA_EXSLB+EX_R13(r13) | |
998 | rfid | |
999 | b . /* prevent speculative execution */ | |
1000 | ||
14cf11af PM |
1001 | /* |
1002 | * Space for CPU0's segment table. | |
1003 | * | |
1004 | * On iSeries, the hypervisor must fill in at least one entry before | |
16a15a30 SR |
1005 | * we get control (with relocate on). The address is given to the hv |
1006 | * as a page number (see xLparMap below), so this must be at a | |
14cf11af PM |
1007 | * fixed address (the linker can't compute (u64)&initial_stab >> |
1008 | * PAGE_SHIFT). | |
1009 | */ | |
758438a7 | 1010 | . = STAB0_OFFSET /* 0x6000 */ |
14cf11af PM |
1011 | .globl initial_stab |
1012 | initial_stab: | |
1013 | .space 4096 | |
1014 | ||
1015 | /* | |
1016 | * Data area reserved for FWNMI option. | |
1017 | * This address (0x7000) is fixed by the RPA. | |
1018 | */ | |
1019 | .= 0x7000 | |
1020 | .globl fwnmi_data_area | |
1021 | fwnmi_data_area: | |
1022 | ||
1023 | /* iSeries does not use the FWNMI stuff, so it is safe to put | |
1024 | * this here, even if we later allow kernels that will boot on | |
1025 | * both pSeries and iSeries */ | |
1026 | #ifdef CONFIG_PPC_ISERIES | |
1027 | . = LPARMAP_PHYS | |
16a15a30 SR |
1028 | .globl xLparMap |
1029 | xLparMap: | |
1030 | .quad HvEsidsToMap /* xNumberEsids */ | |
1031 | .quad HvRangesToMap /* xNumberRanges */ | |
1032 | .quad STAB0_PAGE /* xSegmentTableOffs */ | |
1033 | .zero 40 /* xRsvd */ | |
1034 | /* xEsids (HvEsidsToMap entries of 2 quads) */ | |
1035 | .quad PAGE_OFFSET_ESID /* xKernelEsid */ | |
1036 | .quad PAGE_OFFSET_VSID /* xKernelVsid */ | |
1037 | .quad VMALLOC_START_ESID /* xKernelEsid */ | |
1038 | .quad VMALLOC_START_VSID /* xKernelVsid */ | |
1039 | /* xRanges (HvRangesToMap entries of 3 quads) */ | |
1040 | .quad HvPagesToMap /* xPages */ | |
1041 | .quad 0 /* xOffset */ | |
1042 | .quad PAGE_OFFSET_VSID << (SID_SHIFT - HW_PAGE_SHIFT) /* xVPN */ | |
1043 | ||
14cf11af PM |
1044 | #endif /* CONFIG_PPC_ISERIES */ |
1045 | ||
1046 | . = 0x8000 | |
1047 | ||
1048 | /* | |
f39b7a55 OJ |
1049 | * On pSeries and most other platforms, secondary processors spin |
1050 | * in the following code. | |
14cf11af PM |
1051 | * At entry, r3 = this processor's number (physical cpu id) |
1052 | */ | |
f39b7a55 | 1053 | _GLOBAL(generic_secondary_smp_init) |
14cf11af PM |
1054 | mr r24,r3 |
1055 | ||
1056 | /* turn on 64-bit mode */ | |
1057 | bl .enable_64b_mode | |
14cf11af | 1058 | |
14cf11af PM |
1059 | /* Set up a paca value for this processor. Since we have the |
1060 | * physical cpu id in r24, we need to search the pacas to find | |
1061 | * which logical id maps to our physical one. | |
1062 | */ | |
e58c3495 | 1063 | LOAD_REG_IMMEDIATE(r13, paca) /* Get base vaddr of paca array */ |
14cf11af PM |
1064 | li r5,0 /* logical cpu id */ |
1065 | 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ | |
1066 | cmpw r6,r24 /* Compare to our id */ | |
1067 | beq 2f | |
1068 | addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */ | |
1069 | addi r5,r5,1 | |
1070 | cmpwi r5,NR_CPUS | |
1071 | blt 1b | |
1072 | ||
1073 | mr r3,r24 /* not found, copy phys to r3 */ | |
1074 | b .kexec_wait /* next kernel might do better */ | |
1075 | ||
b5bbeb23 | 1076 | 2: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */ |
14cf11af PM |
1077 | /* From now on, r24 is expected to be logical cpuid */ |
1078 | mr r24,r5 | |
1079 | 3: HMT_LOW | |
1080 | lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ | |
1081 | /* start. */ | |
1082 | sync | |
1083 | ||
f39b7a55 OJ |
1084 | #ifndef CONFIG_SMP |
1085 | b 3b /* Never go on non-SMP */ | |
1086 | #else | |
1087 | cmpwi 0,r23,0 | |
1088 | beq 3b /* Loop until told to go */ | |
1089 | ||
1090 | /* See if we need to call a cpu state restore handler */ | |
1091 | LOAD_REG_IMMEDIATE(r23, cur_cpu_spec) | |
1092 | ld r23,0(r23) | |
1093 | ld r23,CPU_SPEC_RESTORE(r23) | |
1094 | cmpdi 0,r23,0 | |
1095 | beq 4f | |
1096 | ld r23,0(r23) | |
1097 | mtctr r23 | |
1098 | bctrl | |
1099 | ||
1100 | 4: /* Create a temp kernel stack for use before relocation is on. */ | |
14cf11af PM |
1101 | ld r1,PACAEMERGSP(r13) |
1102 | subi r1,r1,STACK_FRAME_OVERHEAD | |
1103 | ||
c705677e | 1104 | b __secondary_start |
14cf11af | 1105 | #endif |
14cf11af | 1106 | |
14cf11af PM |
1107 | _STATIC(__mmu_off) |
1108 | mfmsr r3 | |
1109 | andi. r0,r3,MSR_IR|MSR_DR | |
1110 | beqlr | |
1111 | andc r3,r3,r0 | |
1112 | mtspr SPRN_SRR0,r4 | |
1113 | mtspr SPRN_SRR1,r3 | |
1114 | sync | |
1115 | rfid | |
1116 | b . /* prevent speculative execution */ | |
1117 | ||
1118 | ||
1119 | /* | |
1120 | * Here is our main kernel entry point. We support currently 2 kind of entries | |
1121 | * depending on the value of r5. | |
1122 | * | |
1123 | * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content | |
1124 | * in r3...r7 | |
1125 | * | |
1126 | * r5 == NULL -> kexec style entry. r3 is a physical pointer to the | |
1127 | * DT block, r4 is a physical pointer to the kernel itself | |
1128 | * | |
1129 | */ | |
1130 | _GLOBAL(__start_initialization_multiplatform) | |
1131 | /* | |
1132 | * Are we booted from a PROM Of-type client-interface ? | |
1133 | */ | |
1134 | cmpldi cr0,r5,0 | |
939e60f6 SR |
1135 | beq 1f |
1136 | b .__boot_from_prom /* yes -> prom */ | |
1137 | 1: | |
14cf11af PM |
1138 | /* Save parameters */ |
1139 | mr r31,r3 | |
1140 | mr r30,r4 | |
1141 | ||
1142 | /* Make sure we are running in 64 bits mode */ | |
1143 | bl .enable_64b_mode | |
1144 | ||
1145 | /* Setup some critical 970 SPRs before switching MMU off */ | |
f39b7a55 OJ |
1146 | mfspr r0,SPRN_PVR |
1147 | srwi r0,r0,16 | |
1148 | cmpwi r0,0x39 /* 970 */ | |
1149 | beq 1f | |
1150 | cmpwi r0,0x3c /* 970FX */ | |
1151 | beq 1f | |
1152 | cmpwi r0,0x44 /* 970MP */ | |
190a24f5 OJ |
1153 | beq 1f |
1154 | cmpwi r0,0x45 /* 970GX */ | |
f39b7a55 OJ |
1155 | bne 2f |
1156 | 1: bl .__cpu_preinit_ppc970 | |
1157 | 2: | |
14cf11af | 1158 | |
14cf11af | 1159 | /* Switch off MMU if not already */ |
e58c3495 | 1160 | LOAD_REG_IMMEDIATE(r4, .__after_prom_start - KERNELBASE) |
14cf11af PM |
1161 | add r4,r4,r30 |
1162 | bl .__mmu_off | |
1163 | b .__after_prom_start | |
1164 | ||
939e60f6 | 1165 | _INIT_STATIC(__boot_from_prom) |
14cf11af PM |
1166 | /* Save parameters */ |
1167 | mr r31,r3 | |
1168 | mr r30,r4 | |
1169 | mr r29,r5 | |
1170 | mr r28,r6 | |
1171 | mr r27,r7 | |
1172 | ||
6088857b OH |
1173 | /* |
1174 | * Align the stack to 16-byte boundary | |
1175 | * Depending on the size and layout of the ELF sections in the initial | |
1176 | * boot binary, the stack pointer will be unalignet on PowerMac | |
1177 | */ | |
c05b4770 LT |
1178 | rldicr r1,r1,0,59 |
1179 | ||
14cf11af PM |
1180 | /* Make sure we are running in 64 bits mode */ |
1181 | bl .enable_64b_mode | |
1182 | ||
1183 | /* put a relocation offset into r3 */ | |
1184 | bl .reloc_offset | |
1185 | ||
e58c3495 | 1186 | LOAD_REG_IMMEDIATE(r2,__toc_start) |
14cf11af PM |
1187 | addi r2,r2,0x4000 |
1188 | addi r2,r2,0x4000 | |
1189 | ||
1190 | /* Relocate the TOC from a virt addr to a real addr */ | |
5a408329 | 1191 | add r2,r2,r3 |
14cf11af PM |
1192 | |
1193 | /* Restore parameters */ | |
1194 | mr r3,r31 | |
1195 | mr r4,r30 | |
1196 | mr r5,r29 | |
1197 | mr r6,r28 | |
1198 | mr r7,r27 | |
1199 | ||
1200 | /* Do all of the interaction with OF client interface */ | |
1201 | bl .prom_init | |
1202 | /* We never return */ | |
1203 | trap | |
1204 | ||
14cf11af PM |
1205 | _STATIC(__after_prom_start) |
1206 | ||
1207 | /* | |
758438a7 | 1208 | * We need to run with __start at physical address PHYSICAL_START. |
14cf11af PM |
1209 | * This will leave some code in the first 256B of |
1210 | * real memory, which are reserved for software use. | |
1211 | * The remainder of the first page is loaded with the fixed | |
1212 | * interrupt vectors. The next two pages are filled with | |
1213 | * unknown exception placeholders. | |
1214 | * | |
1215 | * Note: This process overwrites the OF exception vectors. | |
1216 | * r26 == relocation offset | |
1217 | * r27 == KERNELBASE | |
1218 | */ | |
1219 | bl .reloc_offset | |
1220 | mr r26,r3 | |
e58c3495 | 1221 | LOAD_REG_IMMEDIATE(r27, KERNELBASE) |
14cf11af | 1222 | |
e58c3495 | 1223 | LOAD_REG_IMMEDIATE(r3, PHYSICAL_START) /* target addr */ |
14cf11af PM |
1224 | |
1225 | // XXX FIXME: Use phys returned by OF (r30) | |
5a408329 | 1226 | add r4,r27,r26 /* source addr */ |
14cf11af PM |
1227 | /* current address of _start */ |
1228 | /* i.e. where we are running */ | |
1229 | /* the source addr */ | |
1230 | ||
d0b79c54 | 1231 | cmpdi r4,0 /* In some cases the loader may */ |
939e60f6 SR |
1232 | bne 1f |
1233 | b .start_here_multiplatform /* have already put us at zero */ | |
d0b79c54 | 1234 | /* so we can skip the copy. */ |
939e60f6 | 1235 | 1: LOAD_REG_IMMEDIATE(r5,copy_to_here) /* # bytes of memory to copy */ |
14cf11af PM |
1236 | sub r5,r5,r27 |
1237 | ||
1238 | li r6,0x100 /* Start offset, the first 0x100 */ | |
1239 | /* bytes were copied earlier. */ | |
1240 | ||
1241 | bl .copy_and_flush /* copy the first n bytes */ | |
1242 | /* this includes the code being */ | |
1243 | /* executed here. */ | |
1244 | ||
e58c3495 | 1245 | LOAD_REG_IMMEDIATE(r0, 4f) /* Jump to the copy of this code */ |
14cf11af PM |
1246 | mtctr r0 /* that we just made/relocated */ |
1247 | bctr | |
1248 | ||
e58c3495 | 1249 | 4: LOAD_REG_IMMEDIATE(r5,klimit) |
5a408329 | 1250 | add r5,r5,r26 |
14cf11af PM |
1251 | ld r5,0(r5) /* get the value of klimit */ |
1252 | sub r5,r5,r27 | |
1253 | bl .copy_and_flush /* copy the rest */ | |
1254 | b .start_here_multiplatform | |
1255 | ||
14cf11af PM |
1256 | /* |
1257 | * Copy routine used to copy the kernel to start at physical address 0 | |
1258 | * and flush and invalidate the caches as needed. | |
1259 | * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset | |
1260 | * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. | |
1261 | * | |
1262 | * Note: this routine *only* clobbers r0, r6 and lr | |
1263 | */ | |
1264 | _GLOBAL(copy_and_flush) | |
1265 | addi r5,r5,-8 | |
1266 | addi r6,r6,-8 | |
5a2fe38d | 1267 | 4: li r0,8 /* Use the smallest common */ |
14cf11af PM |
1268 | /* denominator cache line */ |
1269 | /* size. This results in */ | |
1270 | /* extra cache line flushes */ | |
1271 | /* but operation is correct. */ | |
1272 | /* Can't get cache line size */ | |
1273 | /* from NACA as it is being */ | |
1274 | /* moved too. */ | |
1275 | ||
1276 | mtctr r0 /* put # words/line in ctr */ | |
1277 | 3: addi r6,r6,8 /* copy a cache line */ | |
1278 | ldx r0,r6,r4 | |
1279 | stdx r0,r6,r3 | |
1280 | bdnz 3b | |
1281 | dcbst r6,r3 /* write it to memory */ | |
1282 | sync | |
1283 | icbi r6,r3 /* flush the icache line */ | |
1284 | cmpld 0,r6,r5 | |
1285 | blt 4b | |
1286 | sync | |
1287 | addi r5,r5,8 | |
1288 | addi r6,r6,8 | |
1289 | blr | |
1290 | ||
1291 | .align 8 | |
1292 | copy_to_here: | |
1293 | ||
1294 | #ifdef CONFIG_SMP | |
1295 | #ifdef CONFIG_PPC_PMAC | |
1296 | /* | |
1297 | * On PowerMac, secondary processors starts from the reset vector, which | |
1298 | * is temporarily turned into a call to one of the functions below. | |
1299 | */ | |
1300 | .section ".text"; | |
1301 | .align 2 ; | |
1302 | ||
35499c01 PM |
1303 | .globl __secondary_start_pmac_0 |
1304 | __secondary_start_pmac_0: | |
1305 | /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ | |
1306 | li r24,0 | |
1307 | b 1f | |
1308 | li r24,1 | |
1309 | b 1f | |
1310 | li r24,2 | |
1311 | b 1f | |
1312 | li r24,3 | |
1313 | 1: | |
14cf11af PM |
1314 | |
1315 | _GLOBAL(pmac_secondary_start) | |
1316 | /* turn on 64-bit mode */ | |
1317 | bl .enable_64b_mode | |
14cf11af PM |
1318 | |
1319 | /* Copy some CPU settings from CPU 0 */ | |
f39b7a55 | 1320 | bl .__restore_cpu_ppc970 |
14cf11af PM |
1321 | |
1322 | /* pSeries do that early though I don't think we really need it */ | |
1323 | mfmsr r3 | |
1324 | ori r3,r3,MSR_RI | |
1325 | mtmsrd r3 /* RI on */ | |
1326 | ||
1327 | /* Set up a paca value for this processor. */ | |
e58c3495 | 1328 | LOAD_REG_IMMEDIATE(r4, paca) /* Get base vaddr of paca array */ |
14cf11af PM |
1329 | mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ |
1330 | add r13,r13,r4 /* for this processor. */ | |
b5bbeb23 | 1331 | mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */ |
14cf11af PM |
1332 | |
1333 | /* Create a temp kernel stack for use before relocation is on. */ | |
1334 | ld r1,PACAEMERGSP(r13) | |
1335 | subi r1,r1,STACK_FRAME_OVERHEAD | |
1336 | ||
c705677e | 1337 | b __secondary_start |
14cf11af PM |
1338 | |
1339 | #endif /* CONFIG_PPC_PMAC */ | |
1340 | ||
1341 | /* | |
1342 | * This function is called after the master CPU has released the | |
1343 | * secondary processors. The execution environment is relocation off. | |
1344 | * The paca for this processor has the following fields initialized at | |
1345 | * this point: | |
1346 | * 1. Processor number | |
1347 | * 2. Segment table pointer (virtual address) | |
1348 | * On entry the following are set: | |
1349 | * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries | |
1350 | * r24 = cpu# (in Linux terms) | |
1351 | * r13 = paca virtual address | |
1352 | * SPRG3 = paca virtual address | |
1353 | */ | |
fc68e869 | 1354 | .globl __secondary_start |
c705677e | 1355 | __secondary_start: |
799d6046 PM |
1356 | /* Set thread priority to MEDIUM */ |
1357 | HMT_MEDIUM | |
14cf11af | 1358 | |
799d6046 | 1359 | /* Load TOC */ |
14cf11af | 1360 | ld r2,PACATOC(r13) |
799d6046 PM |
1361 | |
1362 | /* Do early setup for that CPU (stab, slb, hash table pointer) */ | |
1363 | bl .early_setup_secondary | |
14cf11af PM |
1364 | |
1365 | /* Initialize the kernel stack. Just a repeat for iSeries. */ | |
e58c3495 | 1366 | LOAD_REG_ADDR(r3, current_set) |
14cf11af PM |
1367 | sldi r28,r24,3 /* get current_set[cpu#] */ |
1368 | ldx r1,r3,r28 | |
1369 | addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD | |
1370 | std r1,PACAKSAVE(r13) | |
1371 | ||
799d6046 | 1372 | /* Clear backchain so we get nice backtraces */ |
14cf11af PM |
1373 | li r7,0 |
1374 | mtlr r7 | |
1375 | ||
1376 | /* enable MMU and jump to start_secondary */ | |
e58c3495 DG |
1377 | LOAD_REG_ADDR(r3, .start_secondary_prolog) |
1378 | LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) | |
d04c56f7 | 1379 | #ifdef CONFIG_PPC_ISERIES |
3f639ee8 | 1380 | BEGIN_FW_FTR_SECTION |
14cf11af | 1381 | ori r4,r4,MSR_EE |
3f639ee8 | 1382 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) |
14cf11af | 1383 | #endif |
d04c56f7 PM |
1384 | BEGIN_FW_FTR_SECTION |
1385 | stb r7,PACASOFTIRQEN(r13) | |
1386 | stb r7,PACAHARDIRQEN(r13) | |
1387 | END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES) | |
1388 | ||
b5bbeb23 PM |
1389 | mtspr SPRN_SRR0,r3 |
1390 | mtspr SPRN_SRR1,r4 | |
14cf11af PM |
1391 | rfid |
1392 | b . /* prevent speculative execution */ | |
1393 | ||
1394 | /* | |
1395 | * Running with relocation on at this point. All we want to do is | |
1396 | * zero the stack back-chain pointer before going into C code. | |
1397 | */ | |
1398 | _GLOBAL(start_secondary_prolog) | |
1399 | li r3,0 | |
1400 | std r3,0(r1) /* Zero the stack frame pointer */ | |
1401 | bl .start_secondary | |
799d6046 | 1402 | b . |
14cf11af PM |
1403 | #endif |
1404 | ||
1405 | /* | |
1406 | * This subroutine clobbers r11 and r12 | |
1407 | */ | |
1408 | _GLOBAL(enable_64b_mode) | |
1409 | mfmsr r11 /* grab the current MSR */ | |
1410 | li r12,1 | |
1411 | rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG) | |
1412 | or r11,r11,r12 | |
1413 | li r12,1 | |
1414 | rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG) | |
1415 | or r11,r11,r12 | |
1416 | mtmsrd r11 | |
1417 | isync | |
1418 | blr | |
1419 | ||
14cf11af PM |
1420 | /* |
1421 | * This is where the main kernel code starts. | |
1422 | */ | |
939e60f6 | 1423 | _INIT_STATIC(start_here_multiplatform) |
14cf11af PM |
1424 | /* get a new offset, now that the kernel has moved. */ |
1425 | bl .reloc_offset | |
1426 | mr r26,r3 | |
1427 | ||
1428 | /* Clear out the BSS. It may have been done in prom_init, | |
1429 | * already but that's irrelevant since prom_init will soon | |
1430 | * be detached from the kernel completely. Besides, we need | |
1431 | * to clear it now for kexec-style entry. | |
1432 | */ | |
e58c3495 DG |
1433 | LOAD_REG_IMMEDIATE(r11,__bss_stop) |
1434 | LOAD_REG_IMMEDIATE(r8,__bss_start) | |
14cf11af PM |
1435 | sub r11,r11,r8 /* bss size */ |
1436 | addi r11,r11,7 /* round up to an even double word */ | |
1437 | rldicl. r11,r11,61,3 /* shift right by 3 */ | |
1438 | beq 4f | |
1439 | addi r8,r8,-8 | |
1440 | li r0,0 | |
1441 | mtctr r11 /* zero this many doublewords */ | |
1442 | 3: stdu r0,8(r8) | |
1443 | bdnz 3b | |
1444 | 4: | |
1445 | ||
1446 | mfmsr r6 | |
1447 | ori r6,r6,MSR_RI | |
1448 | mtmsrd r6 /* RI on */ | |
1449 | ||
14cf11af PM |
1450 | /* The following gets the stack and TOC set up with the regs */ |
1451 | /* pointing to the real addr of the kernel stack. This is */ | |
1452 | /* all done to support the C function call below which sets */ | |
1453 | /* up the htab. This is done because we have relocated the */ | |
1454 | /* kernel but are still running in real mode. */ | |
1455 | ||
e58c3495 | 1456 | LOAD_REG_IMMEDIATE(r3,init_thread_union) |
5a408329 | 1457 | add r3,r3,r26 |
14cf11af PM |
1458 | |
1459 | /* set up a stack pointer (physical address) */ | |
1460 | addi r1,r3,THREAD_SIZE | |
1461 | li r0,0 | |
1462 | stdu r0,-STACK_FRAME_OVERHEAD(r1) | |
1463 | ||
1464 | /* set up the TOC (physical address) */ | |
e58c3495 | 1465 | LOAD_REG_IMMEDIATE(r2,__toc_start) |
14cf11af PM |
1466 | addi r2,r2,0x4000 |
1467 | addi r2,r2,0x4000 | |
5a408329 | 1468 | add r2,r2,r26 |
14cf11af | 1469 | |
14cf11af PM |
1470 | /* Do very early kernel initializations, including initial hash table, |
1471 | * stab and slb setup before we turn on relocation. */ | |
1472 | ||
1473 | /* Restore parameters passed from prom_init/kexec */ | |
1474 | mr r3,r31 | |
1475 | bl .early_setup | |
1476 | ||
e58c3495 DG |
1477 | LOAD_REG_IMMEDIATE(r3, .start_here_common) |
1478 | LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) | |
b5bbeb23 PM |
1479 | mtspr SPRN_SRR0,r3 |
1480 | mtspr SPRN_SRR1,r4 | |
14cf11af PM |
1481 | rfid |
1482 | b . /* prevent speculative execution */ | |
14cf11af PM |
1483 | |
1484 | /* This is where all platforms converge execution */ | |
fc68e869 | 1485 | _INIT_GLOBAL(start_here_common) |
14cf11af PM |
1486 | /* relocation is on at this point */ |
1487 | ||
1488 | /* The following code sets up the SP and TOC now that we are */ | |
1489 | /* running with translation enabled. */ | |
1490 | ||
e58c3495 | 1491 | LOAD_REG_IMMEDIATE(r3,init_thread_union) |
14cf11af PM |
1492 | |
1493 | /* set up the stack */ | |
1494 | addi r1,r3,THREAD_SIZE | |
1495 | li r0,0 | |
1496 | stdu r0,-STACK_FRAME_OVERHEAD(r1) | |
1497 | ||
14cf11af | 1498 | /* ptr to current */ |
e58c3495 | 1499 | LOAD_REG_IMMEDIATE(r4, init_task) |
14cf11af PM |
1500 | std r4,PACACURRENT(r13) |
1501 | ||
1502 | /* Load the TOC */ | |
1503 | ld r2,PACATOC(r13) | |
1504 | std r1,PACAKSAVE(r13) | |
1505 | ||
1506 | bl .setup_system | |
1507 | ||
1508 | /* Load up the kernel context */ | |
1509 | 5: | |
14cf11af | 1510 | li r5,0 |
d04c56f7 PM |
1511 | stb r5,PACASOFTIRQEN(r13) /* Soft Disabled */ |
1512 | #ifdef CONFIG_PPC_ISERIES | |
1513 | BEGIN_FW_FTR_SECTION | |
14cf11af PM |
1514 | mfmsr r5 |
1515 | ori r5,r5,MSR_EE /* Hard Enabled */ | |
1516 | mtmsrd r5 | |
3f639ee8 | 1517 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) |
14cf11af | 1518 | #endif |
d04c56f7 PM |
1519 | BEGIN_FW_FTR_SECTION |
1520 | stb r5,PACAHARDIRQEN(r13) | |
1521 | END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES) | |
14cf11af PM |
1522 | |
1523 | bl .start_kernel | |
1524 | ||
f1870f77 AB |
1525 | /* Not reached */ |
1526 | BUG_OPCODE | |
14cf11af | 1527 | |
14cf11af PM |
1528 | /* |
1529 | * We put a few things here that have to be page-aligned. | |
1530 | * This stuff goes at the beginning of the bss, which is page-aligned. | |
1531 | */ | |
1532 | .section ".bss" | |
1533 | ||
1534 | .align PAGE_SHIFT | |
1535 | ||
1536 | .globl empty_zero_page | |
1537 | empty_zero_page: | |
1538 | .space PAGE_SIZE | |
1539 | ||
1540 | .globl swapper_pg_dir | |
1541 | swapper_pg_dir: | |
1542 | .space PAGE_SIZE |