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14cf11af PM |
1 | /* |
2 | * arch/ppc64/kernel/head.S | |
3 | * | |
4 | * PowerPC version | |
5 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
6 | * | |
7 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP | |
8 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> | |
9 | * Adapted for Power Macintosh by Paul Mackerras. | |
10 | * Low-level exception handlers and MMU support | |
11 | * rewritten by Paul Mackerras. | |
12 | * Copyright (C) 1996 Paul Mackerras. | |
13 | * | |
14 | * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and | |
15 | * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com | |
16 | * | |
17 | * This file contains the low-level support and setup for the | |
18 | * PowerPC-64 platform, including trap and interrupt dispatch. | |
19 | * | |
20 | * This program is free software; you can redistribute it and/or | |
21 | * modify it under the terms of the GNU General Public License | |
22 | * as published by the Free Software Foundation; either version | |
23 | * 2 of the License, or (at your option) any later version. | |
24 | */ | |
25 | ||
26 | #include <linux/config.h> | |
27 | #include <linux/threads.h> | |
b5bbeb23 | 28 | #include <asm/reg.h> |
14cf11af PM |
29 | #include <asm/page.h> |
30 | #include <asm/mmu.h> | |
14cf11af PM |
31 | #include <asm/ppc_asm.h> |
32 | #include <asm/asm-offsets.h> | |
33 | #include <asm/bug.h> | |
34 | #include <asm/cputable.h> | |
35 | #include <asm/setup.h> | |
36 | #include <asm/hvcall.h> | |
c43a55ff | 37 | #include <asm/iseries/lpar_map.h> |
6cb7bfeb | 38 | #include <asm/thread_info.h> |
14cf11af PM |
39 | |
40 | #ifdef CONFIG_PPC_ISERIES | |
41 | #define DO_SOFT_DISABLE | |
42 | #endif | |
43 | ||
44 | /* | |
45 | * We layout physical memory as follows: | |
46 | * 0x0000 - 0x00ff : Secondary processor spin code | |
47 | * 0x0100 - 0x2fff : pSeries Interrupt prologs | |
48 | * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs | |
49 | * 0x6000 - 0x6fff : Initial (CPU0) segment table | |
50 | * 0x7000 - 0x7fff : FWNMI data area | |
51 | * 0x8000 - : Early init and support code | |
52 | */ | |
53 | ||
54 | /* | |
55 | * SPRG Usage | |
56 | * | |
57 | * Register Definition | |
58 | * | |
59 | * SPRG0 reserved for hypervisor | |
60 | * SPRG1 temp - used to save gpr | |
61 | * SPRG2 temp - used to save gpr | |
62 | * SPRG3 virt addr of paca | |
63 | */ | |
64 | ||
65 | /* | |
66 | * Entering into this code we make the following assumptions: | |
67 | * For pSeries: | |
68 | * 1. The MMU is off & open firmware is running in real mode. | |
69 | * 2. The kernel is entered at __start | |
70 | * | |
71 | * For iSeries: | |
72 | * 1. The MMU is on (as it always is for iSeries) | |
73 | * 2. The kernel is entered at system_reset_iSeries | |
74 | */ | |
75 | ||
76 | .text | |
77 | .globl _stext | |
78 | _stext: | |
79 | #ifdef CONFIG_PPC_MULTIPLATFORM | |
80 | _GLOBAL(__start) | |
81 | /* NOP this out unconditionally */ | |
82 | BEGIN_FTR_SECTION | |
b85a046a | 83 | b .__start_initialization_multiplatform |
14cf11af PM |
84 | END_FTR_SECTION(0, 1) |
85 | #endif /* CONFIG_PPC_MULTIPLATFORM */ | |
86 | ||
87 | /* Catch branch to 0 in real mode */ | |
88 | trap | |
89 | ||
90 | #ifdef CONFIG_PPC_ISERIES | |
91 | /* | |
92 | * At offset 0x20, there is a pointer to iSeries LPAR data. | |
93 | * This is required by the hypervisor | |
94 | */ | |
95 | . = 0x20 | |
96 | .llong hvReleaseData-KERNELBASE | |
97 | ||
98 | /* | |
99 | * At offset 0x28 and 0x30 are offsets to the mschunks_map | |
100 | * array (used by the iSeries LPAR debugger to do translation | |
101 | * between physical addresses and absolute addresses) and | |
102 | * to the pidhash table (also used by the debugger) | |
103 | */ | |
104 | .llong mschunks_map-KERNELBASE | |
105 | .llong 0 /* pidhash-KERNELBASE SFRXXX */ | |
106 | ||
107 | /* Offset 0x38 - Pointer to start of embedded System.map */ | |
108 | .globl embedded_sysmap_start | |
109 | embedded_sysmap_start: | |
110 | .llong 0 | |
111 | /* Offset 0x40 - Pointer to end of embedded System.map */ | |
112 | .globl embedded_sysmap_end | |
113 | embedded_sysmap_end: | |
114 | .llong 0 | |
115 | ||
116 | #endif /* CONFIG_PPC_ISERIES */ | |
117 | ||
118 | /* Secondary processors spin on this value until it goes to 1. */ | |
119 | .globl __secondary_hold_spinloop | |
120 | __secondary_hold_spinloop: | |
121 | .llong 0x0 | |
122 | ||
123 | /* Secondary processors write this value with their cpu # */ | |
124 | /* after they enter the spin loop immediately below. */ | |
125 | .globl __secondary_hold_acknowledge | |
126 | __secondary_hold_acknowledge: | |
127 | .llong 0x0 | |
128 | ||
129 | . = 0x60 | |
130 | /* | |
131 | * The following code is used on pSeries to hold secondary processors | |
132 | * in a spin loop after they have been freed from OpenFirmware, but | |
133 | * before the bulk of the kernel has been relocated. This code | |
134 | * is relocated to physical address 0x60 before prom_init is run. | |
135 | * All of it must fit below the first exception vector at 0x100. | |
136 | */ | |
137 | _GLOBAL(__secondary_hold) | |
138 | mfmsr r24 | |
139 | ori r24,r24,MSR_RI | |
140 | mtmsrd r24 /* RI on */ | |
141 | ||
142 | /* Grab our linux cpu number */ | |
143 | mr r24,r3 | |
144 | ||
145 | /* Tell the master cpu we're here */ | |
146 | /* Relocation is off & we are located at an address less */ | |
147 | /* than 0x100, so only need to grab low order offset. */ | |
148 | std r24,__secondary_hold_acknowledge@l(0) | |
149 | sync | |
150 | ||
151 | /* All secondary cpus wait here until told to start. */ | |
152 | 100: ld r4,__secondary_hold_spinloop@l(0) | |
153 | cmpdi 0,r4,1 | |
154 | bne 100b | |
155 | ||
156 | #ifdef CONFIG_HMT | |
157 | b .hmt_init | |
158 | #else | |
159 | #ifdef CONFIG_SMP | |
160 | mr r3,r24 | |
161 | b .pSeries_secondary_smp_init | |
162 | #else | |
163 | BUG_OPCODE | |
164 | #endif | |
165 | #endif | |
166 | ||
167 | /* This value is used to mark exception frames on the stack. */ | |
168 | .section ".toc","aw" | |
169 | exception_marker: | |
170 | .tc ID_72656773_68657265[TC],0x7265677368657265 | |
171 | .text | |
172 | ||
173 | /* | |
174 | * The following macros define the code that appears as | |
175 | * the prologue to each of the exception handlers. They | |
176 | * are split into two parts to allow a single kernel binary | |
177 | * to be used for pSeries and iSeries. | |
178 | * LOL. One day... - paulus | |
179 | */ | |
180 | ||
181 | /* | |
182 | * We make as much of the exception code common between native | |
183 | * exception handlers (including pSeries LPAR) and iSeries LPAR | |
184 | * implementations as possible. | |
185 | */ | |
186 | ||
187 | /* | |
188 | * This is the start of the interrupt handlers for pSeries | |
189 | * This code runs with relocation off. | |
190 | */ | |
191 | #define EX_R9 0 | |
192 | #define EX_R10 8 | |
193 | #define EX_R11 16 | |
194 | #define EX_R12 24 | |
195 | #define EX_R13 32 | |
196 | #define EX_SRR0 40 | |
14cf11af | 197 | #define EX_DAR 48 |
14cf11af PM |
198 | #define EX_DSISR 56 |
199 | #define EX_CCR 60 | |
3c726f8d BH |
200 | #define EX_R3 64 |
201 | #define EX_LR 72 | |
14cf11af PM |
202 | |
203 | #define EXCEPTION_PROLOG_PSERIES(area, label) \ | |
b5bbeb23 | 204 | mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ |
14cf11af PM |
205 | std r9,area+EX_R9(r13); /* save r9 - r12 */ \ |
206 | std r10,area+EX_R10(r13); \ | |
207 | std r11,area+EX_R11(r13); \ | |
208 | std r12,area+EX_R12(r13); \ | |
b5bbeb23 | 209 | mfspr r9,SPRN_SPRG1; \ |
14cf11af PM |
210 | std r9,area+EX_R13(r13); \ |
211 | mfcr r9; \ | |
212 | clrrdi r12,r13,32; /* get high part of &label */ \ | |
213 | mfmsr r10; \ | |
b5bbeb23 | 214 | mfspr r11,SPRN_SRR0; /* save SRR0 */ \ |
14cf11af PM |
215 | ori r12,r12,(label)@l; /* virt addr of handler */ \ |
216 | ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ | |
b5bbeb23 PM |
217 | mtspr SPRN_SRR0,r12; \ |
218 | mfspr r12,SPRN_SRR1; /* and SRR1 */ \ | |
219 | mtspr SPRN_SRR1,r10; \ | |
14cf11af PM |
220 | rfid; \ |
221 | b . /* prevent speculative execution */ | |
222 | ||
223 | /* | |
224 | * This is the start of the interrupt handlers for iSeries | |
225 | * This code runs with relocation on. | |
226 | */ | |
227 | #define EXCEPTION_PROLOG_ISERIES_1(area) \ | |
b5bbeb23 | 228 | mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ |
14cf11af PM |
229 | std r9,area+EX_R9(r13); /* save r9 - r12 */ \ |
230 | std r10,area+EX_R10(r13); \ | |
231 | std r11,area+EX_R11(r13); \ | |
232 | std r12,area+EX_R12(r13); \ | |
b5bbeb23 | 233 | mfspr r9,SPRN_SPRG1; \ |
14cf11af PM |
234 | std r9,area+EX_R13(r13); \ |
235 | mfcr r9 | |
236 | ||
237 | #define EXCEPTION_PROLOG_ISERIES_2 \ | |
238 | mfmsr r10; \ | |
239 | ld r11,PACALPPACA+LPPACASRR0(r13); \ | |
240 | ld r12,PACALPPACA+LPPACASRR1(r13); \ | |
241 | ori r10,r10,MSR_RI; \ | |
242 | mtmsrd r10,1 | |
243 | ||
244 | /* | |
245 | * The common exception prolog is used for all except a few exceptions | |
246 | * such as a segment miss on a kernel address. We have to be prepared | |
247 | * to take another exception from the point where we first touch the | |
248 | * kernel stack onwards. | |
249 | * | |
250 | * On entry r13 points to the paca, r9-r13 are saved in the paca, | |
251 | * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and | |
252 | * SRR1, and relocation is on. | |
253 | */ | |
254 | #define EXCEPTION_PROLOG_COMMON(n, area) \ | |
255 | andi. r10,r12,MSR_PR; /* See if coming from user */ \ | |
256 | mr r10,r1; /* Save r1 */ \ | |
257 | subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ | |
258 | beq- 1f; \ | |
259 | ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ | |
260 | 1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \ | |
261 | bge- cr1,bad_stack; /* abort if it is */ \ | |
262 | std r9,_CCR(r1); /* save CR in stackframe */ \ | |
263 | std r11,_NIP(r1); /* save SRR0 in stackframe */ \ | |
264 | std r12,_MSR(r1); /* save SRR1 in stackframe */ \ | |
265 | std r10,0(r1); /* make stack chain pointer */ \ | |
266 | std r0,GPR0(r1); /* save r0 in stackframe */ \ | |
267 | std r10,GPR1(r1); /* save r1 in stackframe */ \ | |
268 | std r2,GPR2(r1); /* save r2 in stackframe */ \ | |
269 | SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ | |
270 | SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ | |
271 | ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ | |
272 | ld r10,area+EX_R10(r13); \ | |
273 | std r9,GPR9(r1); \ | |
274 | std r10,GPR10(r1); \ | |
275 | ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ | |
276 | ld r10,area+EX_R12(r13); \ | |
277 | ld r11,area+EX_R13(r13); \ | |
278 | std r9,GPR11(r1); \ | |
279 | std r10,GPR12(r1); \ | |
280 | std r11,GPR13(r1); \ | |
281 | ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ | |
282 | mflr r9; /* save LR in stackframe */ \ | |
283 | std r9,_LINK(r1); \ | |
284 | mfctr r10; /* save CTR in stackframe */ \ | |
285 | std r10,_CTR(r1); \ | |
b5bbeb23 | 286 | mfspr r11,SPRN_XER; /* save XER in stackframe */ \ |
14cf11af PM |
287 | std r11,_XER(r1); \ |
288 | li r9,(n)+1; \ | |
289 | std r9,_TRAP(r1); /* set trap number */ \ | |
290 | li r10,0; \ | |
291 | ld r11,exception_marker@toc(r2); \ | |
292 | std r10,RESULT(r1); /* clear regs->result */ \ | |
293 | std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ | |
294 | ||
295 | /* | |
296 | * Exception vectors. | |
297 | */ | |
298 | #define STD_EXCEPTION_PSERIES(n, label) \ | |
299 | . = n; \ | |
300 | .globl label##_pSeries; \ | |
301 | label##_pSeries: \ | |
302 | HMT_MEDIUM; \ | |
b5bbeb23 | 303 | mtspr SPRN_SPRG1,r13; /* save r13 */ \ |
14cf11af PM |
304 | RUNLATCH_ON(r13); \ |
305 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common) | |
306 | ||
307 | #define STD_EXCEPTION_ISERIES(n, label, area) \ | |
308 | .globl label##_iSeries; \ | |
309 | label##_iSeries: \ | |
310 | HMT_MEDIUM; \ | |
b5bbeb23 | 311 | mtspr SPRN_SPRG1,r13; /* save r13 */ \ |
14cf11af PM |
312 | RUNLATCH_ON(r13); \ |
313 | EXCEPTION_PROLOG_ISERIES_1(area); \ | |
314 | EXCEPTION_PROLOG_ISERIES_2; \ | |
315 | b label##_common | |
316 | ||
317 | #define MASKABLE_EXCEPTION_ISERIES(n, label) \ | |
318 | .globl label##_iSeries; \ | |
319 | label##_iSeries: \ | |
320 | HMT_MEDIUM; \ | |
b5bbeb23 | 321 | mtspr SPRN_SPRG1,r13; /* save r13 */ \ |
14cf11af PM |
322 | RUNLATCH_ON(r13); \ |
323 | EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \ | |
324 | lbz r10,PACAPROCENABLED(r13); \ | |
325 | cmpwi 0,r10,0; \ | |
326 | beq- label##_iSeries_masked; \ | |
327 | EXCEPTION_PROLOG_ISERIES_2; \ | |
328 | b label##_common; \ | |
329 | ||
330 | #ifdef DO_SOFT_DISABLE | |
331 | #define DISABLE_INTS \ | |
332 | lbz r10,PACAPROCENABLED(r13); \ | |
333 | li r11,0; \ | |
334 | std r10,SOFTE(r1); \ | |
335 | mfmsr r10; \ | |
336 | stb r11,PACAPROCENABLED(r13); \ | |
337 | ori r10,r10,MSR_EE; \ | |
338 | mtmsrd r10,1 | |
339 | ||
340 | #define ENABLE_INTS \ | |
341 | lbz r10,PACAPROCENABLED(r13); \ | |
342 | mfmsr r11; \ | |
343 | std r10,SOFTE(r1); \ | |
344 | ori r11,r11,MSR_EE; \ | |
345 | mtmsrd r11,1 | |
346 | ||
347 | #else /* hard enable/disable interrupts */ | |
348 | #define DISABLE_INTS | |
349 | ||
350 | #define ENABLE_INTS \ | |
351 | ld r12,_MSR(r1); \ | |
352 | mfmsr r11; \ | |
353 | rlwimi r11,r12,0,MSR_EE; \ | |
354 | mtmsrd r11,1 | |
355 | ||
356 | #endif | |
357 | ||
358 | #define STD_EXCEPTION_COMMON(trap, label, hdlr) \ | |
359 | .align 7; \ | |
360 | .globl label##_common; \ | |
361 | label##_common: \ | |
362 | EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ | |
363 | DISABLE_INTS; \ | |
364 | bl .save_nvgprs; \ | |
365 | addi r3,r1,STACK_FRAME_OVERHEAD; \ | |
366 | bl hdlr; \ | |
367 | b .ret_from_except | |
368 | ||
369 | #define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \ | |
370 | .align 7; \ | |
371 | .globl label##_common; \ | |
372 | label##_common: \ | |
373 | EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ | |
374 | DISABLE_INTS; \ | |
375 | addi r3,r1,STACK_FRAME_OVERHEAD; \ | |
376 | bl hdlr; \ | |
377 | b .ret_from_except_lite | |
378 | ||
379 | /* | |
380 | * Start of pSeries system interrupt routines | |
381 | */ | |
382 | . = 0x100 | |
383 | .globl __start_interrupts | |
384 | __start_interrupts: | |
385 | ||
386 | STD_EXCEPTION_PSERIES(0x100, system_reset) | |
387 | ||
388 | . = 0x200 | |
389 | _machine_check_pSeries: | |
390 | HMT_MEDIUM | |
b5bbeb23 | 391 | mtspr SPRN_SPRG1,r13 /* save r13 */ |
14cf11af PM |
392 | RUNLATCH_ON(r13) |
393 | EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) | |
394 | ||
395 | . = 0x300 | |
396 | .globl data_access_pSeries | |
397 | data_access_pSeries: | |
398 | HMT_MEDIUM | |
b5bbeb23 | 399 | mtspr SPRN_SPRG1,r13 |
14cf11af | 400 | BEGIN_FTR_SECTION |
b5bbeb23 PM |
401 | mtspr SPRN_SPRG2,r12 |
402 | mfspr r13,SPRN_DAR | |
403 | mfspr r12,SPRN_DSISR | |
14cf11af PM |
404 | srdi r13,r13,60 |
405 | rlwimi r13,r12,16,0x20 | |
406 | mfcr r12 | |
407 | cmpwi r13,0x2c | |
408 | beq .do_stab_bolted_pSeries | |
409 | mtcrf 0x80,r12 | |
b5bbeb23 | 410 | mfspr r12,SPRN_SPRG2 |
14cf11af PM |
411 | END_FTR_SECTION_IFCLR(CPU_FTR_SLB) |
412 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common) | |
413 | ||
414 | . = 0x380 | |
415 | .globl data_access_slb_pSeries | |
416 | data_access_slb_pSeries: | |
417 | HMT_MEDIUM | |
b5bbeb23 | 418 | mtspr SPRN_SPRG1,r13 |
14cf11af | 419 | RUNLATCH_ON(r13) |
b5bbeb23 | 420 | mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ |
3c726f8d BH |
421 | std r3,PACA_EXSLB+EX_R3(r13) |
422 | mfspr r3,SPRN_DAR | |
14cf11af | 423 | std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ |
3c726f8d BH |
424 | mfcr r9 |
425 | #ifdef __DISABLED__ | |
426 | /* Keep that around for when we re-implement dynamic VSIDs */ | |
427 | cmpdi r3,0 | |
428 | bge slb_miss_user_pseries | |
429 | #endif /* __DISABLED__ */ | |
14cf11af PM |
430 | std r10,PACA_EXSLB+EX_R10(r13) |
431 | std r11,PACA_EXSLB+EX_R11(r13) | |
432 | std r12,PACA_EXSLB+EX_R12(r13) | |
3c726f8d BH |
433 | mfspr r10,SPRN_SPRG1 |
434 | std r10,PACA_EXSLB+EX_R13(r13) | |
b5bbeb23 | 435 | mfspr r12,SPRN_SRR1 /* and SRR1 */ |
3c726f8d | 436 | b .slb_miss_realmode /* Rel. branch works in real mode */ |
14cf11af PM |
437 | |
438 | STD_EXCEPTION_PSERIES(0x400, instruction_access) | |
439 | ||
440 | . = 0x480 | |
441 | .globl instruction_access_slb_pSeries | |
442 | instruction_access_slb_pSeries: | |
443 | HMT_MEDIUM | |
b5bbeb23 | 444 | mtspr SPRN_SPRG1,r13 |
14cf11af | 445 | RUNLATCH_ON(r13) |
b5bbeb23 | 446 | mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ |
3c726f8d BH |
447 | std r3,PACA_EXSLB+EX_R3(r13) |
448 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
14cf11af | 449 | std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ |
3c726f8d BH |
450 | mfcr r9 |
451 | #ifdef __DISABLED__ | |
452 | /* Keep that around for when we re-implement dynamic VSIDs */ | |
453 | cmpdi r3,0 | |
454 | bge slb_miss_user_pseries | |
455 | #endif /* __DISABLED__ */ | |
14cf11af PM |
456 | std r10,PACA_EXSLB+EX_R10(r13) |
457 | std r11,PACA_EXSLB+EX_R11(r13) | |
458 | std r12,PACA_EXSLB+EX_R12(r13) | |
3c726f8d BH |
459 | mfspr r10,SPRN_SPRG1 |
460 | std r10,PACA_EXSLB+EX_R13(r13) | |
b5bbeb23 | 461 | mfspr r12,SPRN_SRR1 /* and SRR1 */ |
3c726f8d | 462 | b .slb_miss_realmode /* Rel. branch works in real mode */ |
14cf11af PM |
463 | |
464 | STD_EXCEPTION_PSERIES(0x500, hardware_interrupt) | |
465 | STD_EXCEPTION_PSERIES(0x600, alignment) | |
466 | STD_EXCEPTION_PSERIES(0x700, program_check) | |
467 | STD_EXCEPTION_PSERIES(0x800, fp_unavailable) | |
468 | STD_EXCEPTION_PSERIES(0x900, decrementer) | |
469 | STD_EXCEPTION_PSERIES(0xa00, trap_0a) | |
470 | STD_EXCEPTION_PSERIES(0xb00, trap_0b) | |
471 | ||
472 | . = 0xc00 | |
473 | .globl system_call_pSeries | |
474 | system_call_pSeries: | |
475 | HMT_MEDIUM | |
476 | RUNLATCH_ON(r9) | |
477 | mr r9,r13 | |
478 | mfmsr r10 | |
b5bbeb23 PM |
479 | mfspr r13,SPRN_SPRG3 |
480 | mfspr r11,SPRN_SRR0 | |
14cf11af PM |
481 | clrrdi r12,r13,32 |
482 | oris r12,r12,system_call_common@h | |
483 | ori r12,r12,system_call_common@l | |
b5bbeb23 | 484 | mtspr SPRN_SRR0,r12 |
14cf11af | 485 | ori r10,r10,MSR_IR|MSR_DR|MSR_RI |
b5bbeb23 PM |
486 | mfspr r12,SPRN_SRR1 |
487 | mtspr SPRN_SRR1,r10 | |
14cf11af PM |
488 | rfid |
489 | b . /* prevent speculative execution */ | |
490 | ||
491 | STD_EXCEPTION_PSERIES(0xd00, single_step) | |
492 | STD_EXCEPTION_PSERIES(0xe00, trap_0e) | |
493 | ||
494 | /* We need to deal with the Altivec unavailable exception | |
495 | * here which is at 0xf20, thus in the middle of the | |
496 | * prolog code of the PerformanceMonitor one. A little | |
497 | * trickery is thus necessary | |
498 | */ | |
499 | . = 0xf00 | |
500 | b performance_monitor_pSeries | |
501 | ||
502 | STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable) | |
503 | ||
504 | STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint) | |
505 | STD_EXCEPTION_PSERIES(0x1700, altivec_assist) | |
506 | ||
507 | . = 0x3000 | |
508 | ||
509 | /*** pSeries interrupt support ***/ | |
510 | ||
511 | /* moved from 0xf00 */ | |
512 | STD_EXCEPTION_PSERIES(., performance_monitor) | |
513 | ||
514 | .align 7 | |
515 | _GLOBAL(do_stab_bolted_pSeries) | |
516 | mtcrf 0x80,r12 | |
b5bbeb23 | 517 | mfspr r12,SPRN_SPRG2 |
14cf11af PM |
518 | EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted) |
519 | ||
3c726f8d BH |
520 | /* |
521 | * We have some room here we use that to put | |
522 | * the peries slb miss user trampoline code so it's reasonably | |
523 | * away from slb_miss_user_common to avoid problems with rfid | |
524 | * | |
525 | * This is used for when the SLB miss handler has to go virtual, | |
526 | * which doesn't happen for now anymore but will once we re-implement | |
527 | * dynamic VSIDs for shared page tables | |
528 | */ | |
529 | #ifdef __DISABLED__ | |
530 | slb_miss_user_pseries: | |
531 | std r10,PACA_EXGEN+EX_R10(r13) | |
532 | std r11,PACA_EXGEN+EX_R11(r13) | |
533 | std r12,PACA_EXGEN+EX_R12(r13) | |
534 | mfspr r10,SPRG1 | |
535 | ld r11,PACA_EXSLB+EX_R9(r13) | |
536 | ld r12,PACA_EXSLB+EX_R3(r13) | |
537 | std r10,PACA_EXGEN+EX_R13(r13) | |
538 | std r11,PACA_EXGEN+EX_R9(r13) | |
539 | std r12,PACA_EXGEN+EX_R3(r13) | |
540 | clrrdi r12,r13,32 | |
541 | mfmsr r10 | |
542 | mfspr r11,SRR0 /* save SRR0 */ | |
543 | ori r12,r12,slb_miss_user_common@l /* virt addr of handler */ | |
544 | ori r10,r10,MSR_IR|MSR_DR|MSR_RI | |
545 | mtspr SRR0,r12 | |
546 | mfspr r12,SRR1 /* and SRR1 */ | |
547 | mtspr SRR1,r10 | |
548 | rfid | |
549 | b . /* prevent spec. execution */ | |
550 | #endif /* __DISABLED__ */ | |
551 | ||
14cf11af PM |
552 | /* |
553 | * Vectors for the FWNMI option. Share common code. | |
554 | */ | |
b5bbeb23 | 555 | .globl system_reset_fwnmi |
14cf11af | 556 | system_reset_fwnmi: |
b5bbeb23 PM |
557 | HMT_MEDIUM |
558 | mtspr SPRN_SPRG1,r13 /* save r13 */ | |
559 | RUNLATCH_ON(r13) | |
560 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common) | |
14cf11af | 561 | |
b5bbeb23 | 562 | .globl machine_check_fwnmi |
14cf11af | 563 | machine_check_fwnmi: |
b5bbeb23 PM |
564 | HMT_MEDIUM |
565 | mtspr SPRN_SPRG1,r13 /* save r13 */ | |
566 | RUNLATCH_ON(r13) | |
567 | EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) | |
14cf11af PM |
568 | |
569 | #ifdef CONFIG_PPC_ISERIES | |
570 | /*** ISeries-LPAR interrupt handlers ***/ | |
571 | ||
572 | STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC) | |
573 | ||
574 | .globl data_access_iSeries | |
575 | data_access_iSeries: | |
b5bbeb23 | 576 | mtspr SPRN_SPRG1,r13 |
14cf11af | 577 | BEGIN_FTR_SECTION |
b5bbeb23 PM |
578 | mtspr SPRN_SPRG2,r12 |
579 | mfspr r13,SPRN_DAR | |
580 | mfspr r12,SPRN_DSISR | |
14cf11af PM |
581 | srdi r13,r13,60 |
582 | rlwimi r13,r12,16,0x20 | |
583 | mfcr r12 | |
584 | cmpwi r13,0x2c | |
585 | beq .do_stab_bolted_iSeries | |
586 | mtcrf 0x80,r12 | |
b5bbeb23 | 587 | mfspr r12,SPRN_SPRG2 |
14cf11af PM |
588 | END_FTR_SECTION_IFCLR(CPU_FTR_SLB) |
589 | EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN) | |
590 | EXCEPTION_PROLOG_ISERIES_2 | |
591 | b data_access_common | |
592 | ||
593 | .do_stab_bolted_iSeries: | |
594 | mtcrf 0x80,r12 | |
b5bbeb23 | 595 | mfspr r12,SPRN_SPRG2 |
14cf11af PM |
596 | EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB) |
597 | EXCEPTION_PROLOG_ISERIES_2 | |
598 | b .do_stab_bolted | |
599 | ||
600 | .globl data_access_slb_iSeries | |
601 | data_access_slb_iSeries: | |
b5bbeb23 | 602 | mtspr SPRN_SPRG1,r13 /* save r13 */ |
3c726f8d | 603 | mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ |
14cf11af | 604 | std r3,PACA_EXSLB+EX_R3(r13) |
b5bbeb23 | 605 | mfspr r3,SPRN_DAR |
3c726f8d BH |
606 | std r9,PACA_EXSLB+EX_R9(r13) |
607 | mfcr r9 | |
608 | #ifdef __DISABLED__ | |
609 | cmpdi r3,0 | |
610 | bge slb_miss_user_iseries | |
611 | #endif | |
612 | std r10,PACA_EXSLB+EX_R10(r13) | |
613 | std r11,PACA_EXSLB+EX_R11(r13) | |
614 | std r12,PACA_EXSLB+EX_R12(r13) | |
615 | mfspr r10,SPRN_SPRG1 | |
616 | std r10,PACA_EXSLB+EX_R13(r13) | |
617 | ld r12,PACALPPACA+LPPACASRR1(r13); | |
618 | b .slb_miss_realmode | |
14cf11af PM |
619 | |
620 | STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN) | |
621 | ||
622 | .globl instruction_access_slb_iSeries | |
623 | instruction_access_slb_iSeries: | |
b5bbeb23 | 624 | mtspr SPRN_SPRG1,r13 /* save r13 */ |
3c726f8d | 625 | mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ |
14cf11af | 626 | std r3,PACA_EXSLB+EX_R3(r13) |
3c726f8d BH |
627 | ld r3,PACALPPACA+LPPACASRR0(r13) /* get SRR0 value */ |
628 | std r9,PACA_EXSLB+EX_R9(r13) | |
629 | mfcr r9 | |
630 | #ifdef __DISABLED__ | |
631 | cmpdi r3,0 | |
632 | bge .slb_miss_user_iseries | |
633 | #endif | |
634 | std r10,PACA_EXSLB+EX_R10(r13) | |
635 | std r11,PACA_EXSLB+EX_R11(r13) | |
636 | std r12,PACA_EXSLB+EX_R12(r13) | |
637 | mfspr r10,SPRN_SPRG1 | |
638 | std r10,PACA_EXSLB+EX_R13(r13) | |
639 | ld r12,PACALPPACA+LPPACASRR1(r13); | |
640 | b .slb_miss_realmode | |
641 | ||
642 | #ifdef __DISABLED__ | |
643 | slb_miss_user_iseries: | |
644 | std r10,PACA_EXGEN+EX_R10(r13) | |
645 | std r11,PACA_EXGEN+EX_R11(r13) | |
646 | std r12,PACA_EXGEN+EX_R12(r13) | |
647 | mfspr r10,SPRG1 | |
648 | ld r11,PACA_EXSLB+EX_R9(r13) | |
649 | ld r12,PACA_EXSLB+EX_R3(r13) | |
650 | std r10,PACA_EXGEN+EX_R13(r13) | |
651 | std r11,PACA_EXGEN+EX_R9(r13) | |
652 | std r12,PACA_EXGEN+EX_R3(r13) | |
653 | EXCEPTION_PROLOG_ISERIES_2 | |
654 | b slb_miss_user_common | |
655 | #endif | |
14cf11af PM |
656 | |
657 | MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt) | |
658 | STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN) | |
659 | STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN) | |
660 | STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN) | |
661 | MASKABLE_EXCEPTION_ISERIES(0x900, decrementer) | |
662 | STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN) | |
663 | STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN) | |
664 | ||
665 | .globl system_call_iSeries | |
666 | system_call_iSeries: | |
667 | mr r9,r13 | |
b5bbeb23 | 668 | mfspr r13,SPRN_SPRG3 |
14cf11af PM |
669 | EXCEPTION_PROLOG_ISERIES_2 |
670 | b system_call_common | |
671 | ||
672 | STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN) | |
673 | STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN) | |
674 | STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN) | |
675 | ||
676 | .globl system_reset_iSeries | |
677 | system_reset_iSeries: | |
b5bbeb23 | 678 | mfspr r13,SPRN_SPRG3 /* Get paca address */ |
14cf11af PM |
679 | mfmsr r24 |
680 | ori r24,r24,MSR_RI | |
681 | mtmsrd r24 /* RI on */ | |
682 | lhz r24,PACAPACAINDEX(r13) /* Get processor # */ | |
683 | cmpwi 0,r24,0 /* Are we processor 0? */ | |
684 | beq .__start_initialization_iSeries /* Start up the first processor */ | |
685 | mfspr r4,SPRN_CTRLF | |
686 | li r5,CTRL_RUNLATCH /* Turn off the run light */ | |
687 | andc r4,r4,r5 | |
688 | mtspr SPRN_CTRLT,r4 | |
689 | ||
690 | 1: | |
691 | HMT_LOW | |
692 | #ifdef CONFIG_SMP | |
693 | lbz r23,PACAPROCSTART(r13) /* Test if this processor | |
694 | * should start */ | |
695 | sync | |
696 | LOADADDR(r3,current_set) | |
697 | sldi r28,r24,3 /* get current_set[cpu#] */ | |
698 | ldx r3,r3,r28 | |
699 | addi r1,r3,THREAD_SIZE | |
700 | subi r1,r1,STACK_FRAME_OVERHEAD | |
701 | ||
702 | cmpwi 0,r23,0 | |
703 | beq iSeries_secondary_smp_loop /* Loop until told to go */ | |
704 | bne .__secondary_start /* Loop until told to go */ | |
705 | iSeries_secondary_smp_loop: | |
706 | /* Let the Hypervisor know we are alive */ | |
707 | /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */ | |
708 | lis r3,0x8002 | |
709 | rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */ | |
710 | #else /* CONFIG_SMP */ | |
711 | /* Yield the processor. This is required for non-SMP kernels | |
712 | which are running on multi-threaded machines. */ | |
713 | lis r3,0x8000 | |
714 | rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */ | |
715 | addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */ | |
716 | li r4,0 /* "yield timed" */ | |
717 | li r5,-1 /* "yield forever" */ | |
718 | #endif /* CONFIG_SMP */ | |
719 | li r0,-1 /* r0=-1 indicates a Hypervisor call */ | |
720 | sc /* Invoke the hypervisor via a system call */ | |
b5bbeb23 | 721 | mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */ |
14cf11af PM |
722 | b 1b /* If SMP not configured, secondaries |
723 | * loop forever */ | |
724 | ||
725 | .globl decrementer_iSeries_masked | |
726 | decrementer_iSeries_masked: | |
727 | li r11,1 | |
728 | stb r11,PACALPPACA+LPPACADECRINT(r13) | |
404849bb | 729 | LOADBASE(r12,tb_ticks_per_jiffy) |
4693c09a | 730 | lwz r12,OFF(tb_ticks_per_jiffy)(r12) |
14cf11af PM |
731 | mtspr SPRN_DEC,r12 |
732 | /* fall through */ | |
733 | ||
734 | .globl hardware_interrupt_iSeries_masked | |
735 | hardware_interrupt_iSeries_masked: | |
736 | mtcrf 0x80,r9 /* Restore regs */ | |
737 | ld r11,PACALPPACA+LPPACASRR0(r13) | |
738 | ld r12,PACALPPACA+LPPACASRR1(r13) | |
b5bbeb23 PM |
739 | mtspr SPRN_SRR0,r11 |
740 | mtspr SPRN_SRR1,r12 | |
14cf11af PM |
741 | ld r9,PACA_EXGEN+EX_R9(r13) |
742 | ld r10,PACA_EXGEN+EX_R10(r13) | |
743 | ld r11,PACA_EXGEN+EX_R11(r13) | |
744 | ld r12,PACA_EXGEN+EX_R12(r13) | |
745 | ld r13,PACA_EXGEN+EX_R13(r13) | |
746 | rfid | |
747 | b . /* prevent speculative execution */ | |
748 | #endif /* CONFIG_PPC_ISERIES */ | |
749 | ||
750 | /*** Common interrupt handlers ***/ | |
751 | ||
752 | STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception) | |
753 | ||
754 | /* | |
755 | * Machine check is different because we use a different | |
756 | * save area: PACA_EXMC instead of PACA_EXGEN. | |
757 | */ | |
758 | .align 7 | |
759 | .globl machine_check_common | |
760 | machine_check_common: | |
761 | EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) | |
762 | DISABLE_INTS | |
763 | bl .save_nvgprs | |
764 | addi r3,r1,STACK_FRAME_OVERHEAD | |
765 | bl .machine_check_exception | |
766 | b .ret_from_except | |
767 | ||
768 | STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt) | |
769 | STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception) | |
770 | STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception) | |
771 | STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception) | |
772 | STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception) | |
773 | STD_EXCEPTION_COMMON(0xf00, performance_monitor, .performance_monitor_exception) | |
774 | STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception) | |
775 | #ifdef CONFIG_ALTIVEC | |
776 | STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception) | |
777 | #else | |
778 | STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception) | |
779 | #endif | |
780 | ||
781 | /* | |
782 | * Here we have detected that the kernel stack pointer is bad. | |
783 | * R9 contains the saved CR, r13 points to the paca, | |
784 | * r10 contains the (bad) kernel stack pointer, | |
785 | * r11 and r12 contain the saved SRR0 and SRR1. | |
786 | * We switch to using an emergency stack, save the registers there, | |
787 | * and call kernel_bad_stack(), which panics. | |
788 | */ | |
789 | bad_stack: | |
790 | ld r1,PACAEMERGSP(r13) | |
791 | subi r1,r1,64+INT_FRAME_SIZE | |
792 | std r9,_CCR(r1) | |
793 | std r10,GPR1(r1) | |
794 | std r11,_NIP(r1) | |
795 | std r12,_MSR(r1) | |
b5bbeb23 PM |
796 | mfspr r11,SPRN_DAR |
797 | mfspr r12,SPRN_DSISR | |
14cf11af PM |
798 | std r11,_DAR(r1) |
799 | std r12,_DSISR(r1) | |
800 | mflr r10 | |
801 | mfctr r11 | |
802 | mfxer r12 | |
803 | std r10,_LINK(r1) | |
804 | std r11,_CTR(r1) | |
805 | std r12,_XER(r1) | |
806 | SAVE_GPR(0,r1) | |
807 | SAVE_GPR(2,r1) | |
808 | SAVE_4GPRS(3,r1) | |
809 | SAVE_2GPRS(7,r1) | |
810 | SAVE_10GPRS(12,r1) | |
811 | SAVE_10GPRS(22,r1) | |
812 | addi r11,r1,INT_FRAME_SIZE | |
813 | std r11,0(r1) | |
814 | li r12,0 | |
815 | std r12,0(r11) | |
816 | ld r2,PACATOC(r13) | |
817 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
818 | bl .kernel_bad_stack | |
819 | b 1b | |
820 | ||
821 | /* | |
822 | * Return from an exception with minimal checks. | |
823 | * The caller is assumed to have done EXCEPTION_PROLOG_COMMON. | |
824 | * If interrupts have been enabled, or anything has been | |
825 | * done that might have changed the scheduling status of | |
826 | * any task or sent any task a signal, you should use | |
827 | * ret_from_except or ret_from_except_lite instead of this. | |
828 | */ | |
40ef8cbc | 829 | .globl fast_exception_return |
14cf11af PM |
830 | fast_exception_return: |
831 | ld r12,_MSR(r1) | |
832 | ld r11,_NIP(r1) | |
833 | andi. r3,r12,MSR_RI /* check if RI is set */ | |
834 | beq- unrecov_fer | |
835 | ld r3,_CCR(r1) | |
836 | ld r4,_LINK(r1) | |
837 | ld r5,_CTR(r1) | |
838 | ld r6,_XER(r1) | |
839 | mtcr r3 | |
840 | mtlr r4 | |
841 | mtctr r5 | |
842 | mtxer r6 | |
843 | REST_GPR(0, r1) | |
844 | REST_8GPRS(2, r1) | |
845 | ||
846 | mfmsr r10 | |
847 | clrrdi r10,r10,2 /* clear RI (LE is 0 already) */ | |
848 | mtmsrd r10,1 | |
849 | ||
b5bbeb23 PM |
850 | mtspr SPRN_SRR1,r12 |
851 | mtspr SPRN_SRR0,r11 | |
14cf11af PM |
852 | REST_4GPRS(10, r1) |
853 | ld r1,GPR1(r1) | |
854 | rfid | |
855 | b . /* prevent speculative execution */ | |
856 | ||
857 | unrecov_fer: | |
858 | bl .save_nvgprs | |
859 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
860 | bl .unrecoverable_exception | |
861 | b 1b | |
862 | ||
863 | /* | |
864 | * Here r13 points to the paca, r9 contains the saved CR, | |
865 | * SRR0 and SRR1 are saved in r11 and r12, | |
866 | * r9 - r13 are saved in paca->exgen. | |
867 | */ | |
868 | .align 7 | |
869 | .globl data_access_common | |
870 | data_access_common: | |
871 | RUNLATCH_ON(r10) /* It wont fit in the 0x300 handler */ | |
b5bbeb23 | 872 | mfspr r10,SPRN_DAR |
14cf11af | 873 | std r10,PACA_EXGEN+EX_DAR(r13) |
b5bbeb23 | 874 | mfspr r10,SPRN_DSISR |
14cf11af PM |
875 | stw r10,PACA_EXGEN+EX_DSISR(r13) |
876 | EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) | |
877 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
878 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
879 | li r5,0x300 | |
880 | b .do_hash_page /* Try to handle as hpte fault */ | |
881 | ||
882 | .align 7 | |
883 | .globl instruction_access_common | |
884 | instruction_access_common: | |
885 | EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) | |
886 | ld r3,_NIP(r1) | |
887 | andis. r4,r12,0x5820 | |
888 | li r5,0x400 | |
889 | b .do_hash_page /* Try to handle as hpte fault */ | |
890 | ||
3c726f8d BH |
891 | /* |
892 | * Here is the common SLB miss user that is used when going to virtual | |
893 | * mode for SLB misses, that is currently not used | |
894 | */ | |
895 | #ifdef __DISABLED__ | |
896 | .align 7 | |
897 | .globl slb_miss_user_common | |
898 | slb_miss_user_common: | |
899 | mflr r10 | |
900 | std r3,PACA_EXGEN+EX_DAR(r13) | |
901 | stw r9,PACA_EXGEN+EX_CCR(r13) | |
902 | std r10,PACA_EXGEN+EX_LR(r13) | |
903 | std r11,PACA_EXGEN+EX_SRR0(r13) | |
904 | bl .slb_allocate_user | |
905 | ||
906 | ld r10,PACA_EXGEN+EX_LR(r13) | |
907 | ld r3,PACA_EXGEN+EX_R3(r13) | |
908 | lwz r9,PACA_EXGEN+EX_CCR(r13) | |
909 | ld r11,PACA_EXGEN+EX_SRR0(r13) | |
910 | mtlr r10 | |
911 | beq- slb_miss_fault | |
912 | ||
913 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | |
914 | beq- unrecov_user_slb | |
915 | mfmsr r10 | |
916 | ||
917 | .machine push | |
918 | .machine "power4" | |
919 | mtcrf 0x80,r9 | |
920 | .machine pop | |
921 | ||
922 | clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */ | |
923 | mtmsrd r10,1 | |
924 | ||
925 | mtspr SRR0,r11 | |
926 | mtspr SRR1,r12 | |
927 | ||
928 | ld r9,PACA_EXGEN+EX_R9(r13) | |
929 | ld r10,PACA_EXGEN+EX_R10(r13) | |
930 | ld r11,PACA_EXGEN+EX_R11(r13) | |
931 | ld r12,PACA_EXGEN+EX_R12(r13) | |
932 | ld r13,PACA_EXGEN+EX_R13(r13) | |
933 | rfid | |
934 | b . | |
935 | ||
936 | slb_miss_fault: | |
937 | EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN) | |
938 | ld r4,PACA_EXGEN+EX_DAR(r13) | |
939 | li r5,0 | |
940 | std r4,_DAR(r1) | |
941 | std r5,_DSISR(r1) | |
942 | b .handle_page_fault | |
943 | ||
944 | unrecov_user_slb: | |
945 | EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN) | |
946 | DISABLE_INTS | |
947 | bl .save_nvgprs | |
948 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
949 | bl .unrecoverable_exception | |
950 | b 1b | |
951 | ||
952 | #endif /* __DISABLED__ */ | |
953 | ||
954 | ||
955 | /* | |
956 | * r13 points to the PACA, r9 contains the saved CR, | |
957 | * r12 contain the saved SRR1, SRR0 is still ready for return | |
958 | * r3 has the faulting address | |
959 | * r9 - r13 are saved in paca->exslb. | |
960 | * r3 is saved in paca->slb_r3 | |
961 | * We assume we aren't going to take any exceptions during this procedure. | |
962 | */ | |
963 | _GLOBAL(slb_miss_realmode) | |
964 | mflr r10 | |
965 | ||
966 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | |
967 | std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ | |
968 | ||
969 | bl .slb_allocate_realmode | |
970 | ||
971 | /* All done -- return from exception. */ | |
972 | ||
973 | ld r10,PACA_EXSLB+EX_LR(r13) | |
974 | ld r3,PACA_EXSLB+EX_R3(r13) | |
975 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | |
976 | #ifdef CONFIG_PPC_ISERIES | |
977 | ld r11,PACALPPACA+LPPACASRR0(r13) /* get SRR0 value */ | |
978 | #endif /* CONFIG_PPC_ISERIES */ | |
979 | ||
980 | mtlr r10 | |
981 | ||
982 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | |
983 | beq- unrecov_slb | |
984 | ||
985 | .machine push | |
986 | .machine "power4" | |
987 | mtcrf 0x80,r9 | |
988 | mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ | |
989 | .machine pop | |
990 | ||
991 | #ifdef CONFIG_PPC_ISERIES | |
992 | mtspr SPRN_SRR0,r11 | |
993 | mtspr SPRN_SRR1,r12 | |
994 | #endif /* CONFIG_PPC_ISERIES */ | |
995 | ld r9,PACA_EXSLB+EX_R9(r13) | |
996 | ld r10,PACA_EXSLB+EX_R10(r13) | |
997 | ld r11,PACA_EXSLB+EX_R11(r13) | |
998 | ld r12,PACA_EXSLB+EX_R12(r13) | |
999 | ld r13,PACA_EXSLB+EX_R13(r13) | |
1000 | rfid | |
1001 | b . /* prevent speculative execution */ | |
1002 | ||
1003 | unrecov_slb: | |
1004 | EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) | |
1005 | DISABLE_INTS | |
1006 | bl .save_nvgprs | |
1007 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
1008 | bl .unrecoverable_exception | |
1009 | b 1b | |
1010 | ||
14cf11af PM |
1011 | .align 7 |
1012 | .globl hardware_interrupt_common | |
1013 | .globl hardware_interrupt_entry | |
1014 | hardware_interrupt_common: | |
1015 | EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN) | |
1016 | hardware_interrupt_entry: | |
1017 | DISABLE_INTS | |
1018 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1019 | bl .do_IRQ | |
1020 | b .ret_from_except_lite | |
1021 | ||
1022 | .align 7 | |
1023 | .globl alignment_common | |
1024 | alignment_common: | |
b5bbeb23 | 1025 | mfspr r10,SPRN_DAR |
14cf11af | 1026 | std r10,PACA_EXGEN+EX_DAR(r13) |
b5bbeb23 | 1027 | mfspr r10,SPRN_DSISR |
14cf11af PM |
1028 | stw r10,PACA_EXGEN+EX_DSISR(r13) |
1029 | EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) | |
1030 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
1031 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
1032 | std r3,_DAR(r1) | |
1033 | std r4,_DSISR(r1) | |
1034 | bl .save_nvgprs | |
1035 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1036 | ENABLE_INTS | |
1037 | bl .alignment_exception | |
1038 | b .ret_from_except | |
1039 | ||
1040 | .align 7 | |
1041 | .globl program_check_common | |
1042 | program_check_common: | |
1043 | EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) | |
1044 | bl .save_nvgprs | |
1045 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1046 | ENABLE_INTS | |
1047 | bl .program_check_exception | |
1048 | b .ret_from_except | |
1049 | ||
1050 | .align 7 | |
1051 | .globl fp_unavailable_common | |
1052 | fp_unavailable_common: | |
1053 | EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) | |
1054 | bne .load_up_fpu /* if from user, just load it up */ | |
1055 | bl .save_nvgprs | |
1056 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1057 | ENABLE_INTS | |
1058 | bl .kernel_fp_unavailable_exception | |
1059 | BUG_OPCODE | |
1060 | ||
14cf11af PM |
1061 | .align 7 |
1062 | .globl altivec_unavailable_common | |
1063 | altivec_unavailable_common: | |
1064 | EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) | |
1065 | #ifdef CONFIG_ALTIVEC | |
1066 | BEGIN_FTR_SECTION | |
1067 | bne .load_up_altivec /* if from user, just load it up */ | |
1068 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1069 | #endif | |
1070 | bl .save_nvgprs | |
1071 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1072 | ENABLE_INTS | |
1073 | bl .altivec_unavailable_exception | |
1074 | b .ret_from_except | |
1075 | ||
1076 | #ifdef CONFIG_ALTIVEC | |
1077 | /* | |
1078 | * load_up_altivec(unused, unused, tsk) | |
1079 | * Disable VMX for the task which had it previously, | |
1080 | * and save its vector registers in its thread_struct. | |
1081 | * Enables the VMX for use in the kernel on return. | |
1082 | * On SMP we know the VMX is free, since we give it up every | |
1083 | * switch (ie, no lazy save of the vector registers). | |
1084 | * On entry: r13 == 'current' && last_task_used_altivec != 'current' | |
1085 | */ | |
1086 | _STATIC(load_up_altivec) | |
1087 | mfmsr r5 /* grab the current MSR */ | |
1088 | oris r5,r5,MSR_VEC@h | |
1089 | mtmsrd r5 /* enable use of VMX now */ | |
1090 | isync | |
1091 | ||
1092 | /* | |
1093 | * For SMP, we don't do lazy VMX switching because it just gets too | |
1094 | * horrendously complex, especially when a task switches from one CPU | |
1095 | * to another. Instead we call giveup_altvec in switch_to. | |
1096 | * VRSAVE isn't dealt with here, that is done in the normal context | |
1097 | * switch code. Note that we could rely on vrsave value to eventually | |
1098 | * avoid saving all of the VREGs here... | |
1099 | */ | |
1100 | #ifndef CONFIG_SMP | |
1101 | ld r3,last_task_used_altivec@got(r2) | |
1102 | ld r4,0(r3) | |
1103 | cmpdi 0,r4,0 | |
1104 | beq 1f | |
1105 | /* Save VMX state to last_task_used_altivec's THREAD struct */ | |
1106 | addi r4,r4,THREAD | |
1107 | SAVE_32VRS(0,r5,r4) | |
1108 | mfvscr vr0 | |
1109 | li r10,THREAD_VSCR | |
1110 | stvx vr0,r10,r4 | |
1111 | /* Disable VMX for last_task_used_altivec */ | |
1112 | ld r5,PT_REGS(r4) | |
1113 | ld r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
1114 | lis r6,MSR_VEC@h | |
1115 | andc r4,r4,r6 | |
1116 | std r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
1117 | 1: | |
1118 | #endif /* CONFIG_SMP */ | |
1119 | /* Hack: if we get an altivec unavailable trap with VRSAVE | |
1120 | * set to all zeros, we assume this is a broken application | |
1121 | * that fails to set it properly, and thus we switch it to | |
1122 | * all 1's | |
1123 | */ | |
1124 | mfspr r4,SPRN_VRSAVE | |
1125 | cmpdi 0,r4,0 | |
1126 | bne+ 1f | |
1127 | li r4,-1 | |
1128 | mtspr SPRN_VRSAVE,r4 | |
1129 | 1: | |
1130 | /* enable use of VMX after return */ | |
1131 | ld r4,PACACURRENT(r13) | |
1132 | addi r5,r4,THREAD /* Get THREAD */ | |
1133 | oris r12,r12,MSR_VEC@h | |
1134 | std r12,_MSR(r1) | |
1135 | li r4,1 | |
1136 | li r10,THREAD_VSCR | |
1137 | stw r4,THREAD_USED_VR(r5) | |
1138 | lvx vr0,r10,r5 | |
1139 | mtvscr vr0 | |
1140 | REST_32VRS(0,r4,r5) | |
1141 | #ifndef CONFIG_SMP | |
1142 | /* Update last_task_used_math to 'current' */ | |
1143 | subi r4,r5,THREAD /* Back to 'current' */ | |
1144 | std r4,0(r3) | |
1145 | #endif /* CONFIG_SMP */ | |
1146 | /* restore registers and return */ | |
1147 | b fast_exception_return | |
1148 | #endif /* CONFIG_ALTIVEC */ | |
1149 | ||
1150 | /* | |
1151 | * Hash table stuff | |
1152 | */ | |
1153 | .align 7 | |
1154 | _GLOBAL(do_hash_page) | |
1155 | std r3,_DAR(r1) | |
1156 | std r4,_DSISR(r1) | |
1157 | ||
1158 | andis. r0,r4,0xa450 /* weird error? */ | |
1159 | bne- .handle_page_fault /* if not, try to insert a HPTE */ | |
1160 | BEGIN_FTR_SECTION | |
1161 | andis. r0,r4,0x0020 /* Is it a segment table fault? */ | |
1162 | bne- .do_ste_alloc /* If so handle it */ | |
1163 | END_FTR_SECTION_IFCLR(CPU_FTR_SLB) | |
1164 | ||
1165 | /* | |
1166 | * We need to set the _PAGE_USER bit if MSR_PR is set or if we are | |
1167 | * accessing a userspace segment (even from the kernel). We assume | |
1168 | * kernel addresses always have the high bit set. | |
1169 | */ | |
1170 | rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */ | |
1171 | rotldi r0,r3,15 /* Move high bit into MSR_PR posn */ | |
1172 | orc r0,r12,r0 /* MSR_PR | ~high_bit */ | |
1173 | rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */ | |
1174 | ori r4,r4,1 /* add _PAGE_PRESENT */ | |
1175 | rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */ | |
1176 | ||
1177 | /* | |
1178 | * On iSeries, we soft-disable interrupts here, then | |
1179 | * hard-enable interrupts so that the hash_page code can spin on | |
1180 | * the hash_table_lock without problems on a shared processor. | |
1181 | */ | |
1182 | DISABLE_INTS | |
1183 | ||
1184 | /* | |
1185 | * r3 contains the faulting address | |
1186 | * r4 contains the required access permissions | |
1187 | * r5 contains the trap number | |
1188 | * | |
1189 | * at return r3 = 0 for success | |
1190 | */ | |
1191 | bl .hash_page /* build HPTE if possible */ | |
1192 | cmpdi r3,0 /* see if hash_page succeeded */ | |
1193 | ||
1194 | #ifdef DO_SOFT_DISABLE | |
1195 | /* | |
1196 | * If we had interrupts soft-enabled at the point where the | |
1197 | * DSI/ISI occurred, and an interrupt came in during hash_page, | |
1198 | * handle it now. | |
1199 | * We jump to ret_from_except_lite rather than fast_exception_return | |
1200 | * because ret_from_except_lite will check for and handle pending | |
1201 | * interrupts if necessary. | |
1202 | */ | |
1203 | beq .ret_from_except_lite | |
1204 | /* For a hash failure, we don't bother re-enabling interrupts */ | |
1205 | ble- 12f | |
1206 | ||
1207 | /* | |
1208 | * hash_page couldn't handle it, set soft interrupt enable back | |
1209 | * to what it was before the trap. Note that .local_irq_restore | |
1210 | * handles any interrupts pending at this point. | |
1211 | */ | |
1212 | ld r3,SOFTE(r1) | |
1213 | bl .local_irq_restore | |
1214 | b 11f | |
1215 | #else | |
1216 | beq fast_exception_return /* Return from exception on success */ | |
1217 | ble- 12f /* Failure return from hash_page */ | |
1218 | ||
1219 | /* fall through */ | |
1220 | #endif | |
1221 | ||
1222 | /* Here we have a page fault that hash_page can't handle. */ | |
1223 | _GLOBAL(handle_page_fault) | |
1224 | ENABLE_INTS | |
1225 | 11: ld r4,_DAR(r1) | |
1226 | ld r5,_DSISR(r1) | |
1227 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1228 | bl .do_page_fault | |
1229 | cmpdi r3,0 | |
1230 | beq+ .ret_from_except_lite | |
1231 | bl .save_nvgprs | |
1232 | mr r5,r3 | |
1233 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1234 | lwz r4,_DAR(r1) | |
1235 | bl .bad_page_fault | |
1236 | b .ret_from_except | |
1237 | ||
1238 | /* We have a page fault that hash_page could handle but HV refused | |
1239 | * the PTE insertion | |
1240 | */ | |
1241 | 12: bl .save_nvgprs | |
1242 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1243 | lwz r4,_DAR(r1) | |
1244 | bl .low_hash_fault | |
1245 | b .ret_from_except | |
1246 | ||
1247 | /* here we have a segment miss */ | |
1248 | _GLOBAL(do_ste_alloc) | |
1249 | bl .ste_allocate /* try to insert stab entry */ | |
1250 | cmpdi r3,0 | |
1251 | beq+ fast_exception_return | |
1252 | b .handle_page_fault | |
1253 | ||
1254 | /* | |
1255 | * r13 points to the PACA, r9 contains the saved CR, | |
1256 | * r11 and r12 contain the saved SRR0 and SRR1. | |
1257 | * r9 - r13 are saved in paca->exslb. | |
1258 | * We assume we aren't going to take any exceptions during this procedure. | |
1259 | * We assume (DAR >> 60) == 0xc. | |
1260 | */ | |
1261 | .align 7 | |
1262 | _GLOBAL(do_stab_bolted) | |
1263 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | |
1264 | std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */ | |
1265 | ||
1266 | /* Hash to the primary group */ | |
1267 | ld r10,PACASTABVIRT(r13) | |
b5bbeb23 | 1268 | mfspr r11,SPRN_DAR |
14cf11af PM |
1269 | srdi r11,r11,28 |
1270 | rldimi r10,r11,7,52 /* r10 = first ste of the group */ | |
1271 | ||
1272 | /* Calculate VSID */ | |
1273 | /* This is a kernel address, so protovsid = ESID */ | |
1274 | ASM_VSID_SCRAMBLE(r11, r9) | |
1275 | rldic r9,r11,12,16 /* r9 = vsid << 12 */ | |
1276 | ||
1277 | /* Search the primary group for a free entry */ | |
1278 | 1: ld r11,0(r10) /* Test valid bit of the current ste */ | |
1279 | andi. r11,r11,0x80 | |
1280 | beq 2f | |
1281 | addi r10,r10,16 | |
1282 | andi. r11,r10,0x70 | |
1283 | bne 1b | |
1284 | ||
1285 | /* Stick for only searching the primary group for now. */ | |
1286 | /* At least for now, we use a very simple random castout scheme */ | |
1287 | /* Use the TB as a random number ; OR in 1 to avoid entry 0 */ | |
1288 | mftb r11 | |
1289 | rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */ | |
1290 | ori r11,r11,0x10 | |
1291 | ||
1292 | /* r10 currently points to an ste one past the group of interest */ | |
1293 | /* make it point to the randomly selected entry */ | |
1294 | subi r10,r10,128 | |
1295 | or r10,r10,r11 /* r10 is the entry to invalidate */ | |
1296 | ||
1297 | isync /* mark the entry invalid */ | |
1298 | ld r11,0(r10) | |
1299 | rldicl r11,r11,56,1 /* clear the valid bit */ | |
1300 | rotldi r11,r11,8 | |
1301 | std r11,0(r10) | |
1302 | sync | |
1303 | ||
1304 | clrrdi r11,r11,28 /* Get the esid part of the ste */ | |
1305 | slbie r11 | |
1306 | ||
1307 | 2: std r9,8(r10) /* Store the vsid part of the ste */ | |
1308 | eieio | |
1309 | ||
b5bbeb23 | 1310 | mfspr r11,SPRN_DAR /* Get the new esid */ |
14cf11af PM |
1311 | clrrdi r11,r11,28 /* Permits a full 32b of ESID */ |
1312 | ori r11,r11,0x90 /* Turn on valid and kp */ | |
1313 | std r11,0(r10) /* Put new entry back into the stab */ | |
1314 | ||
1315 | sync | |
1316 | ||
1317 | /* All done -- return from exception. */ | |
1318 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | |
1319 | ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */ | |
1320 | ||
1321 | andi. r10,r12,MSR_RI | |
1322 | beq- unrecov_slb | |
1323 | ||
1324 | mtcrf 0x80,r9 /* restore CR */ | |
1325 | ||
1326 | mfmsr r10 | |
1327 | clrrdi r10,r10,2 | |
1328 | mtmsrd r10,1 | |
1329 | ||
b5bbeb23 PM |
1330 | mtspr SPRN_SRR0,r11 |
1331 | mtspr SPRN_SRR1,r12 | |
14cf11af PM |
1332 | ld r9,PACA_EXSLB+EX_R9(r13) |
1333 | ld r10,PACA_EXSLB+EX_R10(r13) | |
1334 | ld r11,PACA_EXSLB+EX_R11(r13) | |
1335 | ld r12,PACA_EXSLB+EX_R12(r13) | |
1336 | ld r13,PACA_EXSLB+EX_R13(r13) | |
1337 | rfid | |
1338 | b . /* prevent speculative execution */ | |
1339 | ||
14cf11af PM |
1340 | /* |
1341 | * Space for CPU0's segment table. | |
1342 | * | |
1343 | * On iSeries, the hypervisor must fill in at least one entry before | |
1344 | * we get control (with relocate on). The address is give to the hv | |
ee400b63 | 1345 | * as a page number (see xLparMap in lpardata.c), so this must be at a |
14cf11af PM |
1346 | * fixed address (the linker can't compute (u64)&initial_stab >> |
1347 | * PAGE_SHIFT). | |
1348 | */ | |
1349 | . = STAB0_PHYS_ADDR /* 0x6000 */ | |
1350 | .globl initial_stab | |
1351 | initial_stab: | |
1352 | .space 4096 | |
1353 | ||
1354 | /* | |
1355 | * Data area reserved for FWNMI option. | |
1356 | * This address (0x7000) is fixed by the RPA. | |
1357 | */ | |
1358 | .= 0x7000 | |
1359 | .globl fwnmi_data_area | |
1360 | fwnmi_data_area: | |
1361 | ||
1362 | /* iSeries does not use the FWNMI stuff, so it is safe to put | |
1363 | * this here, even if we later allow kernels that will boot on | |
1364 | * both pSeries and iSeries */ | |
1365 | #ifdef CONFIG_PPC_ISERIES | |
1366 | . = LPARMAP_PHYS | |
1367 | #include "lparmap.s" | |
1368 | /* | |
1369 | * This ".text" is here for old compilers that generate a trailing | |
1370 | * .note section when compiling .c files to .s | |
1371 | */ | |
1372 | .text | |
1373 | #endif /* CONFIG_PPC_ISERIES */ | |
1374 | ||
1375 | . = 0x8000 | |
1376 | ||
1377 | /* | |
1378 | * On pSeries, secondary processors spin in the following code. | |
1379 | * At entry, r3 = this processor's number (physical cpu id) | |
1380 | */ | |
1381 | _GLOBAL(pSeries_secondary_smp_init) | |
1382 | mr r24,r3 | |
1383 | ||
1384 | /* turn on 64-bit mode */ | |
1385 | bl .enable_64b_mode | |
1386 | isync | |
1387 | ||
1388 | /* Copy some CPU settings from CPU 0 */ | |
1389 | bl .__restore_cpu_setup | |
1390 | ||
1391 | /* Set up a paca value for this processor. Since we have the | |
1392 | * physical cpu id in r24, we need to search the pacas to find | |
1393 | * which logical id maps to our physical one. | |
1394 | */ | |
1395 | LOADADDR(r13, paca) /* Get base vaddr of paca array */ | |
1396 | li r5,0 /* logical cpu id */ | |
1397 | 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ | |
1398 | cmpw r6,r24 /* Compare to our id */ | |
1399 | beq 2f | |
1400 | addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */ | |
1401 | addi r5,r5,1 | |
1402 | cmpwi r5,NR_CPUS | |
1403 | blt 1b | |
1404 | ||
1405 | mr r3,r24 /* not found, copy phys to r3 */ | |
1406 | b .kexec_wait /* next kernel might do better */ | |
1407 | ||
b5bbeb23 | 1408 | 2: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */ |
14cf11af PM |
1409 | /* From now on, r24 is expected to be logical cpuid */ |
1410 | mr r24,r5 | |
1411 | 3: HMT_LOW | |
1412 | lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ | |
1413 | /* start. */ | |
1414 | sync | |
1415 | ||
1416 | /* Create a temp kernel stack for use before relocation is on. */ | |
1417 | ld r1,PACAEMERGSP(r13) | |
1418 | subi r1,r1,STACK_FRAME_OVERHEAD | |
1419 | ||
1420 | cmpwi 0,r23,0 | |
1421 | #ifdef CONFIG_SMP | |
1422 | bne .__secondary_start | |
1423 | #endif | |
1424 | b 3b /* Loop until told to go */ | |
1425 | ||
1426 | #ifdef CONFIG_PPC_ISERIES | |
1427 | _STATIC(__start_initialization_iSeries) | |
1428 | /* Clear out the BSS */ | |
1429 | LOADADDR(r11,__bss_stop) | |
1430 | LOADADDR(r8,__bss_start) | |
1431 | sub r11,r11,r8 /* bss size */ | |
1432 | addi r11,r11,7 /* round up to an even double word */ | |
1433 | rldicl. r11,r11,61,3 /* shift right by 3 */ | |
1434 | beq 4f | |
1435 | addi r8,r8,-8 | |
1436 | li r0,0 | |
1437 | mtctr r11 /* zero this many doublewords */ | |
1438 | 3: stdu r0,8(r8) | |
1439 | bdnz 3b | |
1440 | 4: | |
1441 | LOADADDR(r1,init_thread_union) | |
1442 | addi r1,r1,THREAD_SIZE | |
1443 | li r0,0 | |
1444 | stdu r0,-STACK_FRAME_OVERHEAD(r1) | |
1445 | ||
1446 | LOADADDR(r3,cpu_specs) | |
1447 | LOADADDR(r4,cur_cpu_spec) | |
1448 | li r5,0 | |
1449 | bl .identify_cpu | |
1450 | ||
1451 | LOADADDR(r2,__toc_start) | |
1452 | addi r2,r2,0x4000 | |
1453 | addi r2,r2,0x4000 | |
1454 | ||
1455 | bl .iSeries_early_setup | |
ee400b63 | 1456 | bl .early_setup |
14cf11af PM |
1457 | |
1458 | /* relocation is on at this point */ | |
1459 | ||
1460 | b .start_here_common | |
1461 | #endif /* CONFIG_PPC_ISERIES */ | |
1462 | ||
1463 | #ifdef CONFIG_PPC_MULTIPLATFORM | |
1464 | ||
1465 | _STATIC(__mmu_off) | |
1466 | mfmsr r3 | |
1467 | andi. r0,r3,MSR_IR|MSR_DR | |
1468 | beqlr | |
1469 | andc r3,r3,r0 | |
1470 | mtspr SPRN_SRR0,r4 | |
1471 | mtspr SPRN_SRR1,r3 | |
1472 | sync | |
1473 | rfid | |
1474 | b . /* prevent speculative execution */ | |
1475 | ||
1476 | ||
1477 | /* | |
1478 | * Here is our main kernel entry point. We support currently 2 kind of entries | |
1479 | * depending on the value of r5. | |
1480 | * | |
1481 | * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content | |
1482 | * in r3...r7 | |
1483 | * | |
1484 | * r5 == NULL -> kexec style entry. r3 is a physical pointer to the | |
1485 | * DT block, r4 is a physical pointer to the kernel itself | |
1486 | * | |
1487 | */ | |
1488 | _GLOBAL(__start_initialization_multiplatform) | |
1489 | /* | |
1490 | * Are we booted from a PROM Of-type client-interface ? | |
1491 | */ | |
1492 | cmpldi cr0,r5,0 | |
1493 | bne .__boot_from_prom /* yes -> prom */ | |
1494 | ||
1495 | /* Save parameters */ | |
1496 | mr r31,r3 | |
1497 | mr r30,r4 | |
1498 | ||
1499 | /* Make sure we are running in 64 bits mode */ | |
1500 | bl .enable_64b_mode | |
1501 | ||
1502 | /* Setup some critical 970 SPRs before switching MMU off */ | |
1503 | bl .__970_cpu_preinit | |
1504 | ||
1505 | /* cpu # */ | |
1506 | li r24,0 | |
1507 | ||
1508 | /* Switch off MMU if not already */ | |
1509 | LOADADDR(r4, .__after_prom_start - KERNELBASE) | |
1510 | add r4,r4,r30 | |
1511 | bl .__mmu_off | |
1512 | b .__after_prom_start | |
1513 | ||
1514 | _STATIC(__boot_from_prom) | |
1515 | /* Save parameters */ | |
1516 | mr r31,r3 | |
1517 | mr r30,r4 | |
1518 | mr r29,r5 | |
1519 | mr r28,r6 | |
1520 | mr r27,r7 | |
1521 | ||
1522 | /* Make sure we are running in 64 bits mode */ | |
1523 | bl .enable_64b_mode | |
1524 | ||
1525 | /* put a relocation offset into r3 */ | |
1526 | bl .reloc_offset | |
1527 | ||
1528 | LOADADDR(r2,__toc_start) | |
1529 | addi r2,r2,0x4000 | |
1530 | addi r2,r2,0x4000 | |
1531 | ||
1532 | /* Relocate the TOC from a virt addr to a real addr */ | |
5a408329 | 1533 | add r2,r2,r3 |
14cf11af PM |
1534 | |
1535 | /* Restore parameters */ | |
1536 | mr r3,r31 | |
1537 | mr r4,r30 | |
1538 | mr r5,r29 | |
1539 | mr r6,r28 | |
1540 | mr r7,r27 | |
1541 | ||
1542 | /* Do all of the interaction with OF client interface */ | |
1543 | bl .prom_init | |
1544 | /* We never return */ | |
1545 | trap | |
1546 | ||
1547 | /* | |
1548 | * At this point, r3 contains the physical address we are running at, | |
1549 | * returned by prom_init() | |
1550 | */ | |
1551 | _STATIC(__after_prom_start) | |
1552 | ||
1553 | /* | |
1554 | * We need to run with __start at physical address 0. | |
1555 | * This will leave some code in the first 256B of | |
1556 | * real memory, which are reserved for software use. | |
1557 | * The remainder of the first page is loaded with the fixed | |
1558 | * interrupt vectors. The next two pages are filled with | |
1559 | * unknown exception placeholders. | |
1560 | * | |
1561 | * Note: This process overwrites the OF exception vectors. | |
1562 | * r26 == relocation offset | |
1563 | * r27 == KERNELBASE | |
1564 | */ | |
1565 | bl .reloc_offset | |
1566 | mr r26,r3 | |
1567 | SET_REG_TO_CONST(r27,KERNELBASE) | |
1568 | ||
1569 | li r3,0 /* target addr */ | |
1570 | ||
1571 | // XXX FIXME: Use phys returned by OF (r30) | |
5a408329 | 1572 | add r4,r27,r26 /* source addr */ |
14cf11af PM |
1573 | /* current address of _start */ |
1574 | /* i.e. where we are running */ | |
1575 | /* the source addr */ | |
1576 | ||
1577 | LOADADDR(r5,copy_to_here) /* # bytes of memory to copy */ | |
1578 | sub r5,r5,r27 | |
1579 | ||
1580 | li r6,0x100 /* Start offset, the first 0x100 */ | |
1581 | /* bytes were copied earlier. */ | |
1582 | ||
1583 | bl .copy_and_flush /* copy the first n bytes */ | |
1584 | /* this includes the code being */ | |
1585 | /* executed here. */ | |
1586 | ||
1587 | LOADADDR(r0, 4f) /* Jump to the copy of this code */ | |
1588 | mtctr r0 /* that we just made/relocated */ | |
1589 | bctr | |
1590 | ||
1591 | 4: LOADADDR(r5,klimit) | |
5a408329 | 1592 | add r5,r5,r26 |
14cf11af PM |
1593 | ld r5,0(r5) /* get the value of klimit */ |
1594 | sub r5,r5,r27 | |
1595 | bl .copy_and_flush /* copy the rest */ | |
1596 | b .start_here_multiplatform | |
1597 | ||
1598 | #endif /* CONFIG_PPC_MULTIPLATFORM */ | |
1599 | ||
1600 | /* | |
1601 | * Copy routine used to copy the kernel to start at physical address 0 | |
1602 | * and flush and invalidate the caches as needed. | |
1603 | * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset | |
1604 | * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. | |
1605 | * | |
1606 | * Note: this routine *only* clobbers r0, r6 and lr | |
1607 | */ | |
1608 | _GLOBAL(copy_and_flush) | |
1609 | addi r5,r5,-8 | |
1610 | addi r6,r6,-8 | |
1611 | 4: li r0,16 /* Use the least common */ | |
1612 | /* denominator cache line */ | |
1613 | /* size. This results in */ | |
1614 | /* extra cache line flushes */ | |
1615 | /* but operation is correct. */ | |
1616 | /* Can't get cache line size */ | |
1617 | /* from NACA as it is being */ | |
1618 | /* moved too. */ | |
1619 | ||
1620 | mtctr r0 /* put # words/line in ctr */ | |
1621 | 3: addi r6,r6,8 /* copy a cache line */ | |
1622 | ldx r0,r6,r4 | |
1623 | stdx r0,r6,r3 | |
1624 | bdnz 3b | |
1625 | dcbst r6,r3 /* write it to memory */ | |
1626 | sync | |
1627 | icbi r6,r3 /* flush the icache line */ | |
1628 | cmpld 0,r6,r5 | |
1629 | blt 4b | |
1630 | sync | |
1631 | addi r5,r5,8 | |
1632 | addi r6,r6,8 | |
1633 | blr | |
1634 | ||
1635 | .align 8 | |
1636 | copy_to_here: | |
1637 | ||
1638 | #ifdef CONFIG_SMP | |
1639 | #ifdef CONFIG_PPC_PMAC | |
1640 | /* | |
1641 | * On PowerMac, secondary processors starts from the reset vector, which | |
1642 | * is temporarily turned into a call to one of the functions below. | |
1643 | */ | |
1644 | .section ".text"; | |
1645 | .align 2 ; | |
1646 | ||
35499c01 PM |
1647 | .globl __secondary_start_pmac_0 |
1648 | __secondary_start_pmac_0: | |
1649 | /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ | |
1650 | li r24,0 | |
1651 | b 1f | |
1652 | li r24,1 | |
1653 | b 1f | |
1654 | li r24,2 | |
1655 | b 1f | |
1656 | li r24,3 | |
1657 | 1: | |
14cf11af PM |
1658 | |
1659 | _GLOBAL(pmac_secondary_start) | |
1660 | /* turn on 64-bit mode */ | |
1661 | bl .enable_64b_mode | |
1662 | isync | |
1663 | ||
1664 | /* Copy some CPU settings from CPU 0 */ | |
1665 | bl .__restore_cpu_setup | |
1666 | ||
1667 | /* pSeries do that early though I don't think we really need it */ | |
1668 | mfmsr r3 | |
1669 | ori r3,r3,MSR_RI | |
1670 | mtmsrd r3 /* RI on */ | |
1671 | ||
1672 | /* Set up a paca value for this processor. */ | |
1673 | LOADADDR(r4, paca) /* Get base vaddr of paca array */ | |
1674 | mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ | |
1675 | add r13,r13,r4 /* for this processor. */ | |
b5bbeb23 | 1676 | mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */ |
14cf11af PM |
1677 | |
1678 | /* Create a temp kernel stack for use before relocation is on. */ | |
1679 | ld r1,PACAEMERGSP(r13) | |
1680 | subi r1,r1,STACK_FRAME_OVERHEAD | |
1681 | ||
1682 | b .__secondary_start | |
1683 | ||
1684 | #endif /* CONFIG_PPC_PMAC */ | |
1685 | ||
1686 | /* | |
1687 | * This function is called after the master CPU has released the | |
1688 | * secondary processors. The execution environment is relocation off. | |
1689 | * The paca for this processor has the following fields initialized at | |
1690 | * this point: | |
1691 | * 1. Processor number | |
1692 | * 2. Segment table pointer (virtual address) | |
1693 | * On entry the following are set: | |
1694 | * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries | |
1695 | * r24 = cpu# (in Linux terms) | |
1696 | * r13 = paca virtual address | |
1697 | * SPRG3 = paca virtual address | |
1698 | */ | |
1699 | _GLOBAL(__secondary_start) | |
799d6046 PM |
1700 | /* Set thread priority to MEDIUM */ |
1701 | HMT_MEDIUM | |
14cf11af | 1702 | |
799d6046 | 1703 | /* Load TOC */ |
14cf11af | 1704 | ld r2,PACATOC(r13) |
799d6046 PM |
1705 | |
1706 | /* Do early setup for that CPU (stab, slb, hash table pointer) */ | |
1707 | bl .early_setup_secondary | |
14cf11af PM |
1708 | |
1709 | /* Initialize the kernel stack. Just a repeat for iSeries. */ | |
1710 | LOADADDR(r3,current_set) | |
1711 | sldi r28,r24,3 /* get current_set[cpu#] */ | |
1712 | ldx r1,r3,r28 | |
1713 | addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD | |
1714 | std r1,PACAKSAVE(r13) | |
1715 | ||
799d6046 | 1716 | /* Clear backchain so we get nice backtraces */ |
14cf11af PM |
1717 | li r7,0 |
1718 | mtlr r7 | |
1719 | ||
1720 | /* enable MMU and jump to start_secondary */ | |
1721 | LOADADDR(r3,.start_secondary_prolog) | |
1722 | SET_REG_TO_CONST(r4, MSR_KERNEL) | |
1723 | #ifdef DO_SOFT_DISABLE | |
1724 | ori r4,r4,MSR_EE | |
1725 | #endif | |
b5bbeb23 PM |
1726 | mtspr SPRN_SRR0,r3 |
1727 | mtspr SPRN_SRR1,r4 | |
14cf11af PM |
1728 | rfid |
1729 | b . /* prevent speculative execution */ | |
1730 | ||
1731 | /* | |
1732 | * Running with relocation on at this point. All we want to do is | |
1733 | * zero the stack back-chain pointer before going into C code. | |
1734 | */ | |
1735 | _GLOBAL(start_secondary_prolog) | |
1736 | li r3,0 | |
1737 | std r3,0(r1) /* Zero the stack frame pointer */ | |
1738 | bl .start_secondary | |
799d6046 | 1739 | b . |
14cf11af PM |
1740 | #endif |
1741 | ||
1742 | /* | |
1743 | * This subroutine clobbers r11 and r12 | |
1744 | */ | |
1745 | _GLOBAL(enable_64b_mode) | |
1746 | mfmsr r11 /* grab the current MSR */ | |
1747 | li r12,1 | |
1748 | rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG) | |
1749 | or r11,r11,r12 | |
1750 | li r12,1 | |
1751 | rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG) | |
1752 | or r11,r11,r12 | |
1753 | mtmsrd r11 | |
1754 | isync | |
1755 | blr | |
1756 | ||
1757 | #ifdef CONFIG_PPC_MULTIPLATFORM | |
1758 | /* | |
1759 | * This is where the main kernel code starts. | |
1760 | */ | |
1761 | _STATIC(start_here_multiplatform) | |
1762 | /* get a new offset, now that the kernel has moved. */ | |
1763 | bl .reloc_offset | |
1764 | mr r26,r3 | |
1765 | ||
1766 | /* Clear out the BSS. It may have been done in prom_init, | |
1767 | * already but that's irrelevant since prom_init will soon | |
1768 | * be detached from the kernel completely. Besides, we need | |
1769 | * to clear it now for kexec-style entry. | |
1770 | */ | |
1771 | LOADADDR(r11,__bss_stop) | |
1772 | LOADADDR(r8,__bss_start) | |
1773 | sub r11,r11,r8 /* bss size */ | |
1774 | addi r11,r11,7 /* round up to an even double word */ | |
1775 | rldicl. r11,r11,61,3 /* shift right by 3 */ | |
1776 | beq 4f | |
1777 | addi r8,r8,-8 | |
1778 | li r0,0 | |
1779 | mtctr r11 /* zero this many doublewords */ | |
1780 | 3: stdu r0,8(r8) | |
1781 | bdnz 3b | |
1782 | 4: | |
1783 | ||
1784 | mfmsr r6 | |
1785 | ori r6,r6,MSR_RI | |
1786 | mtmsrd r6 /* RI on */ | |
1787 | ||
1788 | #ifdef CONFIG_HMT | |
1789 | /* Start up the second thread on cpu 0 */ | |
b5bbeb23 | 1790 | mfspr r3,SPRN_PVR |
14cf11af PM |
1791 | srwi r3,r3,16 |
1792 | cmpwi r3,0x34 /* Pulsar */ | |
1793 | beq 90f | |
1794 | cmpwi r3,0x36 /* Icestar */ | |
1795 | beq 90f | |
1796 | cmpwi r3,0x37 /* SStar */ | |
1797 | beq 90f | |
1798 | b 91f /* HMT not supported */ | |
1799 | 90: li r3,0 | |
1800 | bl .hmt_start_secondary | |
1801 | 91: | |
1802 | #endif | |
1803 | ||
1804 | /* The following gets the stack and TOC set up with the regs */ | |
1805 | /* pointing to the real addr of the kernel stack. This is */ | |
1806 | /* all done to support the C function call below which sets */ | |
1807 | /* up the htab. This is done because we have relocated the */ | |
1808 | /* kernel but are still running in real mode. */ | |
1809 | ||
1810 | LOADADDR(r3,init_thread_union) | |
5a408329 | 1811 | add r3,r3,r26 |
14cf11af PM |
1812 | |
1813 | /* set up a stack pointer (physical address) */ | |
1814 | addi r1,r3,THREAD_SIZE | |
1815 | li r0,0 | |
1816 | stdu r0,-STACK_FRAME_OVERHEAD(r1) | |
1817 | ||
1818 | /* set up the TOC (physical address) */ | |
1819 | LOADADDR(r2,__toc_start) | |
1820 | addi r2,r2,0x4000 | |
1821 | addi r2,r2,0x4000 | |
5a408329 | 1822 | add r2,r2,r26 |
14cf11af PM |
1823 | |
1824 | LOADADDR(r3,cpu_specs) | |
5a408329 | 1825 | add r3,r3,r26 |
14cf11af | 1826 | LOADADDR(r4,cur_cpu_spec) |
5a408329 | 1827 | add r4,r4,r26 |
14cf11af PM |
1828 | mr r5,r26 |
1829 | bl .identify_cpu | |
1830 | ||
1831 | /* Save some low level config HIDs of CPU0 to be copied to | |
1832 | * other CPUs later on, or used for suspend/resume | |
1833 | */ | |
1834 | bl .__save_cpu_setup | |
1835 | sync | |
1836 | ||
1837 | /* Setup a valid physical PACA pointer in SPRG3 for early_setup | |
1838 | * note that boot_cpuid can always be 0 nowadays since there is | |
1839 | * nowhere it can be initialized differently before we reach this | |
1840 | * code | |
1841 | */ | |
1842 | LOADADDR(r27, boot_cpuid) | |
5a408329 | 1843 | add r27,r27,r26 |
14cf11af PM |
1844 | lwz r27,0(r27) |
1845 | ||
1846 | LOADADDR(r24, paca) /* Get base vaddr of paca array */ | |
1847 | mulli r13,r27,PACA_SIZE /* Calculate vaddr of right paca */ | |
1848 | add r13,r13,r24 /* for this processor. */ | |
5a408329 | 1849 | add r13,r13,r26 /* convert to physical addr */ |
b5bbeb23 | 1850 | mtspr SPRN_SPRG3,r13 /* PPPBBB: Temp... -Peter */ |
14cf11af PM |
1851 | |
1852 | /* Do very early kernel initializations, including initial hash table, | |
1853 | * stab and slb setup before we turn on relocation. */ | |
1854 | ||
1855 | /* Restore parameters passed from prom_init/kexec */ | |
1856 | mr r3,r31 | |
1857 | bl .early_setup | |
1858 | ||
14cf11af PM |
1859 | LOADADDR(r3,.start_here_common) |
1860 | SET_REG_TO_CONST(r4, MSR_KERNEL) | |
b5bbeb23 PM |
1861 | mtspr SPRN_SRR0,r3 |
1862 | mtspr SPRN_SRR1,r4 | |
14cf11af PM |
1863 | rfid |
1864 | b . /* prevent speculative execution */ | |
1865 | #endif /* CONFIG_PPC_MULTIPLATFORM */ | |
1866 | ||
1867 | /* This is where all platforms converge execution */ | |
1868 | _STATIC(start_here_common) | |
1869 | /* relocation is on at this point */ | |
1870 | ||
1871 | /* The following code sets up the SP and TOC now that we are */ | |
1872 | /* running with translation enabled. */ | |
1873 | ||
1874 | LOADADDR(r3,init_thread_union) | |
1875 | ||
1876 | /* set up the stack */ | |
1877 | addi r1,r3,THREAD_SIZE | |
1878 | li r0,0 | |
1879 | stdu r0,-STACK_FRAME_OVERHEAD(r1) | |
1880 | ||
1881 | /* Apply the CPUs-specific fixups (nop out sections not relevant | |
1882 | * to this CPU | |
1883 | */ | |
1884 | li r3,0 | |
1885 | bl .do_cpu_ftr_fixups | |
1886 | ||
1887 | LOADADDR(r26, boot_cpuid) | |
1888 | lwz r26,0(r26) | |
1889 | ||
1890 | LOADADDR(r24, paca) /* Get base vaddr of paca array */ | |
1891 | mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */ | |
1892 | add r13,r13,r24 /* for this processor. */ | |
b5bbeb23 | 1893 | mtspr SPRN_SPRG3,r13 |
14cf11af PM |
1894 | |
1895 | /* ptr to current */ | |
1896 | LOADADDR(r4,init_task) | |
1897 | std r4,PACACURRENT(r13) | |
1898 | ||
1899 | /* Load the TOC */ | |
1900 | ld r2,PACATOC(r13) | |
1901 | std r1,PACAKSAVE(r13) | |
1902 | ||
1903 | bl .setup_system | |
1904 | ||
1905 | /* Load up the kernel context */ | |
1906 | 5: | |
1907 | #ifdef DO_SOFT_DISABLE | |
1908 | li r5,0 | |
1909 | stb r5,PACAPROCENABLED(r13) /* Soft Disabled */ | |
1910 | mfmsr r5 | |
1911 | ori r5,r5,MSR_EE /* Hard Enabled */ | |
1912 | mtmsrd r5 | |
1913 | #endif | |
1914 | ||
1915 | bl .start_kernel | |
1916 | ||
1917 | _GLOBAL(hmt_init) | |
1918 | #ifdef CONFIG_HMT | |
1919 | LOADADDR(r5, hmt_thread_data) | |
b5bbeb23 | 1920 | mfspr r7,SPRN_PVR |
14cf11af PM |
1921 | srwi r7,r7,16 |
1922 | cmpwi r7,0x34 /* Pulsar */ | |
1923 | beq 90f | |
1924 | cmpwi r7,0x36 /* Icestar */ | |
1925 | beq 91f | |
1926 | cmpwi r7,0x37 /* SStar */ | |
1927 | beq 91f | |
1928 | b 101f | |
b5bbeb23 | 1929 | 90: mfspr r6,SPRN_PIR |
14cf11af PM |
1930 | andi. r6,r6,0x1f |
1931 | b 92f | |
b5bbeb23 | 1932 | 91: mfspr r6,SPRN_PIR |
14cf11af PM |
1933 | andi. r6,r6,0x3ff |
1934 | 92: sldi r4,r24,3 | |
1935 | stwx r6,r5,r4 | |
1936 | bl .hmt_start_secondary | |
1937 | b 101f | |
1938 | ||
1939 | __hmt_secondary_hold: | |
1940 | LOADADDR(r5, hmt_thread_data) | |
1941 | clrldi r5,r5,4 | |
1942 | li r7,0 | |
b5bbeb23 PM |
1943 | mfspr r6,SPRN_PIR |
1944 | mfspr r8,SPRN_PVR | |
14cf11af PM |
1945 | srwi r8,r8,16 |
1946 | cmpwi r8,0x34 | |
1947 | bne 93f | |
1948 | andi. r6,r6,0x1f | |
1949 | b 103f | |
1950 | 93: andi. r6,r6,0x3f | |
1951 | ||
1952 | 103: lwzx r8,r5,r7 | |
1953 | cmpw r8,r6 | |
1954 | beq 104f | |
1955 | addi r7,r7,8 | |
1956 | b 103b | |
1957 | ||
1958 | 104: addi r7,r7,4 | |
1959 | lwzx r9,r5,r7 | |
1960 | mr r24,r9 | |
1961 | 101: | |
1962 | #endif | |
1963 | mr r3,r24 | |
1964 | b .pSeries_secondary_smp_init | |
1965 | ||
1966 | #ifdef CONFIG_HMT | |
1967 | _GLOBAL(hmt_start_secondary) | |
1968 | LOADADDR(r4,__hmt_secondary_hold) | |
1969 | clrldi r4,r4,4 | |
b5bbeb23 PM |
1970 | mtspr SPRN_NIADORM, r4 |
1971 | mfspr r4, SPRN_MSRDORM | |
14cf11af PM |
1972 | li r5, -65 |
1973 | and r4, r4, r5 | |
b5bbeb23 | 1974 | mtspr SPRN_MSRDORM, r4 |
14cf11af PM |
1975 | lis r4,0xffef |
1976 | ori r4,r4,0x7403 | |
b5bbeb23 | 1977 | mtspr SPRN_TSC, r4 |
14cf11af | 1978 | li r4,0x1f4 |
b5bbeb23 PM |
1979 | mtspr SPRN_TST, r4 |
1980 | mfspr r4, SPRN_HID0 | |
14cf11af | 1981 | ori r4, r4, 0x1 |
b5bbeb23 | 1982 | mtspr SPRN_HID0, r4 |
14cf11af PM |
1983 | mfspr r4, SPRN_CTRLF |
1984 | oris r4, r4, 0x40 | |
1985 | mtspr SPRN_CTRLT, r4 | |
1986 | blr | |
1987 | #endif | |
1988 | ||
14cf11af PM |
1989 | /* |
1990 | * We put a few things here that have to be page-aligned. | |
1991 | * This stuff goes at the beginning of the bss, which is page-aligned. | |
1992 | */ | |
1993 | .section ".bss" | |
1994 | ||
1995 | .align PAGE_SHIFT | |
1996 | ||
1997 | .globl empty_zero_page | |
1998 | empty_zero_page: | |
1999 | .space PAGE_SIZE | |
2000 | ||
2001 | .globl swapper_pg_dir | |
2002 | swapper_pg_dir: | |
2003 | .space PAGE_SIZE | |
2004 | ||
2005 | /* | |
2006 | * This space gets a copy of optional info passed to us by the bootstrap | |
2007 | * Used to pass parameters into the kernel like root=/dev/sda1, etc. | |
2008 | */ | |
2009 | .globl cmd_line | |
2010 | cmd_line: | |
2011 | .space COMMAND_LINE_SIZE |