projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[POWERPC] 8xx: Fix CONFIG_PIN_TLB.
[deliverable/linux.git] / arch / powerpc / kernel / head_8xx.S
CommitLineData
14cf11af 1/*
14cf11af
PM		 2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Low-level exception handlers and MMU support
7 * rewritten by Paul Mackerras.
8 * Copyright (C) 1996 Paul Mackerras.
9 * MPC8xx modifications by Dan Malek
10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
11 *
12 * This file contains low-level support and setup for PowerPC 8xx
13 * embedded processors, including trap and interrupt dispatch.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 *
20 */
21
14cf11af
PM		 22#include <asm/processor.h>
23#include <asm/page.h>
24#include <asm/mmu.h>
25#include <asm/cache.h>
26#include <asm/pgtable.h>
27#include <asm/cputable.h>
28#include <asm/thread_info.h>
29#include <asm/ppc_asm.h>
30#include <asm/asm-offsets.h>
31
32/* Macro to make the code more readable. */
33#ifdef CONFIG_8xx_CPU6
34#define DO_8xx_CPU6(val, reg) \
35 li reg, val; \
36 stw reg, 12(r0); \
37 lwz reg, 12(r0);
38#else
39#define DO_8xx_CPU6(val, reg)
40#endif
748a7683
KG		 41 .section .text.head, "ax"
42_ENTRY(_stext);
43_ENTRY(_start);
14cf11af
PM		 44
45/* MPC8xx
46 * This port was done on an MBX board with an 860. Right now I only
47 * support an ELF compressed (zImage) boot from EPPC-Bug because the
48 * code there loads up some registers before calling us:
49 * r3: ptr to board info data
50 * r4: initrd_start or if no initrd then 0
51 * r5: initrd_end - unused if r4 is 0
52 * r6: Start of command line string
53 * r7: End of command line string
54 *
55 * I decided to use conditional compilation instead of checking PVR and
56 * adding more processor specific branches around code I don't need.
57 * Since this is an embedded processor, I also appreciate any memory
58 * savings I can get.
59 *
60 * The MPC8xx does not have any BATs, but it supports large page sizes.
61 * We first initialize the MMU to support 8M byte pages, then load one
62 * entry into each of the instruction and data TLBs to map the first
63 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to
64 * the "internal" processor registers before MMU_init is called.
65 *
66 * The TLB code currently contains a major hack. Since I use the condition
67 * code register, I have to save and restore it. I am out of registers, so
68 * I just store it in memory location 0 (the TLB handlers are not reentrant).
69 * To avoid making any decisions, I need to use the "segment" valid bit
70 * in the first level table, but that would require many changes to the
71 * Linux page directory/table functions that I don't want to do right now.
72 *
73 * I used to use SPRG2 for a temporary register in the TLB handler, but it
74 * has since been put to other uses. I now use a hack to save a register
75 * and the CCR at memory location 0.....Someday I'll fix this.....
76 * -- Dan
77 */
78 .globl __start
79__start:
80 mr r31,r3 /* save parameters */
81 mr r30,r4
82 mr r29,r5
83 mr r28,r6
84 mr r27,r7
85
86 /* We have to turn on the MMU right away so we get cache modes
87 * set correctly.
88 */
89 bl initial_mmu
90
91/* We now have the lower 8 Meg mapped into TLB entries, and the caches
92 * ready to work.
93 */
94
95turn_on_mmu:
96 mfmsr r0
97 ori r0,r0,MSR_DR|MSR_IR
98 mtspr SPRN_SRR1,r0
99 lis r0,start_here@h
100 ori r0,r0,start_here@l
101 mtspr SPRN_SRR0,r0
102 SYNC
103 rfi /* enables MMU */
104
105/*
106 * Exception entry code. This code runs with address translation
107 * turned off, i.e. using physical addresses.
108 * We assume sprg3 has the physical address of the current
109 * task's thread_struct.
110 */
111#define EXCEPTION_PROLOG \
112 mtspr SPRN_SPRG0,r10; \
113 mtspr SPRN_SPRG1,r11; \
114 mfcr r10; \
115 EXCEPTION_PROLOG_1; \
116 EXCEPTION_PROLOG_2
117
118#define EXCEPTION_PROLOG_1 \
119 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
120 andi. r11,r11,MSR_PR; \
121 tophys(r11,r1); /* use tophys(r1) if kernel */ \
122 beq 1f; \
123 mfspr r11,SPRN_SPRG3; \
124 lwz r11,THREAD_INFO-THREAD(r11); \
125 addi r11,r11,THREAD_SIZE; \
126 tophys(r11,r11); \
1271: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
128
129
130#define EXCEPTION_PROLOG_2 \
131 CLR_TOP32(r11); \
132 stw r10,_CCR(r11); /* save registers */ \
133 stw r12,GPR12(r11); \
134 stw r9,GPR9(r11); \
135 mfspr r10,SPRN_SPRG0; \
136 stw r10,GPR10(r11); \
137 mfspr r12,SPRN_SPRG1; \
138 stw r12,GPR11(r11); \
139 mflr r10; \
140 stw r10,_LINK(r11); \
141 mfspr r12,SPRN_SRR0; \
142 mfspr r9,SPRN_SRR1; \
143 stw r1,GPR1(r11); \
144 stw r1,0(r11); \
145 tovirt(r1,r11); /* set new kernel sp */ \
146 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
147 MTMSRD(r10); /* (except for mach check in rtas) */ \
148 stw r0,GPR0(r11); \
149 SAVE_4GPRS(3, r11); \
150 SAVE_2GPRS(7, r11)
151
152/*
153 * Note: code which follows this uses cr0.eq (set if from kernel),
154 * r11, r12 (SRR0), and r9 (SRR1).
155 *
156 * Note2: once we have set r1 we are in a position to take exceptions
157 * again, and we could thus set MSR:RI at that point.
158 */
159
160/*
161 * Exception vectors.
162 */
163#define EXCEPTION(n, label, hdlr, xfer) \
164 . = n; \
165label: \
166 EXCEPTION_PROLOG; \
167 addi r3,r1,STACK_FRAME_OVERHEAD; \
168 xfer(n, hdlr)
169
170#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
171 li r10,trap; \
d73e0c99 172 stw r10,_TRAP(r11); \
14cf11af
PM		 173 li r10,MSR_KERNEL; \
174 copyee(r10, r9); \
175 bl tfer; \
176i##n: \
177 .long hdlr; \
178 .long ret
179
180#define COPY_EE(d, s) rlwimi d,s,0,16,16
181#define NOCOPY(d, s)
182
183#define EXC_XFER_STD(n, hdlr) \
184 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
185 ret_from_except_full)
186
187#define EXC_XFER_LITE(n, hdlr) \
188 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
189 ret_from_except)
190
191#define EXC_XFER_EE(n, hdlr) \
192 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
193 ret_from_except_full)
194
195#define EXC_XFER_EE_LITE(n, hdlr) \
196 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
197 ret_from_except)
198
199/* System reset */
dc1c1ca3 200 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
14cf11af
PM		 201
202/* Machine check */
203 . = 0x200
204MachineCheck:
205 EXCEPTION_PROLOG
206 mfspr r4,SPRN_DAR
207 stw r4,_DAR(r11)
208 mfspr r5,SPRN_DSISR
209 stw r5,_DSISR(r11)
210 addi r3,r1,STACK_FRAME_OVERHEAD
dc1c1ca3 211 EXC_XFER_STD(0x200, machine_check_exception)
14cf11af
PM		 212
213/* Data access exception.
214 * This is "never generated" by the MPC8xx. We jump to it for other
215 * translation errors.
216 */
217 . = 0x300
218DataAccess:
219 EXCEPTION_PROLOG
220 mfspr r10,SPRN_DSISR
221 stw r10,_DSISR(r11)
222 mr r5,r10
223 mfspr r4,SPRN_DAR
224 EXC_XFER_EE_LITE(0x300, handle_page_fault)
225
226/* Instruction access exception.
227 * This is "never generated" by the MPC8xx. We jump to it for other
228 * translation errors.
229 */
230 . = 0x400
231InstructionAccess:
232 EXCEPTION_PROLOG
233 mr r4,r12
234 mr r5,r9
235 EXC_XFER_EE_LITE(0x400, handle_page_fault)
236
237/* External interrupt */
238 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
239
240/* Alignment exception */
241 . = 0x600
242Alignment:
243 EXCEPTION_PROLOG
244 mfspr r4,SPRN_DAR
245 stw r4,_DAR(r11)
246 mfspr r5,SPRN_DSISR
247 stw r5,_DSISR(r11)
248 addi r3,r1,STACK_FRAME_OVERHEAD
dc1c1ca3 249 EXC_XFER_EE(0x600, alignment_exception)
14cf11af
PM		 250
251/* Program check exception */
dc1c1ca3 252 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
14cf11af
PM		 253
254/* No FPU on MPC8xx. This exception is not supposed to happen.
255*/
dc1c1ca3 256 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD)
14cf11af
PM		 257
258/* Decrementer */
259 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
260
dc1c1ca3
SR		 261 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
262 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
14cf11af
PM		 263
264/* System call */
265 . = 0xc00
266SystemCall:
267 EXCEPTION_PROLOG
268 EXC_XFER_EE_LITE(0xc00, DoSyscall)
269
270/* Single step - not used on 601 */
dc1c1ca3
SR		 271 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
272 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
273 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE)
14cf11af
PM		 274
275/* On the MPC8xx, this is a software emulation interrupt. It occurs
276 * for all unimplemented and illegal instructions.
277 */
278 EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD)
279
280 . = 0x1100
281/*
282 * For the MPC8xx, this is a software tablewalk to load the instruction
283 * TLB. It is modelled after the example in the Motorola manual. The task
284 * switch loads the M_TWB register with the pointer to the first level table.
285 * If we discover there is no second level table (value is zero) or if there
286 * is an invalid pte, we load that into the TLB, which causes another fault
287 * into the TLB Error interrupt where we can handle such problems.
288 * We have to use the MD_xxx registers for the tablewalk because the
289 * equivalent MI_xxx registers only perform the attribute functions.
290 */
291InstructionTLBMiss:
292#ifdef CONFIG_8xx_CPU6
293 stw r3, 8(r0)
294#endif
295 DO_8xx_CPU6(0x3f80, r3)
296 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
297 mfcr r10
298 stw r10, 0(r0)
299 stw r11, 4(r0)
300 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
301 DO_8xx_CPU6(0x3780, r3)
302 mtspr SPRN_MD_EPN, r10 /* Have to use MD_EPN for walk, MI_EPN can't */
303 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
304
305 /* If we are faulting a kernel address, we have to use the
306 * kernel page tables.
307 */
308 andi. r11, r10, 0x0800 /* Address >= 0x80000000 */
309 beq 3f
310 lis r11, swapper_pg_dir@h
311 ori r11, r11, swapper_pg_dir@l
312 rlwimi r10, r11, 0, 2, 19
3133:
314 lwz r11, 0(r10) /* Get the level 1 entry */
315 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
316 beq 2f /* If zero, don't try to find a pte */
317
318 /* We have a pte table, so load the MI_TWC with the attributes
319 * for this "segment."
320 */
321 ori r11,r11,1 /* Set valid bit */
322 DO_8xx_CPU6(0x2b80, r3)
323 mtspr SPRN_MI_TWC, r11 /* Set segment attributes */
324 DO_8xx_CPU6(0x3b80, r3)
325 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
326 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
327 lwz r10, 0(r11) /* Get the pte */
328
329 ori r10, r10, _PAGE_ACCESSED
330 stw r10, 0(r11)
331
332 /* The Linux PTE won't go exactly into the MMU TLB.
333 * Software indicator bits 21, 22 and 28 must be clear.
334 * Software indicator bits 24, 25, 26, and 27 must be
335 * set. All other Linux PTE bits control the behavior
336 * of the MMU.
337 */
3382: li r11, 0x00f0
339 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
340 DO_8xx_CPU6(0x2d80, r3)
341 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
342
343 mfspr r10, SPRN_M_TW /* Restore registers */
344 lwz r11, 0(r0)
345 mtcr r11
346 lwz r11, 4(r0)
347#ifdef CONFIG_8xx_CPU6
348 lwz r3, 8(r0)
349#endif
350 rfi
351
352 . = 0x1200
353DataStoreTLBMiss:
354#ifdef CONFIG_8xx_CPU6
355 stw r3, 8(r0)
356#endif
357 DO_8xx_CPU6(0x3f80, r3)
358 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
359 mfcr r10
360 stw r10, 0(r0)
361 stw r11, 4(r0)
362 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
363
364 /* If we are faulting a kernel address, we have to use the
365 * kernel page tables.
366 */
367 andi. r11, r10, 0x0800
368 beq 3f
369 lis r11, swapper_pg_dir@h
370 ori r11, r11, swapper_pg_dir@l
371 rlwimi r10, r11, 0, 2, 19
3723:
373 lwz r11, 0(r10) /* Get the level 1 entry */
374 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
375 beq 2f /* If zero, don't try to find a pte */
376
377 /* We have a pte table, so load fetch the pte from the table.
378 */
379 ori r11, r11, 1 /* Set valid bit in physical L2 page */
380 DO_8xx_CPU6(0x3b80, r3)
381 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
382 mfspr r10, SPRN_MD_TWC /* ....and get the pte address */
383 lwz r10, 0(r10) /* Get the pte */
384
385 /* Insert the Guarded flag into the TWC from the Linux PTE.
386 * It is bit 27 of both the Linux PTE and the TWC (at least
387 * I got that right :-). It will be better when we can put
388 * this into the Linux pgd/pmd and load it in the operation
389 * above.
390 */
391 rlwimi r11, r10, 0, 27, 27
392 DO_8xx_CPU6(0x3b80, r3)
393 mtspr SPRN_MD_TWC, r11
394
395 mfspr r11, SPRN_MD_TWC /* get the pte address again */
396 ori r10, r10, _PAGE_ACCESSED
397 stw r10, 0(r11)
398
399 /* The Linux PTE won't go exactly into the MMU TLB.
400 * Software indicator bits 21, 22 and 28 must be clear.
401 * Software indicator bits 24, 25, 26, and 27 must be
402 * set. All other Linux PTE bits control the behavior
403 * of the MMU.
404 */
4052: li r11, 0x00f0
406 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
407 DO_8xx_CPU6(0x3d80, r3)
408 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
409
410 mfspr r10, SPRN_M_TW /* Restore registers */
411 lwz r11, 0(r0)
412 mtcr r11
413 lwz r11, 4(r0)
414#ifdef CONFIG_8xx_CPU6
415 lwz r3, 8(r0)
416#endif
417 rfi
418
419/* This is an instruction TLB error on the MPC8xx. This could be due
420 * to many reasons, such as executing guarded memory or illegal instruction
421 * addresses. There is nothing to do but handle a big time error fault.
422 */
423 . = 0x1300
424InstructionTLBError:
425 b InstructionAccess
426
427/* This is the data TLB error on the MPC8xx. This could be due to
428 * many reasons, including a dirty update to a pte. We can catch that
429 * one here, but anything else is an error. First, we track down the
430 * Linux pte. If it is valid, write access is allowed, but the
431 * page dirty bit is not set, we will set it and reload the TLB. For
432 * any other case, we bail out to a higher level function that can
433 * handle it.
434 */
435 . = 0x1400
436DataTLBError:
437#ifdef CONFIG_8xx_CPU6
438 stw r3, 8(r0)
439#endif
440 DO_8xx_CPU6(0x3f80, r3)
441 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
442 mfcr r10
443 stw r10, 0(r0)
444 stw r11, 4(r0)
445
446 /* First, make sure this was a store operation.
447 */
448 mfspr r10, SPRN_DSISR
449 andis. r11, r10, 0x0200 /* If set, indicates store op */
450 beq 2f
451
452 /* The EA of a data TLB miss is automatically stored in the MD_EPN
453 * register. The EA of a data TLB error is automatically stored in
454 * the DAR, but not the MD_EPN register. We must copy the 20 most
455 * significant bits of the EA from the DAR to MD_EPN before we
456 * start walking the page tables. We also need to copy the CASID
457 * value from the M_CASID register.
458 * Addendum: The EA of a data TLB error is _supposed_ to be stored
459 * in DAR, but it seems that this doesn't happen in some cases, such
460 * as when the error is due to a dcbi instruction to a page with a
461 * TLB that doesn't have the changed bit set. In such cases, there
462 * does not appear to be any way to recover the EA of the error
463 * since it is neither in DAR nor MD_EPN. As a workaround, the
464 * _PAGE_HWWRITE bit is set for all kernel data pages when the PTEs
465 * are initialized in mapin_ram(). This will avoid the problem,
466 * assuming we only use the dcbi instruction on kernel addresses.
467 */
468 mfspr r10, SPRN_DAR
469 rlwinm r11, r10, 0, 0, 19
470 ori r11, r11, MD_EVALID
471 mfspr r10, SPRN_M_CASID
472 rlwimi r11, r10, 0, 28, 31
473 DO_8xx_CPU6(0x3780, r3)
474 mtspr SPRN_MD_EPN, r11
475
476 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
477
478 /* If we are faulting a kernel address, we have to use the
479 * kernel page tables.
480 */
481 andi. r11, r10, 0x0800
482 beq 3f
483 lis r11, swapper_pg_dir@h
484 ori r11, r11, swapper_pg_dir@l
485 rlwimi r10, r11, 0, 2, 19
4863:
487 lwz r11, 0(r10) /* Get the level 1 entry */
488 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
489 beq 2f /* If zero, bail */
490
491 /* We have a pte table, so fetch the pte from the table.
492 */
493 ori r11, r11, 1 /* Set valid bit in physical L2 page */
494 DO_8xx_CPU6(0x3b80, r3)
495 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
496 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
497 lwz r10, 0(r11) /* Get the pte */
498
499 andi. r11, r10, _PAGE_RW /* Is it writeable? */
500 beq 2f /* Bail out if not */
501
502 /* Update 'changed', among others.
503 */
504 ori r10, r10, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
505 mfspr r11, SPRN_MD_TWC /* Get pte address again */
506 stw r10, 0(r11) /* and update pte in table */
507
508 /* The Linux PTE won't go exactly into the MMU TLB.
509 * Software indicator bits 21, 22 and 28 must be clear.
510 * Software indicator bits 24, 25, 26, and 27 must be
511 * set. All other Linux PTE bits control the behavior
512 * of the MMU.
513 */
514 li r11, 0x00f0
515 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
516 DO_8xx_CPU6(0x3d80, r3)
517 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
518
519 mfspr r10, SPRN_M_TW /* Restore registers */
520 lwz r11, 0(r0)
521 mtcr r11
522 lwz r11, 4(r0)
523#ifdef CONFIG_8xx_CPU6
524 lwz r3, 8(r0)
525#endif
526 rfi
5272:
528 mfspr r10, SPRN_M_TW /* Restore registers */
529 lwz r11, 0(r0)
530 mtcr r11
531 lwz r11, 4(r0)
532#ifdef CONFIG_8xx_CPU6
533 lwz r3, 8(r0)
534#endif
535 b DataAccess
536
dc1c1ca3
SR		 537 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
538 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
539 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE)
540 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
541 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
542 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
543 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
14cf11af
PM		 544
545/* On the MPC8xx, these next four traps are used for development
546 * support of breakpoints and such. Someday I will get around to
547 * using them.
548 */
dc1c1ca3
SR		 549 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
550 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
551 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
552 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
14cf11af
PM		 553
554 . = 0x2000
555
556 .globl giveup_fpu
557giveup_fpu:
558 blr
559
560/*
561 * This is where the main kernel code starts.
562 */
563start_here:
564 /* ptr to current */
565 lis r2,init_task@h
566 ori r2,r2,init_task@l
567
568 /* ptr to phys current thread */
569 tophys(r4,r2)
570 addi r4,r4,THREAD /* init task's THREAD */
571 mtspr SPRN_SPRG3,r4
572 li r3,0
573 mtspr SPRN_SPRG2,r3 /* 0 => r1 has kernel sp */
574
575 /* stack */
576 lis r1,init_thread_union@ha
577 addi r1,r1,init_thread_union@l
578 li r0,0
579 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
580
581 bl early_init /* We have to do this with MMU on */
582
583/*
584 * Decide what sort of machine this is and initialize the MMU.
585 */
586 mr r3,r31
587 mr r4,r30
588 mr r5,r29
589 mr r6,r28
590 mr r7,r27
591 bl machine_init
592 bl MMU_init
593
594/*
595 * Go back to running unmapped so we can load up new values
596 * and change to using our exception vectors.
597 * On the 8xx, all we have to do is invalidate the TLB to clear
598 * the old 8M byte TLB mappings and load the page table base register.
599 */
600 /* The right way to do this would be to track it down through
601 * init's THREAD like the context switch code does, but this is
602 * easier......until someone changes init's static structures.
603 */
604 lis r6, swapper_pg_dir@h
605 ori r6, r6, swapper_pg_dir@l
606 tophys(r6,r6)
607#ifdef CONFIG_8xx_CPU6
608 lis r4, cpu6_errata_word@h
609 ori r4, r4, cpu6_errata_word@l
610 li r3, 0x3980
611 stw r3, 12(r4)
612 lwz r3, 12(r4)
613#endif
614 mtspr SPRN_M_TWB, r6
615 lis r4,2f@h
616 ori r4,r4,2f@l
617 tophys(r4,r4)
618 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
619 mtspr SPRN_SRR0,r4
620 mtspr SPRN_SRR1,r3
621 rfi
622/* Load up the kernel context */
6232:
624 SYNC /* Force all PTE updates to finish */
625 tlbia /* Clear all TLB entries */
626 sync /* wait for tlbia/tlbie to finish */
627 TLBSYNC /* ... on all CPUs */
628
629 /* set up the PTE pointers for the Abatron bdiGDB.
630 */
631 tovirt(r6,r6)
632 lis r5, abatron_pteptrs@h
633 ori r5, r5, abatron_pteptrs@l
634 stw r5, 0xf0(r0) /* Must match your Abatron config file */
635 tophys(r5,r5)
636 stw r6, 0(r5)
637
638/* Now turn on the MMU for real! */
639 li r4,MSR_KERNEL
640 lis r3,start_kernel@h
641 ori r3,r3,start_kernel@l
642 mtspr SPRN_SRR0,r3
643 mtspr SPRN_SRR1,r4
644 rfi /* enable MMU and jump to start_kernel */
645
646/* Set up the initial MMU state so we can do the first level of
647 * kernel initialization. This maps the first 8 MBytes of memory 1:1
648 * virtual to physical. Also, set the cache mode since that is defined
649 * by TLB entries and perform any additional mapping (like of the IMMR).
650 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel,
651 * 24 Mbytes of data, and the 8M IMMR space. Anything not covered by
652 * these mappings is mapped by page tables.
653 */
654initial_mmu:
655 tlbia /* Invalidate all TLB entries */
656#ifdef CONFIG_PIN_TLB
657 lis r8, MI_RSV4I@h
658 ori r8, r8, 0x1c00
659#else
660 li r8, 0
661#endif
662 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
663
664#ifdef CONFIG_PIN_TLB
665 lis r10, (MD_RSV4I | MD_RESETVAL)@h
666 ori r10, r10, 0x1c00
667 mr r8, r10
668#else
669 lis r10, MD_RESETVAL@h
670#endif
671#ifndef CONFIG_8xx_COPYBACK
672 oris r10, r10, MD_WTDEF@h
673#endif
674 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
675
676 /* Now map the lower 8 Meg into the TLBs. For this quick hack,
677 * we can load the instruction and data TLB registers with the
678 * same values.
679 */
680 lis r8, KERNELBASE@h /* Create vaddr for TLB */
681 ori r8, r8, MI_EVALID /* Mark it valid */
682 mtspr SPRN_MI_EPN, r8
683 mtspr SPRN_MD_EPN, r8
684 li r8, MI_PS8MEG /* Set 8M byte page */
685 ori r8, r8, MI_SVALID /* Make it valid */
686 mtspr SPRN_MI_TWC, r8
687 mtspr SPRN_MD_TWC, r8
688 li r8, MI_BOOTINIT /* Create RPN for address 0 */
689 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */
690 mtspr SPRN_MD_RPN, r8
691 lis r8, MI_Kp@h /* Set the protection mode */
692 mtspr SPRN_MI_AP, r8
693 mtspr SPRN_MD_AP, r8
694
695 /* Map another 8 MByte at the IMMR to get the processor
696 * internal registers (among other things).
697 */
698#ifdef CONFIG_PIN_TLB
699 addi r10, r10, 0x0100
700 mtspr SPRN_MD_CTR, r10
701#endif
702 mfspr r9, 638 /* Get current IMMR */
703 andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */
704
705 mr r8, r9 /* Create vaddr for TLB */
706 ori r8, r8, MD_EVALID /* Mark it valid */
707 mtspr SPRN_MD_EPN, r8
708 li r8, MD_PS8MEG /* Set 8M byte page */
709 ori r8, r8, MD_SVALID /* Make it valid */
710 mtspr SPRN_MD_TWC, r8
711 mr r8, r9 /* Create paddr for TLB */
712 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
713 mtspr SPRN_MD_RPN, r8
714
715#ifdef CONFIG_PIN_TLB
716 /* Map two more 8M kernel data pages.
717 */
718 addi r10, r10, 0x0100
719 mtspr SPRN_MD_CTR, r10
720
721 lis r8, KERNELBASE@h /* Create vaddr for TLB */
722 addis r8, r8, 0x0080 /* Add 8M */
723 ori r8, r8, MI_EVALID /* Mark it valid */
724 mtspr SPRN_MD_EPN, r8
725 li r9, MI_PS8MEG /* Set 8M byte page */
726 ori r9, r9, MI_SVALID /* Make it valid */
727 mtspr SPRN_MD_TWC, r9
728 li r11, MI_BOOTINIT /* Create RPN for address 0 */
729 addis r11, r11, 0x0080 /* Add 8M */
ccf0d68e 730 mtspr SPRN_MD_RPN, r11
14cf11af
PM		 731
732 addis r8, r8, 0x0080 /* Add 8M */
733 mtspr SPRN_MD_EPN, r8
734 mtspr SPRN_MD_TWC, r9
735 addis r11, r11, 0x0080 /* Add 8M */
ccf0d68e 736 mtspr SPRN_MD_RPN, r11
14cf11af
PM		 737#endif
738
739 /* Since the cache is enabled according to the information we
740 * just loaded into the TLB, invalidate and enable the caches here.
741 * We should probably check/set other modes....later.
742 */
743 lis r8, IDC_INVALL@h
744 mtspr SPRN_IC_CST, r8
745 mtspr SPRN_DC_CST, r8
746 lis r8, IDC_ENABLE@h
747 mtspr SPRN_IC_CST, r8
748#ifdef CONFIG_8xx_COPYBACK
749 mtspr SPRN_DC_CST, r8
750#else
751 /* For a debug option, I left this here to easily enable
752 * the write through cache mode
753 */
754 lis r8, DC_SFWT@h
755 mtspr SPRN_DC_CST, r8
756 lis r8, IDC_ENABLE@h
757 mtspr SPRN_DC_CST, r8
758#endif
759 blr
760
761
762/*
763 * Set up to use a given MMU context.
764 * r3 is context number, r4 is PGD pointer.
765 *
766 * We place the physical address of the new task page directory loaded
767 * into the MMU base register, and set the ASID compare register with
768 * the new "context."
769 */
770_GLOBAL(set_context)
771
772#ifdef CONFIG_BDI_SWITCH
773 /* Context switch the PTE pointer for the Abatron BDI2000.
774 * The PGDIR is passed as second argument.
775 */
776 lis r5, KERNELBASE@h
777 lwz r5, 0xf0(r5)
778 stw r4, 0x4(r5)
779#endif
780
781#ifdef CONFIG_8xx_CPU6
782 lis r6, cpu6_errata_word@h
783 ori r6, r6, cpu6_errata_word@l
784 tophys (r4, r4)
785 li r7, 0x3980
786 stw r7, 12(r6)
787 lwz r7, 12(r6)
788 mtspr SPRN_M_TWB, r4 /* Update MMU base address */
789 li r7, 0x3380
790 stw r7, 12(r6)
791 lwz r7, 12(r6)
792 mtspr SPRN_M_CASID, r3 /* Update context */
793#else
794 mtspr SPRN_M_CASID,r3 /* Update context */
795 tophys (r4, r4)
796 mtspr SPRN_M_TWB, r4 /* and pgd */
797#endif
798 SYNC
799 blr
800
801#ifdef CONFIG_8xx_CPU6
802/* It's here because it is unique to the 8xx.
803 * It is important we get called with interrupts disabled. I used to
804 * do that, but it appears that all code that calls this already had
805 * interrupt disabled.
806 */
807 .globl set_dec_cpu6
808set_dec_cpu6:
809 lis r7, cpu6_errata_word@h
810 ori r7, r7, cpu6_errata_word@l
811 li r4, 0x2c00
812 stw r4, 8(r7)
813 lwz r4, 8(r7)
814 mtspr 22, r3 /* Update Decrementer */
815 SYNC
816 blr
817#endif
818
819/*
820 * We put a few things here that have to be page-aligned.
821 * This stuff goes at the beginning of the data segment,
822 * which is page-aligned.
823 */
824 .data
825 .globl sdata
826sdata:
827 .globl empty_zero_page
828empty_zero_page:
829 .space 4096
830
831 .globl swapper_pg_dir
832swapper_pg_dir:
833 .space 4096
834
14cf11af
PM		 835/* Room for two PTE table poiners, usually the kernel and current user
836 * pointer to their respective root page table (pgdir).
837 */
838abatron_pteptrs:
839 .space 8
840
841#ifdef CONFIG_8xx_CPU6
842 .globl cpu6_errata_word
843cpu6_errata_word:
844 .space 16
845#endif
846
Linux kernel - Deliverables
This page took 0.213845 seconds and 5 git commands to generate.