[deliverable/linux.git] / arch / powerpc / kernel / head_booke.h

#ifndef __HEAD_BOOKE_H__
#define __HEAD_BOOKE_H__

/*
 * Macros used for common Book-e exception handling
 */

#define SET_IVOR(vector_number, vector_label)		\
		li	r26,vector_label@l; 		\
		mtspr	SPRN_IVOR##vector_number,r26;	\
		sync

#if (THREAD_SHIFT < 15)
#define ALLOC_STACK_FRAME(reg, val)			\
	addi reg,reg,val
#else
#define ALLOC_STACK_FRAME(reg, val)			\
	addis	reg,reg,val@ha;				\
	addi	reg,reg,val@l
#endif

#define NORMAL_EXCEPTION_PROLOG						     \
	mtspr	SPRN_SPRG0,r10;		/* save two registers to work with */\
	mtspr	SPRN_SPRG1,r11;						     \
	mtspr	SPRN_SPRG4W,r1;						     \
	mfcr	r10;			/* save CR in r10 for now	   */\
	mfspr	r11,SPRN_SRR1;		/* check whether user or kernel    */\
	andi.	r11,r11,MSR_PR;						     \
	beq	1f;							     \
	mfspr	r1,SPRN_SPRG3;		/* if from user, start at top of   */\
	lwz	r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack   */\
	ALLOC_STACK_FRAME(r1, THREAD_SIZE);				     \
1:	subi	r1,r1,INT_FRAME_SIZE;	/* Allocate an exception frame     */\
	mr	r11,r1;							     \
	stw	r10,_CCR(r11);          /* save various registers	   */\
	stw	r12,GPR12(r11);						     \
	stw	r9,GPR9(r11);						     \
	mfspr	r10,SPRN_SPRG0;						     \
	stw	r10,GPR10(r11);						     \
	mfspr	r12,SPRN_SPRG1;						     \
	stw	r12,GPR11(r11);						     \
	mflr	r10;							     \
	stw	r10,_LINK(r11);						     \
	mfspr	r10,SPRN_SPRG4R;					     \
	mfspr	r12,SPRN_SRR0;						     \
	stw	r10,GPR1(r11);						     \
	mfspr	r9,SPRN_SRR1;						     \
	stw	r10,0(r11);						     \
	rlwinm	r9,r9,0,14,12;		/* clear MSR_WE (necessary?)	   */\
	stw	r0,GPR0(r11);						     \
	SAVE_4GPRS(3, r11);						     \
	SAVE_2GPRS(7, r11)

/* To handle the additional exception priority levels on 40x and Book-E
 * processors we allocate a stack per additional priority level.
 *
 * On 40x critical is the only additional level
 * On 44x/e500 we have critical and machine check
 * On e200 we have critical and debug (machine check occurs via critical)
 *
 * Additionally we reserve a SPRG for each priority level so we can free up a
 * GPR to use as the base for indirect access to the exception stacks.  This
 * is necessary since the MMU is always on, for Book-E parts, and the stacks
 * are offset from KERNELBASE.
 *
 * There is some space optimization to be had here if desired.  However
 * to allow for a common kernel with support for debug exceptions either
 * going to critical or their own debug level we aren't currently
 * providing configurations that micro-optimize space usage.
 */

/* CRIT_SPRG only used in critical exception handling */
#define CRIT_SPRG	SPRN_SPRG2
/* MCHECK_SPRG only used in machine check exception handling */
#define MCHECK_SPRG	SPRN_SPRG6W

#define MCHECK_STACK_BASE	mcheckirq_ctx
#define CRIT_STACK_BASE		critirq_ctx

/* only on e500mc/e200 */
#define DEBUG_STACK_BASE	dbgirq_ctx
#ifdef CONFIG_E200
#define DEBUG_SPRG		SPRN_SPRG6W
#else
#define DEBUG_SPRG		SPRN_SPRG9
#endif

#define EXC_LVL_FRAME_OVERHEAD	(THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE)

#ifdef CONFIG_SMP
#define BOOKE_LOAD_EXC_LEVEL_STACK(level)		\
	mfspr	r8,SPRN_PIR;				\
	slwi	r8,r8,2;				\
	addis	r8,r8,level##_STACK_BASE@ha;		\
	lwz	r8,level##_STACK_BASE@l(r8);		\
	addi	r8,r8,EXC_LVL_FRAME_OVERHEAD;
#else
#define BOOKE_LOAD_EXC_LEVEL_STACK(level)		\
	lis	r8,level##_STACK_BASE@ha;		\
	lwz	r8,level##_STACK_BASE@l(r8);		\
	addi	r8,r8,EXC_LVL_FRAME_OVERHEAD;
#endif

/*
 * Exception prolog for critical/machine check exceptions.  This is a
 * little different from the normal exception prolog above since a
 * critical/machine check exception can potentially occur at any point
 * during normal exception processing. Thus we cannot use the same SPRG
 * registers as the normal prolog above. Instead we use a portion of the
 * critical/machine check exception stack at low physical addresses.
 */
#define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, exc_level_srr0, exc_level_srr1) \
	mtspr	exc_level##_SPRG,r8;					     \
	BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \
	stw	r9,GPR9(r8);		/* save various registers	   */\
	mfcr	r9;			/* save CR in r9 for now	   */\
	stw	r10,GPR10(r8);						     \
	stw	r11,GPR11(r8);						     \
	stw	r9,_CCR(r8);		/* save CR on stack		   */\
	mfspr	r10,exc_level_srr1;	/* check whether user or kernel    */\
	andi.	r10,r10,MSR_PR;						     \
	mfspr	r11,SPRN_SPRG3;		/* if from user, start at top of   */\
	lwz	r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
	addi	r11,r11,EXC_LVL_FRAME_OVERHEAD;	/* allocate stack frame    */\
	beq	1f;							     \
	/* COMING FROM USER MODE */					     \
	stw	r9,_CCR(r11);		/* save CR			   */\
	lwz	r10,GPR10(r8);		/* copy regs from exception stack  */\
	lwz	r9,GPR9(r8);						     \
	stw	r10,GPR10(r11);						     \
	lwz	r10,GPR11(r8);						     \
	stw	r9,GPR9(r11);						     \
	stw	r10,GPR11(r11);						     \
	b	2f;							     \
	/* COMING FROM PRIV MODE */					     \
1:	lwz	r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r11);		     \
	lwz	r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r11);		     \
	stw	r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r8);			     \
	stw	r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r8);		     \
	lwz	r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r11);			     \
	stw	r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r8);			     \
	mr	r11,r8;							     \
2:	mfspr	r8,exc_level##_SPRG;					     \
	stw	r12,GPR12(r11);		/* save various registers	   */\
	mflr	r10;							     \
	stw	r10,_LINK(r11);						     \
	mfspr	r12,SPRN_DEAR;		/* save DEAR and ESR in the frame  */\
	stw	r12,_DEAR(r11);		/* since they may have had stuff   */\
	mfspr	r9,SPRN_ESR;		/* in them at the point where the  */\
	stw	r9,_ESR(r11);		/* exception was taken		   */\
	mfspr	r12,exc_level_srr0;					     \
	stw	r1,GPR1(r11);						     \
	mfspr	r9,exc_level_srr1;					     \
	stw	r1,0(r11);						     \
	mr	r1,r11;							     \
	rlwinm	r9,r9,0,14,12;		/* clear MSR_WE (necessary?)	   */\
	stw	r0,GPR0(r11);						     \
	SAVE_4GPRS(3, r11);						     \
	SAVE_2GPRS(7, r11)

#define CRITICAL_EXCEPTION_PROLOG \
		EXC_LEVEL_EXCEPTION_PROLOG(CRIT, SPRN_CSRR0, SPRN_CSRR1)
#define DEBUG_EXCEPTION_PROLOG \
		EXC_LEVEL_EXCEPTION_PROLOG(DEBUG, SPRN_DSRR0, SPRN_DSRR1)
#define MCHECK_EXCEPTION_PROLOG \
		EXC_LEVEL_EXCEPTION_PROLOG(MCHECK, SPRN_MCSRR0, SPRN_MCSRR1)

/*
 * Exception vectors.
 */
#define	START_EXCEPTION(label)						     \
        .align 5;              						     \
label:

#define FINISH_EXCEPTION(func)					\
	bl	transfer_to_handler_full;			\
	.long	func;						\
	.long	ret_from_except_full

#define EXCEPTION(n, label, hdlr, xfer)				\
	START_EXCEPTION(label);					\
	NORMAL_EXCEPTION_PROLOG;				\
	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
	xfer(n, hdlr)

#define CRITICAL_EXCEPTION(n, label, hdlr)			\
	START_EXCEPTION(label);					\
	CRITICAL_EXCEPTION_PROLOG;				\
	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
	EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
			  NOCOPY, crit_transfer_to_handler, \
			  ret_from_crit_exc)

#define MCHECK_EXCEPTION(n, label, hdlr)			\
	START_EXCEPTION(label);					\
	MCHECK_EXCEPTION_PROLOG;				\
	mfspr	r5,SPRN_ESR;					\
	stw	r5,_ESR(r11);					\
	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
	EXC_XFER_TEMPLATE(hdlr, n+4, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
			  NOCOPY, mcheck_transfer_to_handler,   \
			  ret_from_mcheck_exc)

#define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret)	\
	li	r10,trap;					\
	stw	r10,_TRAP(r11);					\
	lis	r10,msr@h;					\
	ori	r10,r10,msr@l;					\
	copyee(r10, r9);					\
	bl	tfer;		 				\
	.long	hdlr;						\
	.long	ret

#define COPY_EE(d, s)		rlwimi d,s,0,16,16
#define NOCOPY(d, s)

#define EXC_XFER_STD(n, hdlr)		\
	EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \
			  ret_from_except_full)

#define EXC_XFER_LITE(n, hdlr)		\
	EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \
			  ret_from_except)

#define EXC_XFER_EE(n, hdlr)		\
	EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \
			  ret_from_except_full)

#define EXC_XFER_EE_LITE(n, hdlr)	\
	EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \
			  ret_from_except)

/* Check for a single step debug exception while in an exception
 * handler before state has been saved.  This is to catch the case
 * where an instruction that we are trying to single step causes
 * an exception (eg ITLB/DTLB miss) and thus the first instruction of
 * the exception handler generates a single step debug exception.
 *
 * If we get a debug trap on the first instruction of an exception handler,
 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
 * The exception handler was handling a non-critical interrupt, so it will
 * save (and later restore) the MSR via SPRN_CSRR1, which will still have
 * the MSR_DE bit set.
 */
#define DEBUG_DEBUG_EXCEPTION						      \
	START_EXCEPTION(DebugDebug);					      \
	DEBUG_EXCEPTION_PROLOG;						      \
									      \
	/*								      \
	 * If there is a single step or branch-taken exception in an	      \
	 * exception entry sequence, it was probably meant to apply to	      \
	 * the code where the exception occurred (since exception entry	      \
	 * doesn't turn off DE automatically).  We simulate the effect	      \
	 * of turning off DE on entry to an exception handler by turning      \
	 * off DE in the DSRR1 value and clearing the debug status.	      \
	 */								      \
	mfspr	r10,SPRN_DBSR;		/* check single-step/branch taken */  \
	andis.	r10,r10,DBSR_IC@h;					      \
	beq+	2f;							      \
									      \
	lis	r10,KERNELBASE@h;	/* check if exception in vectors */   \
	ori	r10,r10,KERNELBASE@l;					      \
	cmplw	r12,r10;						      \
	blt+	2f;			/* addr below exception vectors */    \
									      \
	lis	r10,DebugDebug@h;					      \
	ori	r10,r10,DebugDebug@l;					      \
	cmplw	r12,r10;						      \
	bgt+	2f;			/* addr above exception vectors */    \
									      \
	/* here it looks like we got an inappropriate debug exception. */     \
1:	rlwinm	r9,r9,0,~MSR_DE;	/* clear DE in the CDRR1 value */     \
	lis	r10,DBSR_IC@h;		/* clear the IC event */	      \
	mtspr	SPRN_DBSR,r10;						      \
	/* restore state and get out */					      \
	lwz	r10,_CCR(r11);						      \
	lwz	r0,GPR0(r11);						      \
	lwz	r1,GPR1(r11);						      \
	mtcrf	0x80,r10;						      \
	mtspr	SPRN_DSRR0,r12;						      \
	mtspr	SPRN_DSRR1,r9;						      \
	lwz	r9,GPR9(r11);						      \
	lwz	r12,GPR12(r11);						      \
	mtspr	DEBUG_SPRG,r8;						      \
	BOOKE_LOAD_EXC_LEVEL_STACK(DEBUG); /* r8 points to the debug stack */ \
	lwz	r10,GPR10(r8);						      \
	lwz	r11,GPR11(r8);						      \
	mfspr	r8,DEBUG_SPRG;						      \
									      \
	PPC_RFDI;								      \
	b	.;							      \
									      \
	/* continue normal handling for a debug exception... */		      \
2:	mfspr	r4,SPRN_DBSR;						      \
	addi	r3,r1,STACK_FRAME_OVERHEAD;				      \
	EXC_XFER_TEMPLATE(DebugException, 0x2008, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, debug_transfer_to_handler, ret_from_debug_exc)

#define DEBUG_CRIT_EXCEPTION						      \
	START_EXCEPTION(DebugCrit);					      \
	CRITICAL_EXCEPTION_PROLOG;					      \
									      \
	/*								      \
	 * If there is a single step or branch-taken exception in an	      \
	 * exception entry sequence, it was probably meant to apply to	      \
	 * the code where the exception occurred (since exception entry	      \
	 * doesn't turn off DE automatically).  We simulate the effect	      \
	 * of turning off DE on entry to an exception handler by turning      \
	 * off DE in the CSRR1 value and clearing the debug status.	      \
	 */								      \
	mfspr	r10,SPRN_DBSR;		/* check single-step/branch taken */  \
	andis.	r10,r10,DBSR_IC@h;					      \
	beq+	2f;							      \
									      \
	lis	r10,KERNELBASE@h;	/* check if exception in vectors */   \
	ori	r10,r10,KERNELBASE@l;					      \
	cmplw	r12,r10;						      \
	blt+	2f;			/* addr below exception vectors */    \
									      \
	lis	r10,DebugCrit@h;						      \
	ori	r10,r10,DebugCrit@l;					      \
	cmplw	r12,r10;						      \
	bgt+	2f;			/* addr above exception vectors */    \
									      \
	/* here it looks like we got an inappropriate debug exception. */     \
1:	rlwinm	r9,r9,0,~MSR_DE;	/* clear DE in the CSRR1 value */     \
	lis	r10,DBSR_IC@h;		/* clear the IC event */	      \
	mtspr	SPRN_DBSR,r10;						      \
	/* restore state and get out */					      \
	lwz	r10,_CCR(r11);						      \
	lwz	r0,GPR0(r11);						      \
	lwz	r1,GPR1(r11);						      \
	mtcrf	0x80,r10;						      \
	mtspr	SPRN_CSRR0,r12;						      \
	mtspr	SPRN_CSRR1,r9;						      \
	lwz	r9,GPR9(r11);						      \
	lwz	r12,GPR12(r11);						      \
	mtspr	CRIT_SPRG,r8;						      \
	BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */  \
	lwz	r10,GPR10(r8);						      \
	lwz	r11,GPR11(r8);						      \
	mfspr	r8,CRIT_SPRG;						      \
									      \
	rfci;								      \
	b	.;							      \
									      \
	/* continue normal handling for a critical exception... */	      \
2:	mfspr	r4,SPRN_DBSR;						      \
	addi	r3,r1,STACK_FRAME_OVERHEAD;				      \
	EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)

#define DATA_STORAGE_EXCEPTION						      \
	START_EXCEPTION(DataStorage)					      \
	NORMAL_EXCEPTION_PROLOG;					      \
	mfspr	r5,SPRN_ESR;		/* Grab the ESR and save it */	      \
	stw	r5,_ESR(r11);						      \
	mfspr	r4,SPRN_DEAR;		/* Grab the DEAR */		      \
	EXC_XFER_EE_LITE(0x0300, handle_page_fault)

#define INSTRUCTION_STORAGE_EXCEPTION					      \
	START_EXCEPTION(InstructionStorage)				      \
	NORMAL_EXCEPTION_PROLOG;					      \
	mfspr	r5,SPRN_ESR;		/* Grab the ESR and save it */	      \
	stw	r5,_ESR(r11);						      \
	mr      r4,r12;                 /* Pass SRR0 as arg2 */		      \
	li      r5,0;                   /* Pass zero as arg3 */		      \
	EXC_XFER_EE_LITE(0x0400, handle_page_fault)

#define ALIGNMENT_EXCEPTION						      \
	START_EXCEPTION(Alignment)					      \
	NORMAL_EXCEPTION_PROLOG;					      \
	mfspr   r4,SPRN_DEAR;           /* Grab the DEAR and save it */	      \
	stw     r4,_DEAR(r11);						      \
	addi    r3,r1,STACK_FRAME_OVERHEAD;				      \
	EXC_XFER_EE(0x0600, alignment_exception)

#define PROGRAM_EXCEPTION						      \
	START_EXCEPTION(Program)					      \
	NORMAL_EXCEPTION_PROLOG;					      \
	mfspr	r4,SPRN_ESR;		/* Grab the ESR and save it */	      \
	stw	r4,_ESR(r11);						      \
	addi	r3,r1,STACK_FRAME_OVERHEAD;				      \
	EXC_XFER_STD(0x0700, program_check_exception)

#define DECREMENTER_EXCEPTION						      \
	START_EXCEPTION(Decrementer)					      \
	NORMAL_EXCEPTION_PROLOG;					      \
	lis     r0,TSR_DIS@h;           /* Setup the DEC interrupt mask */    \
	mtspr   SPRN_TSR,r0;		/* Clear the DEC interrupt */	      \
	addi    r3,r1,STACK_FRAME_OVERHEAD;				      \
	EXC_XFER_LITE(0x0900, timer_interrupt)

#define FP_UNAVAILABLE_EXCEPTION					      \
	START_EXCEPTION(FloatingPointUnavailable)			      \
	NORMAL_EXCEPTION_PROLOG;					      \
	beq	1f;							      \
	bl	load_up_fpu;		/* if from user, just load it up */   \
	b	fast_exception_return;					      \
1:	addi	r3,r1,STACK_FRAME_OVERHEAD;				      \
	EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)

#ifndef __ASSEMBLY__
struct exception_regs {
	unsigned long mas0;
	unsigned long mas1;
	unsigned long mas2;
	unsigned long mas3;
	unsigned long mas6;
	unsigned long mas7;
	unsigned long srr0;
	unsigned long srr1;
	unsigned long csrr0;
	unsigned long csrr1;
	unsigned long dsrr0;
	unsigned long dsrr1;
	unsigned long saved_ksp_limit;
};

/* ensure this structure is always sized to a multiple of the stack alignment */
#define STACK_EXC_LVL_FRAME_SIZE	_ALIGN_UP(sizeof (struct exception_regs), 16)

#endif /* __ASSEMBLY__ */
#endif /* __HEAD_BOOKE_H__ */
Commit	Line	Data
63dafe57 BB	1	#ifndef __HEAD_BOOKE_H__
	2	#define __HEAD_BOOKE_H__
	3
	4	/*
	5	* Macros used for common Book-e exception handling
	6	*/
	7
	8	#define SET_IVOR(vector_number, vector_label) \
	9	li r26,vector_label@l; \
	10	mtspr SPRN_IVOR##vector_number,r26; \
	11	sync
	12
e1240122 YT	13	#if (THREAD_SHIFT < 15)
	14	#define ALLOC_STACK_FRAME(reg, val) \
	15	addi reg,reg,val
	16	#else
	17	#define ALLOC_STACK_FRAME(reg, val) \
	18	addis reg,reg,val@ha; \
	19	addi reg,reg,val@l
	20	#endif
	21
63dafe57 BB	22	#define NORMAL_EXCEPTION_PROLOG \
	23	mtspr SPRN_SPRG0,r10; /* save two registers to work with */\
	24	mtspr SPRN_SPRG1,r11; \
	25	mtspr SPRN_SPRG4W,r1; \
	26	mfcr r10; /* save CR in r10 for now */\
	27	mfspr r11,SPRN_SRR1; /* check whether user or kernel */\
	28	andi. r11,r11,MSR_PR; \
	29	beq 1f; \
	30	mfspr r1,SPRN_SPRG3; /* if from user, start at top of */\
	31	lwz r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack */\
e1240122	32	ALLOC_STACK_FRAME(r1, THREAD_SIZE); \
63dafe57 BB	33	1: subi r1,r1,INT_FRAME_SIZE; /* Allocate an exception frame */\
	34	mr r11,r1; \
	35	stw r10,_CCR(r11); /* save various registers */\
	36	stw r12,GPR12(r11); \
	37	stw r9,GPR9(r11); \
	38	mfspr r10,SPRN_SPRG0; \
	39	stw r10,GPR10(r11); \
	40	mfspr r12,SPRN_SPRG1; \
	41	stw r12,GPR11(r11); \
	42	mflr r10; \
	43	stw r10,_LINK(r11); \
	44	mfspr r10,SPRN_SPRG4R; \
	45	mfspr r12,SPRN_SRR0; \
	46	stw r10,GPR1(r11); \
	47	mfspr r9,SPRN_SRR1; \
	48	stw r10,0(r11); \
	49	rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
	50	stw r0,GPR0(r11); \
	51	SAVE_4GPRS(3, r11); \
	52	SAVE_2GPRS(7, r11)
	53
	54	/* To handle the additional exception priority levels on 40x and Book-E
bcf0b088	55	* processors we allocate a stack per additional priority level.
63dafe57 BB	56	*
	57	* On 40x critical is the only additional level
	58	* On 44x/e500 we have critical and machine check
	59	* On e200 we have critical and debug (machine check occurs via critical)
	60	*
	61	* Additionally we reserve a SPRG for each priority level so we can free up a
	62	* GPR to use as the base for indirect access to the exception stacks. This
	63	* is necessary since the MMU is always on, for Book-E parts, and the stacks
	64	* are offset from KERNELBASE.
	65	*
eb0cd5fd KG	66	* There is some space optimization to be had here if desired. However
	67	* to allow for a common kernel with support for debug exceptions either
	68	* going to critical or their own debug level we aren't currently
	69	* providing configurations that micro-optimize space usage.
63dafe57	70	*/
63dafe57 BB	71
	72	/* CRIT_SPRG only used in critical exception handling */
	73	#define CRIT_SPRG SPRN_SPRG2
	74	/* MCHECK_SPRG only used in machine check exception handling */
	75	#define MCHECK_SPRG SPRN_SPRG6W
	76
bcf0b088 KG	77	#define MCHECK_STACK_BASE mcheckirq_ctx
bcf0b088 KG	78	#define CRIT_STACK_BASE critirq_ctx
63dafe57	79
3dfa8773	80	/* only on e500mc/e200 */
bcf0b088	81	#define DEBUG_STACK_BASE dbgirq_ctx
105c31df	82	#ifdef CONFIG_E200
63dafe57	83	#define DEBUG_SPRG SPRN_SPRG6W
105c31df KG	84	#else
105c31df KG	85	#define DEBUG_SPRG SPRN_SPRG9
3dfa8773	86	#endif
63dafe57	87
fca622c5	88	#define EXC_LVL_FRAME_OVERHEAD (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE)
369e757b	89
63dafe57 BB	90	#ifdef CONFIG_SMP
	91	#define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
	92	mfspr r8,SPRN_PIR; \
bcf0b088 KG	93	slwi r8,r8,2; \
	94	addis r8,r8,level##_STACK_BASE@ha; \
	95	lwz r8,level##_STACK_BASE@l(r8); \
369e757b	96	addi r8,r8,EXC_LVL_FRAME_OVERHEAD;
63dafe57 BB	97	#else
63dafe57 BB	98	#define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
bcf0b088 KG	99	lis r8,level##_STACK_BASE@ha; \
bcf0b088 KG	100	lwz r8,level##_STACK_BASE@l(r8); \
369e757b	101	addi r8,r8,EXC_LVL_FRAME_OVERHEAD;
63dafe57 BB	102	#endif
	103
	104	/*
	105	* Exception prolog for critical/machine check exceptions. This is a
	106	* little different from the normal exception prolog above since a
	107	* critical/machine check exception can potentially occur at any point
	108	* during normal exception processing. Thus we cannot use the same SPRG
	109	* registers as the normal prolog above. Instead we use a portion of the
	110	* critical/machine check exception stack at low physical addresses.
	111	*/
	112	#define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, exc_level_srr0, exc_level_srr1) \
	113	mtspr exc_level##_SPRG,r8; \
	114	BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \
369e757b KG	115	stw r9,GPR9(r8); /* save various registers */\
	116	mfcr r9; /* save CR in r9 for now */\
	117	stw r10,GPR10(r8); \
	118	stw r11,GPR11(r8); \
	119	stw r9,_CCR(r8); /* save CR on stack */\
	120	mfspr r10,exc_level_srr1; /* check whether user or kernel */\
	121	andi. r10,r10,MSR_PR; \
63dafe57 BB	122	mfspr r11,SPRN_SPRG3; /* if from user, start at top of */\
63dafe57 BB	123	lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
369e757b KG	124	addi r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame */\
	125	beq 1f; \
	126	/* COMING FROM USER MODE */ \
	127	stw r9,_CCR(r11); /* save CR */\
	128	lwz r10,GPR10(r8); /* copy regs from exception stack */\
	129	lwz r9,GPR9(r8); \
	130	stw r10,GPR10(r11); \
	131	lwz r10,GPR11(r8); \
63dafe57	132	stw r9,GPR9(r11); \
369e757b KG	133	stw r10,GPR11(r11); \
	134	b 2f; \
	135	/* COMING FROM PRIV MODE */ \
	136	1: lwz r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r11); \
	137	lwz r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r11); \
	138	stw r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r8); \
	139	stw r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r8); \
	140	lwz r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r11); \
	141	stw r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r8); \
	142	mr r11,r8; \
	143	2: mfspr r8,exc_level##_SPRG; \
	144	stw r12,GPR12(r11); /* save various registers */\
63dafe57 BB	145	mflr r10; \
	146	stw r10,_LINK(r11); \
	147	mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\
	148	stw r12,_DEAR(r11); /* since they may have had stuff */\
	149	mfspr r9,SPRN_ESR; /* in them at the point where the */\
	150	stw r9,_ESR(r11); /* exception was taken */\
	151	mfspr r12,exc_level_srr0; \
	152	stw r1,GPR1(r11); \
	153	mfspr r9,exc_level_srr1; \
	154	stw r1,0(r11); \
	155	mr r1,r11; \
	156	rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
	157	stw r0,GPR0(r11); \
	158	SAVE_4GPRS(3, r11); \
	159	SAVE_2GPRS(7, r11)
	160
	161	#define CRITICAL_EXCEPTION_PROLOG \
	162	EXC_LEVEL_EXCEPTION_PROLOG(CRIT, SPRN_CSRR0, SPRN_CSRR1)
	163	#define DEBUG_EXCEPTION_PROLOG \
	164	EXC_LEVEL_EXCEPTION_PROLOG(DEBUG, SPRN_DSRR0, SPRN_DSRR1)
	165	#define MCHECK_EXCEPTION_PROLOG \
	166	EXC_LEVEL_EXCEPTION_PROLOG(MCHECK, SPRN_MCSRR0, SPRN_MCSRR1)
	167
	168	/*
	169	* Exception vectors.
	170	*/
	171	#define START_EXCEPTION(label) \
	172	.align 5; \
	173	label:
	174
	175	#define FINISH_EXCEPTION(func) \
	176	bl transfer_to_handler_full; \
	177	.long func; \
	178	.long ret_from_except_full
	179
	180	#define EXCEPTION(n, label, hdlr, xfer) \
	181	START_EXCEPTION(label); \
	182	NORMAL_EXCEPTION_PROLOG; \
	183	addi r3,r1,STACK_FRAME_OVERHEAD; \
	184	xfer(n, hdlr)
	185
	186	#define CRITICAL_EXCEPTION(n, label, hdlr) \
	187	START_EXCEPTION(label); \
	188	CRITICAL_EXCEPTION_PROLOG; \
	189	addi r3,r1,STACK_FRAME_OVERHEAD; \
	190	EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME\|MSR_DE\|MSR_CE)), \
	191	NOCOPY, crit_transfer_to_handler, \
	192	ret_from_crit_exc)
	193
	194	#define MCHECK_EXCEPTION(n, label, hdlr) \
	195	START_EXCEPTION(label); \
	196	MCHECK_EXCEPTION_PROLOG; \
	197	mfspr r5,SPRN_ESR; \
	198	stw r5,_ESR(r11); \
	199	addi r3,r1,STACK_FRAME_OVERHEAD; \
47c0bd1a	200	EXC_XFER_TEMPLATE(hdlr, n+4, (MSR_KERNEL & ~(MSR_ME\|MSR_DE\|MSR_CE)), \
63dafe57 BB	201	NOCOPY, mcheck_transfer_to_handler, \
	202	ret_from_mcheck_exc)
	203
	204	#define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \
	205	li r10,trap; \
	206	stw r10,_TRAP(r11); \
	207	lis r10,msr@h; \
	208	ori r10,r10,msr@l; \
	209	copyee(r10, r9); \
	210	bl tfer; \
	211	.long hdlr; \
	212	.long ret
	213
	214	#define COPY_EE(d, s) rlwimi d,s,0,16,16
	215	#define NOCOPY(d, s)
	216
	217	#define EXC_XFER_STD(n, hdlr) \
	218	EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \
	219	ret_from_except_full)
	220
	221	#define EXC_XFER_LITE(n, hdlr) \
	222	EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \
	223	ret_from_except)
	224
	225	#define EXC_XFER_EE(n, hdlr) \
	226	EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \
	227	ret_from_except_full)
	228
	229	#define EXC_XFER_EE_LITE(n, hdlr) \
	230	EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \
	231	ret_from_except)
	232
	233	/* Check for a single step debug exception while in an exception
	234	* handler before state has been saved. This is to catch the case
	235	* where an instruction that we are trying to single step causes
	236	* an exception (eg ITLB/DTLB miss) and thus the first instruction of
	237	* the exception handler generates a single step debug exception.
	238	*
	239	* If we get a debug trap on the first instruction of an exception handler,
	240	* we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
	241	* a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
	242	* The exception handler was handling a non-critical interrupt, so it will
	243	* save (and later restore) the MSR via SPRN_CSRR1, which will still have
	244	* the MSR_DE bit set.
	245	*/
eb0cd5fd KG	246	#define DEBUG_DEBUG_EXCEPTION \
eb0cd5fd KG	247	START_EXCEPTION(DebugDebug); \
63dafe57 BB	248	DEBUG_EXCEPTION_PROLOG; \
	249	\
	250	/* \
	251	* If there is a single step or branch-taken exception in an \
	252	* exception entry sequence, it was probably meant to apply to \
	253	* the code where the exception occurred (since exception entry \
	254	* doesn't turn off DE automatically). We simulate the effect \
	255	* of turning off DE on entry to an exception handler by turning \
fec6a822	256	* off DE in the DSRR1 value and clearing the debug status. \
63dafe57 BB	257	*/ \
	258	mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
	259	andis. r10,r10,DBSR_IC@h; \
	260	beq+ 2f; \
	261	\
	262	lis r10,KERNELBASE@h; /* check if exception in vectors */ \
	263	ori r10,r10,KERNELBASE@l; \
	264	cmplw r12,r10; \
	265	blt+ 2f; /* addr below exception vectors */ \
	266	\
eb0cd5fd KG	267	lis r10,DebugDebug@h; \
eb0cd5fd KG	268	ori r10,r10,DebugDebug@l; \
63dafe57 BB	269	cmplw r12,r10; \
	270	bgt+ 2f; /* addr above exception vectors */ \
	271	\
	272	/* here it looks like we got an inappropriate debug exception. */ \
	273	1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CDRR1 value */ \
	274	lis r10,DBSR_IC@h; /* clear the IC event */ \
	275	mtspr SPRN_DBSR,r10; \
	276	/* restore state and get out */ \
	277	lwz r10,_CCR(r11); \
	278	lwz r0,GPR0(r11); \
	279	lwz r1,GPR1(r11); \
	280	mtcrf 0x80,r10; \
	281	mtspr SPRN_DSRR0,r12; \
	282	mtspr SPRN_DSRR1,r9; \
	283	lwz r9,GPR9(r11); \
	284	lwz r12,GPR12(r11); \
	285	mtspr DEBUG_SPRG,r8; \
	286	BOOKE_LOAD_EXC_LEVEL_STACK(DEBUG); /* r8 points to the debug stack */ \
369e757b KG	287	lwz r10,GPR10(r8); \
369e757b KG	288	lwz r11,GPR11(r8); \
63dafe57 BB	289	mfspr r8,DEBUG_SPRG; \
63dafe57 BB	290	\
16c57b36	291	PPC_RFDI; \
63dafe57 BB	292	b .; \
63dafe57 BB	293	\
fec6a822	294	/* continue normal handling for a debug exception... */ \
63dafe57 BB	295	2: mfspr r4,SPRN_DBSR; \
63dafe57 BB	296	addi r3,r1,STACK_FRAME_OVERHEAD; \
663276b7	297	EXC_XFER_TEMPLATE(DebugException, 0x2008, (MSR_KERNEL & ~(MSR_ME\|MSR_DE\|MSR_CE)), NOCOPY, debug_transfer_to_handler, ret_from_debug_exc)
eb0cd5fd KG	298
	299	#define DEBUG_CRIT_EXCEPTION \
	300	START_EXCEPTION(DebugCrit); \
63dafe57 BB	301	CRITICAL_EXCEPTION_PROLOG; \
	302	\
	303	/* \
	304	* If there is a single step or branch-taken exception in an \
	305	* exception entry sequence, it was probably meant to apply to \
	306	* the code where the exception occurred (since exception entry \
	307	* doesn't turn off DE automatically). We simulate the effect \
	308	* of turning off DE on entry to an exception handler by turning \
	309	* off DE in the CSRR1 value and clearing the debug status. \
	310	*/ \
	311	mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
	312	andis. r10,r10,DBSR_IC@h; \
	313	beq+ 2f; \
	314	\
	315	lis r10,KERNELBASE@h; /* check if exception in vectors */ \
	316	ori r10,r10,KERNELBASE@l; \
	317	cmplw r12,r10; \
	318	blt+ 2f; /* addr below exception vectors */ \
	319	\
eb0cd5fd KG	320	lis r10,DebugCrit@h; \
eb0cd5fd KG	321	ori r10,r10,DebugCrit@l; \
63dafe57 BB	322	cmplw r12,r10; \
	323	bgt+ 2f; /* addr above exception vectors */ \
	324	\
	325	/* here it looks like we got an inappropriate debug exception. */ \
	326	1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CSRR1 value */ \
	327	lis r10,DBSR_IC@h; /* clear the IC event */ \
	328	mtspr SPRN_DBSR,r10; \
	329	/* restore state and get out */ \
	330	lwz r10,_CCR(r11); \
	331	lwz r0,GPR0(r11); \
	332	lwz r1,GPR1(r11); \
	333	mtcrf 0x80,r10; \
	334	mtspr SPRN_CSRR0,r12; \
	335	mtspr SPRN_CSRR1,r9; \
	336	lwz r9,GPR9(r11); \
	337	lwz r12,GPR12(r11); \
	338	mtspr CRIT_SPRG,r8; \
	339	BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */ \
369e757b KG	340	lwz r10,GPR10(r8); \
369e757b KG	341	lwz r11,GPR11(r8); \
63dafe57 BB	342	mfspr r8,CRIT_SPRG; \
	343	\
	344	rfci; \
	345	b .; \
	346	\
	347	/* continue normal handling for a critical exception... */ \
	348	2: mfspr r4,SPRN_DBSR; \
	349	addi r3,r1,STACK_FRAME_OVERHEAD; \
	350	EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME\|MSR_DE\|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)
63dafe57	351
1bc54c03 BH	352	#define DATA_STORAGE_EXCEPTION \
	353	START_EXCEPTION(DataStorage) \
	354	NORMAL_EXCEPTION_PROLOG; \
	355	mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \
	356	stw r5,_ESR(r11); \
	357	mfspr r4,SPRN_DEAR; /* Grab the DEAR */ \
	358	EXC_XFER_EE_LITE(0x0300, handle_page_fault)
	359
63dafe57 BB	360	#define INSTRUCTION_STORAGE_EXCEPTION \
	361	START_EXCEPTION(InstructionStorage) \
	362	NORMAL_EXCEPTION_PROLOG; \
	363	mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \
	364	stw r5,_ESR(r11); \
	365	mr r4,r12; /* Pass SRR0 as arg2 */ \
	366	li r5,0; /* Pass zero as arg3 */ \
	367	EXC_XFER_EE_LITE(0x0400, handle_page_fault)
	368
	369	#define ALIGNMENT_EXCEPTION \
	370	START_EXCEPTION(Alignment) \
	371	NORMAL_EXCEPTION_PROLOG; \
	372	mfspr r4,SPRN_DEAR; /* Grab the DEAR and save it */ \
	373	stw r4,_DEAR(r11); \
	374	addi r3,r1,STACK_FRAME_OVERHEAD; \
	375	EXC_XFER_EE(0x0600, alignment_exception)
	376
	377	#define PROGRAM_EXCEPTION \
	378	START_EXCEPTION(Program) \
	379	NORMAL_EXCEPTION_PROLOG; \
	380	mfspr r4,SPRN_ESR; /* Grab the ESR and save it */ \
	381	stw r4,_ESR(r11); \
	382	addi r3,r1,STACK_FRAME_OVERHEAD; \
	383	EXC_XFER_STD(0x0700, program_check_exception)
	384
	385	#define DECREMENTER_EXCEPTION \
	386	START_EXCEPTION(Decrementer) \
	387	NORMAL_EXCEPTION_PROLOG; \
	388	lis r0,TSR_DIS@h; /* Setup the DEC interrupt mask */ \
	389	mtspr SPRN_TSR,r0; /* Clear the DEC interrupt */ \
	390	addi r3,r1,STACK_FRAME_OVERHEAD; \
	391	EXC_XFER_LITE(0x0900, timer_interrupt)
	392
	393	#define FP_UNAVAILABLE_EXCEPTION \
	394	START_EXCEPTION(FloatingPointUnavailable) \
	395	NORMAL_EXCEPTION_PROLOG; \
6f3d8e69 MN	396	beq 1f; \
	397	bl load_up_fpu; /* if from user, just load it up */ \
	398	b fast_exception_return; \
	399	1: addi r3,r1,STACK_FRAME_OVERHEAD; \
66f2d025	400	EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)
63dafe57	401
fca622c5 KG	402	#ifndef __ASSEMBLY__
	403	struct exception_regs {
	404	unsigned long mas0;
	405	unsigned long mas1;
	406	unsigned long mas2;
	407	unsigned long mas3;
	408	unsigned long mas6;
	409	unsigned long mas7;
	410	unsigned long srr0;
	411	unsigned long srr1;
	412	unsigned long csrr0;
	413	unsigned long csrr1;
	414	unsigned long dsrr0;
	415	unsigned long dsrr1;
	416	unsigned long saved_ksp_limit;
	417	};
	418
	419	/* ensure this structure is always sized to a multiple of the stack alignment */
	420	#define STACK_EXC_LVL_FRAME_SIZE _ALIGN_UP(sizeof (struct exception_regs), 16)
	421
	422	#endif /* __ASSEMBLY__ */
63dafe57	423	#endif /* __HEAD_BOOKE_H__ */