[deliverable/linux.git] / arch / powerpc / kernel / head_booke.h

#ifndef __HEAD_BOOKE_H__
#define __HEAD_BOOKE_H__

/*
 * Macros used for common Book-e exception handling
 */

#define SET_IVOR(vector_number, vector_label)		\
		li	r26,vector_label@l; 		\
		mtspr	SPRN_IVOR##vector_number,r26;	\
		sync

#define NORMAL_EXCEPTION_PROLOG						     \
	mtspr	SPRN_SPRG0,r10;		/* save two registers to work with */\
	mtspr	SPRN_SPRG1,r11;						     \
	mtspr	SPRN_SPRG4W,r1;						     \
	mfcr	r10;			/* save CR in r10 for now	   */\
	mfspr	r11,SPRN_SRR1;		/* check whether user or kernel    */\
	andi.	r11,r11,MSR_PR;						     \
	beq	1f;							     \
	mfspr	r1,SPRN_SPRG3;		/* if from user, start at top of   */\
	lwz	r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack   */\
	addi	r1,r1,THREAD_SIZE;					     \
1:	subi	r1,r1,INT_FRAME_SIZE;	/* Allocate an exception frame     */\
	mr	r11,r1;							     \
	stw	r10,_CCR(r11);          /* save various registers	   */\
	stw	r12,GPR12(r11);						     \
	stw	r9,GPR9(r11);						     \
	mfspr	r10,SPRN_SPRG0;						     \
	stw	r10,GPR10(r11);						     \
	mfspr	r12,SPRN_SPRG1;						     \
	stw	r12,GPR11(r11);						     \
	mflr	r10;							     \
	stw	r10,_LINK(r11);						     \
	mfspr	r10,SPRN_SPRG4R;					     \
	mfspr	r12,SPRN_SRR0;						     \
	stw	r10,GPR1(r11);						     \
	mfspr	r9,SPRN_SRR1;						     \
	stw	r10,0(r11);						     \
	rlwinm	r9,r9,0,14,12;		/* clear MSR_WE (necessary?)	   */\
	stw	r0,GPR0(r11);						     \
	SAVE_4GPRS(3, r11);						     \
	SAVE_2GPRS(7, r11)

/* To handle the additional exception priority levels on 40x and Book-E
 * processors we allocate a stack per additional priority level.
 *
 * On 40x critical is the only additional level
 * On 44x/e500 we have critical and machine check
 * On e200 we have critical and debug (machine check occurs via critical)
 *
 * Additionally we reserve a SPRG for each priority level so we can free up a
 * GPR to use as the base for indirect access to the exception stacks.  This
 * is necessary since the MMU is always on, for Book-E parts, and the stacks
 * are offset from KERNELBASE.
 *
 * There is some space optimization to be had here if desired.  However
 * to allow for a common kernel with support for debug exceptions either
 * going to critical or their own debug level we aren't currently
 * providing configurations that micro-optimize space usage.
 */

/* CRIT_SPRG only used in critical exception handling */
#define CRIT_SPRG	SPRN_SPRG2
/* MCHECK_SPRG only used in machine check exception handling */
#define MCHECK_SPRG	SPRN_SPRG6W

#define MCHECK_STACK_BASE	mcheckirq_ctx
#define CRIT_STACK_BASE		critirq_ctx

/* only on e200 for now */
#define DEBUG_STACK_BASE	dbgirq_ctx
#define DEBUG_SPRG		SPRN_SPRG6W

#define EXC_LVL_FRAME_OVERHEAD	(THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE)

#ifdef CONFIG_SMP
#define BOOKE_LOAD_EXC_LEVEL_STACK(level)		\
	mfspr	r8,SPRN_PIR;				\
	slwi	r8,r8,2;				\
	addis	r8,r8,level##_STACK_BASE@ha;		\
	lwz	r8,level##_STACK_BASE@l(r8);		\
	addi	r8,r8,EXC_LVL_FRAME_OVERHEAD;
#else
#define BOOKE_LOAD_EXC_LEVEL_STACK(level)		\
	lis	r8,level##_STACK_BASE@ha;		\
	lwz	r8,level##_STACK_BASE@l(r8);		\
	addi	r8,r8,EXC_LVL_FRAME_OVERHEAD;
#endif

/*
 * Exception prolog for critical/machine check exceptions.  This is a
 * little different from the normal exception prolog above since a
 * critical/machine check exception can potentially occur at any point
 * during normal exception processing. Thus we cannot use the same SPRG
 * registers as the normal prolog above. Instead we use a portion of the
 * critical/machine check exception stack at low physical addresses.
 */
#define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, exc_level_srr0, exc_level_srr1) \
	mtspr	exc_level##_SPRG,r8;					     \
	BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \
	stw	r9,GPR9(r8);		/* save various registers	   */\
	mfcr	r9;			/* save CR in r9 for now	   */\
	stw	r10,GPR10(r8);						     \
	stw	r11,GPR11(r8);						     \
	stw	r9,_CCR(r8);		/* save CR on stack		   */\
	mfspr	r10,exc_level_srr1;	/* check whether user or kernel    */\
	andi.	r10,r10,MSR_PR;						     \
	mfspr	r11,SPRN_SPRG3;		/* if from user, start at top of   */\
	lwz	r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
	addi	r11,r11,EXC_LVL_FRAME_OVERHEAD;	/* allocate stack frame    */\
	beq	1f;							     \
	/* COMING FROM USER MODE */					     \
	stw	r9,_CCR(r11);		/* save CR			   */\
	lwz	r10,GPR10(r8);		/* copy regs from exception stack  */\
	lwz	r9,GPR9(r8);						     \
	stw	r10,GPR10(r11);						     \
	lwz	r10,GPR11(r8);						     \
	stw	r9,GPR9(r11);						     \
	stw	r10,GPR11(r11);						     \
	b	2f;							     \
	/* COMING FROM PRIV MODE */					     \
1:	lwz	r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r11);		     \
	lwz	r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r11);		     \
	stw	r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r8);			     \
	stw	r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r8);		     \
	lwz	r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r11);			     \
	stw	r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r8);			     \
	mr	r11,r8;							     \
2:	mfspr	r8,exc_level##_SPRG;					     \
	stw	r12,GPR12(r11);		/* save various registers	   */\
	mflr	r10;							     \
	stw	r10,_LINK(r11);						     \
	mfspr	r12,SPRN_DEAR;		/* save DEAR and ESR in the frame  */\
	stw	r12,_DEAR(r11);		/* since they may have had stuff   */\
	mfspr	r9,SPRN_ESR;		/* in them at the point where the  */\
	stw	r9,_ESR(r11);		/* exception was taken		   */\
	mfspr	r12,exc_level_srr0;					     \
	stw	r1,GPR1(r11);						     \
	mfspr	r9,exc_level_srr1;					     \
	stw	r1,0(r11);						     \
	mr	r1,r11;							     \
	rlwinm	r9,r9,0,14,12;		/* clear MSR_WE (necessary?)	   */\
	stw	r0,GPR0(r11);						     \
	SAVE_4GPRS(3, r11);						     \
	SAVE_2GPRS(7, r11)

#define CRITICAL_EXCEPTION_PROLOG \
		EXC_LEVEL_EXCEPTION_PROLOG(CRIT, SPRN_CSRR0, SPRN_CSRR1)
#define DEBUG_EXCEPTION_PROLOG \
		EXC_LEVEL_EXCEPTION_PROLOG(DEBUG, SPRN_DSRR0, SPRN_DSRR1)
#define MCHECK_EXCEPTION_PROLOG \
		EXC_LEVEL_EXCEPTION_PROLOG(MCHECK, SPRN_MCSRR0, SPRN_MCSRR1)

/*
 * Exception vectors.
 */
#define	START_EXCEPTION(label)						     \
        .align 5;              						     \
label:

#define FINISH_EXCEPTION(func)					\
	bl	transfer_to_handler_full;			\
	.long	func;						\
	.long	ret_from_except_full

#define EXCEPTION(n, label, hdlr, xfer)				\
	START_EXCEPTION(label);					\
	NORMAL_EXCEPTION_PROLOG;				\
	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
	xfer(n, hdlr)

#define CRITICAL_EXCEPTION(n, label, hdlr)			\
	START_EXCEPTION(label);					\
	CRITICAL_EXCEPTION_PROLOG;				\
	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
	EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
			  NOCOPY, crit_transfer_to_handler, \
			  ret_from_crit_exc)

#define MCHECK_EXCEPTION(n, label, hdlr)			\
	START_EXCEPTION(label);					\
	MCHECK_EXCEPTION_PROLOG;				\
	mfspr	r5,SPRN_ESR;					\
	stw	r5,_ESR(r11);					\
	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
	EXC_XFER_TEMPLATE(hdlr, n+4, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
			  NOCOPY, mcheck_transfer_to_handler,   \
			  ret_from_mcheck_exc)

#define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret)	\
	li	r10,trap;					\
	stw	r10,_TRAP(r11);					\
	lis	r10,msr@h;					\
	ori	r10,r10,msr@l;					\
	copyee(r10, r9);					\
	bl	tfer;		 				\
	.long	hdlr;						\
	.long	ret

#define COPY_EE(d, s)		rlwimi d,s,0,16,16
#define NOCOPY(d, s)

#define EXC_XFER_STD(n, hdlr)		\
	EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \
			  ret_from_except_full)

#define EXC_XFER_LITE(n, hdlr)		\
	EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \
			  ret_from_except)

#define EXC_XFER_EE(n, hdlr)		\
	EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \
			  ret_from_except_full)

#define EXC_XFER_EE_LITE(n, hdlr)	\
	EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \
			  ret_from_except)

/* Check for a single step debug exception while in an exception
 * handler before state has been saved.  This is to catch the case
 * where an instruction that we are trying to single step causes
 * an exception (eg ITLB/DTLB miss) and thus the first instruction of
 * the exception handler generates a single step debug exception.
 *
 * If we get a debug trap on the first instruction of an exception handler,
 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
 * The exception handler was handling a non-critical interrupt, so it will
 * save (and later restore) the MSR via SPRN_CSRR1, which will still have
 * the MSR_DE bit set.
 */
#define DEBUG_DEBUG_EXCEPTION						      \
	START_EXCEPTION(DebugDebug);					      \
	DEBUG_EXCEPTION_PROLOG;						      \
									      \
	/*								      \
	 * If there is a single step or branch-taken exception in an	      \
	 * exception entry sequence, it was probably meant to apply to	      \
	 * the code where the exception occurred (since exception entry	      \
	 * doesn't turn off DE automatically).  We simulate the effect	      \
	 * of turning off DE on entry to an exception handler by turning      \
	 * off DE in the CSRR1 value and clearing the debug status.	      \
	 */								      \
	mfspr	r10,SPRN_DBSR;		/* check single-step/branch taken */  \
	andis.	r10,r10,DBSR_IC@h;					      \
	beq+	2f;							      \
									      \
	lis	r10,KERNELBASE@h;	/* check if exception in vectors */   \
	ori	r10,r10,KERNELBASE@l;					      \
	cmplw	r12,r10;						      \
	blt+	2f;			/* addr below exception vectors */    \
									      \
	lis	r10,DebugDebug@h;					      \
	ori	r10,r10,DebugDebug@l;					      \
	cmplw	r12,r10;						      \
	bgt+	2f;			/* addr above exception vectors */    \
									      \
	/* here it looks like we got an inappropriate debug exception. */     \
1:	rlwinm	r9,r9,0,~MSR_DE;	/* clear DE in the CDRR1 value */     \
	lis	r10,DBSR_IC@h;		/* clear the IC event */	      \
	mtspr	SPRN_DBSR,r10;						      \
	/* restore state and get out */					      \
	lwz	r10,_CCR(r11);						      \
	lwz	r0,GPR0(r11);						      \
	lwz	r1,GPR1(r11);						      \
	mtcrf	0x80,r10;						      \
	mtspr	SPRN_DSRR0,r12;						      \
	mtspr	SPRN_DSRR1,r9;						      \
	lwz	r9,GPR9(r11);						      \
	lwz	r12,GPR12(r11);						      \
	mtspr	DEBUG_SPRG,r8;						      \
	BOOKE_LOAD_EXC_LEVEL_STACK(DEBUG); /* r8 points to the debug stack */ \
	lwz	r10,GPR10(r8);						      \
	lwz	r11,GPR11(r8);						      \
	mfspr	r8,DEBUG_SPRG;						      \
									      \
	RFDI;								      \
	b	.;							      \
									      \
	/* continue normal handling for a critical exception... */	      \
2:	mfspr	r4,SPRN_DBSR;						      \
	addi	r3,r1,STACK_FRAME_OVERHEAD;				      \
	EXC_XFER_TEMPLATE(DebugException, 0x2008, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, debug_transfer_to_handler, ret_from_debug_exc)

#define DEBUG_CRIT_EXCEPTION						      \
	START_EXCEPTION(DebugCrit);					      \
	CRITICAL_EXCEPTION_PROLOG;					      \
									      \
	/*								      \
	 * If there is a single step or branch-taken exception in an	      \
	 * exception entry sequence, it was probably meant to apply to	      \
	 * the code where the exception occurred (since exception entry	      \
	 * doesn't turn off DE automatically).  We simulate the effect	      \
	 * of turning off DE on entry to an exception handler by turning      \
	 * off DE in the CSRR1 value and clearing the debug status.	      \
	 */								      \
	mfspr	r10,SPRN_DBSR;		/* check single-step/branch taken */  \
	andis.	r10,r10,DBSR_IC@h;					      \
	beq+	2f;							      \
									      \
	lis	r10,KERNELBASE@h;	/* check if exception in vectors */   \
	ori	r10,r10,KERNELBASE@l;					      \
	cmplw	r12,r10;						      \
	blt+	2f;			/* addr below exception vectors */    \
									      \
	lis	r10,DebugCrit@h;						      \
	ori	r10,r10,DebugCrit@l;					      \
	cmplw	r12,r10;						      \
	bgt+	2f;			/* addr above exception vectors */    \
									      \
	/* here it looks like we got an inappropriate debug exception. */     \
1:	rlwinm	r9,r9,0,~MSR_DE;	/* clear DE in the CSRR1 value */     \
	lis	r10,DBSR_IC@h;		/* clear the IC event */	      \
	mtspr	SPRN_DBSR,r10;						      \
	/* restore state and get out */					      \
	lwz	r10,_CCR(r11);						      \
	lwz	r0,GPR0(r11);						      \
	lwz	r1,GPR1(r11);						      \
	mtcrf	0x80,r10;						      \
	mtspr	SPRN_CSRR0,r12;						      \
	mtspr	SPRN_CSRR1,r9;						      \
	lwz	r9,GPR9(r11);						      \
	lwz	r12,GPR12(r11);						      \
	mtspr	CRIT_SPRG,r8;						      \
	BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */  \
	lwz	r10,GPR10(r8);						      \
	lwz	r11,GPR11(r8);						      \
	mfspr	r8,CRIT_SPRG;						      \
									      \
	rfci;								      \
	b	.;							      \
									      \
	/* continue normal handling for a critical exception... */	      \
2:	mfspr	r4,SPRN_DBSR;						      \
	addi	r3,r1,STACK_FRAME_OVERHEAD;				      \
	EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)

#define INSTRUCTION_STORAGE_EXCEPTION					      \
	START_EXCEPTION(InstructionStorage)				      \
	NORMAL_EXCEPTION_PROLOG;					      \
	mfspr	r5,SPRN_ESR;		/* Grab the ESR and save it */	      \
	stw	r5,_ESR(r11);						      \
	mr      r4,r12;                 /* Pass SRR0 as arg2 */		      \
	li      r5,0;                   /* Pass zero as arg3 */		      \
	EXC_XFER_EE_LITE(0x0400, handle_page_fault)

#define ALIGNMENT_EXCEPTION						      \
	START_EXCEPTION(Alignment)					      \
	NORMAL_EXCEPTION_PROLOG;					      \
	mfspr   r4,SPRN_DEAR;           /* Grab the DEAR and save it */	      \
	stw     r4,_DEAR(r11);						      \
	addi    r3,r1,STACK_FRAME_OVERHEAD;				      \
	EXC_XFER_EE(0x0600, alignment_exception)

#define PROGRAM_EXCEPTION						      \
	START_EXCEPTION(Program)					      \
	NORMAL_EXCEPTION_PROLOG;					      \
	mfspr	r4,SPRN_ESR;		/* Grab the ESR and save it */	      \
	stw	r4,_ESR(r11);						      \
	addi	r3,r1,STACK_FRAME_OVERHEAD;				      \
	EXC_XFER_STD(0x0700, program_check_exception)

#define DECREMENTER_EXCEPTION						      \
	START_EXCEPTION(Decrementer)					      \
	NORMAL_EXCEPTION_PROLOG;					      \
	lis     r0,TSR_DIS@h;           /* Setup the DEC interrupt mask */    \
	mtspr   SPRN_TSR,r0;		/* Clear the DEC interrupt */	      \
	addi    r3,r1,STACK_FRAME_OVERHEAD;				      \
	EXC_XFER_LITE(0x0900, timer_interrupt)

#define FP_UNAVAILABLE_EXCEPTION					      \
	START_EXCEPTION(FloatingPointUnavailable)			      \
	NORMAL_EXCEPTION_PROLOG;					      \
	bne	load_up_fpu;		/* if from user, just load it up */   \
	addi	r3,r1,STACK_FRAME_OVERHEAD;				      \
	EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)

#ifndef __ASSEMBLY__
struct exception_regs {
	unsigned long mas0;
	unsigned long mas1;
	unsigned long mas2;
	unsigned long mas3;
	unsigned long mas6;
	unsigned long mas7;
	unsigned long srr0;
	unsigned long srr1;
	unsigned long csrr0;
	unsigned long csrr1;
	unsigned long dsrr0;
	unsigned long dsrr1;
	unsigned long saved_ksp_limit;
};

/* ensure this structure is always sized to a multiple of the stack alignment */
#define STACK_EXC_LVL_FRAME_SIZE	_ALIGN_UP(sizeof (struct exception_regs), 16)

#endif /* __ASSEMBLY__ */
#endif /* __HEAD_BOOKE_H__ */
Commit	Line	Data
63dafe57 BB	1	#ifndef __HEAD_BOOKE_H__
	2	#define __HEAD_BOOKE_H__
	3
	4	/*
	5	* Macros used for common Book-e exception handling
	6	*/
	7
	8	#define SET_IVOR(vector_number, vector_label) \
	9	li r26,vector_label@l; \
	10	mtspr SPRN_IVOR##vector_number,r26; \
	11	sync
	12
	13	#define NORMAL_EXCEPTION_PROLOG \
	14	mtspr SPRN_SPRG0,r10; /* save two registers to work with */\
	15	mtspr SPRN_SPRG1,r11; \
	16	mtspr SPRN_SPRG4W,r1; \
	17	mfcr r10; /* save CR in r10 for now */\
	18	mfspr r11,SPRN_SRR1; /* check whether user or kernel */\
	19	andi. r11,r11,MSR_PR; \
	20	beq 1f; \
	21	mfspr r1,SPRN_SPRG3; /* if from user, start at top of */\
	22	lwz r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack */\
	23	addi r1,r1,THREAD_SIZE; \
	24	1: subi r1,r1,INT_FRAME_SIZE; /* Allocate an exception frame */\
	25	mr r11,r1; \
	26	stw r10,_CCR(r11); /* save various registers */\
	27	stw r12,GPR12(r11); \
	28	stw r9,GPR9(r11); \
	29	mfspr r10,SPRN_SPRG0; \
	30	stw r10,GPR10(r11); \
	31	mfspr r12,SPRN_SPRG1; \
	32	stw r12,GPR11(r11); \
	33	mflr r10; \
	34	stw r10,_LINK(r11); \
	35	mfspr r10,SPRN_SPRG4R; \
	36	mfspr r12,SPRN_SRR0; \
	37	stw r10,GPR1(r11); \
	38	mfspr r9,SPRN_SRR1; \
	39	stw r10,0(r11); \
	40	rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
	41	stw r0,GPR0(r11); \
	42	SAVE_4GPRS(3, r11); \
	43	SAVE_2GPRS(7, r11)
	44
	45	/* To handle the additional exception priority levels on 40x and Book-E
bcf0b088	46	* processors we allocate a stack per additional priority level.
63dafe57 BB	47	*
	48	* On 40x critical is the only additional level
	49	* On 44x/e500 we have critical and machine check
	50	* On e200 we have critical and debug (machine check occurs via critical)
	51	*
	52	* Additionally we reserve a SPRG for each priority level so we can free up a
	53	* GPR to use as the base for indirect access to the exception stacks. This
	54	* is necessary since the MMU is always on, for Book-E parts, and the stacks
	55	* are offset from KERNELBASE.
	56	*
eb0cd5fd KG	57	* There is some space optimization to be had here if desired. However
	58	* to allow for a common kernel with support for debug exceptions either
	59	* going to critical or their own debug level we aren't currently
	60	* providing configurations that micro-optimize space usage.
63dafe57	61	*/
63dafe57 BB	62
	63	/* CRIT_SPRG only used in critical exception handling */
	64	#define CRIT_SPRG SPRN_SPRG2
	65	/* MCHECK_SPRG only used in machine check exception handling */
	66	#define MCHECK_SPRG SPRN_SPRG6W
	67
bcf0b088 KG	68	#define MCHECK_STACK_BASE mcheckirq_ctx
bcf0b088 KG	69	#define CRIT_STACK_BASE critirq_ctx
63dafe57 BB	70
63dafe57 BB	71	/* only on e200 for now */
bcf0b088	72	#define DEBUG_STACK_BASE dbgirq_ctx
63dafe57 BB	73	#define DEBUG_SPRG SPRN_SPRG6W
63dafe57 BB	74
fca622c5	75	#define EXC_LVL_FRAME_OVERHEAD (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE)
369e757b	76
63dafe57 BB	77	#ifdef CONFIG_SMP
	78	#define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
	79	mfspr r8,SPRN_PIR; \
bcf0b088 KG	80	slwi r8,r8,2; \
	81	addis r8,r8,level##_STACK_BASE@ha; \
	82	lwz r8,level##_STACK_BASE@l(r8); \
369e757b	83	addi r8,r8,EXC_LVL_FRAME_OVERHEAD;
63dafe57 BB	84	#else
63dafe57 BB	85	#define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
bcf0b088 KG	86	lis r8,level##_STACK_BASE@ha; \
bcf0b088 KG	87	lwz r8,level##_STACK_BASE@l(r8); \
369e757b	88	addi r8,r8,EXC_LVL_FRAME_OVERHEAD;
63dafe57 BB	89	#endif
	90
	91	/*
	92	* Exception prolog for critical/machine check exceptions. This is a
	93	* little different from the normal exception prolog above since a
	94	* critical/machine check exception can potentially occur at any point
	95	* during normal exception processing. Thus we cannot use the same SPRG
	96	* registers as the normal prolog above. Instead we use a portion of the
	97	* critical/machine check exception stack at low physical addresses.
	98	*/
	99	#define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, exc_level_srr0, exc_level_srr1) \
	100	mtspr exc_level##_SPRG,r8; \
	101	BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \
369e757b KG	102	stw r9,GPR9(r8); /* save various registers */\
	103	mfcr r9; /* save CR in r9 for now */\
	104	stw r10,GPR10(r8); \
	105	stw r11,GPR11(r8); \
	106	stw r9,_CCR(r8); /* save CR on stack */\
	107	mfspr r10,exc_level_srr1; /* check whether user or kernel */\
	108	andi. r10,r10,MSR_PR; \
63dafe57 BB	109	mfspr r11,SPRN_SPRG3; /* if from user, start at top of */\
63dafe57 BB	110	lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
369e757b KG	111	addi r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame */\
	112	beq 1f; \
	113	/* COMING FROM USER MODE */ \
	114	stw r9,_CCR(r11); /* save CR */\
	115	lwz r10,GPR10(r8); /* copy regs from exception stack */\
	116	lwz r9,GPR9(r8); \
	117	stw r10,GPR10(r11); \
	118	lwz r10,GPR11(r8); \
63dafe57	119	stw r9,GPR9(r11); \
369e757b KG	120	stw r10,GPR11(r11); \
	121	b 2f; \
	122	/* COMING FROM PRIV MODE */ \
	123	1: lwz r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r11); \
	124	lwz r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r11); \
	125	stw r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r8); \
	126	stw r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r8); \
	127	lwz r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r11); \
	128	stw r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r8); \
	129	mr r11,r8; \
	130	2: mfspr r8,exc_level##_SPRG; \
	131	stw r12,GPR12(r11); /* save various registers */\
63dafe57 BB	132	mflr r10; \
	133	stw r10,_LINK(r11); \
	134	mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\
	135	stw r12,_DEAR(r11); /* since they may have had stuff */\
	136	mfspr r9,SPRN_ESR; /* in them at the point where the */\
	137	stw r9,_ESR(r11); /* exception was taken */\
	138	mfspr r12,exc_level_srr0; \
	139	stw r1,GPR1(r11); \
	140	mfspr r9,exc_level_srr1; \
	141	stw r1,0(r11); \
	142	mr r1,r11; \
	143	rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
	144	stw r0,GPR0(r11); \
	145	SAVE_4GPRS(3, r11); \
	146	SAVE_2GPRS(7, r11)
	147
	148	#define CRITICAL_EXCEPTION_PROLOG \
	149	EXC_LEVEL_EXCEPTION_PROLOG(CRIT, SPRN_CSRR0, SPRN_CSRR1)
	150	#define DEBUG_EXCEPTION_PROLOG \
	151	EXC_LEVEL_EXCEPTION_PROLOG(DEBUG, SPRN_DSRR0, SPRN_DSRR1)
	152	#define MCHECK_EXCEPTION_PROLOG \
	153	EXC_LEVEL_EXCEPTION_PROLOG(MCHECK, SPRN_MCSRR0, SPRN_MCSRR1)
	154
	155	/*
	156	* Exception vectors.
	157	*/
	158	#define START_EXCEPTION(label) \
	159	.align 5; \
	160	label:
	161
	162	#define FINISH_EXCEPTION(func) \
	163	bl transfer_to_handler_full; \
	164	.long func; \
	165	.long ret_from_except_full
	166
	167	#define EXCEPTION(n, label, hdlr, xfer) \
	168	START_EXCEPTION(label); \
	169	NORMAL_EXCEPTION_PROLOG; \
	170	addi r3,r1,STACK_FRAME_OVERHEAD; \
	171	xfer(n, hdlr)
	172
	173	#define CRITICAL_EXCEPTION(n, label, hdlr) \
	174	START_EXCEPTION(label); \
	175	CRITICAL_EXCEPTION_PROLOG; \
	176	addi r3,r1,STACK_FRAME_OVERHEAD; \
	177	EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME\|MSR_DE\|MSR_CE)), \
	178	NOCOPY, crit_transfer_to_handler, \
	179	ret_from_crit_exc)
	180
	181	#define MCHECK_EXCEPTION(n, label, hdlr) \
	182	START_EXCEPTION(label); \
	183	MCHECK_EXCEPTION_PROLOG; \
	184	mfspr r5,SPRN_ESR; \
	185	stw r5,_ESR(r11); \
	186	addi r3,r1,STACK_FRAME_OVERHEAD; \
47c0bd1a	187	EXC_XFER_TEMPLATE(hdlr, n+4, (MSR_KERNEL & ~(MSR_ME\|MSR_DE\|MSR_CE)), \
63dafe57 BB	188	NOCOPY, mcheck_transfer_to_handler, \
	189	ret_from_mcheck_exc)
	190
	191	#define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \
	192	li r10,trap; \
	193	stw r10,_TRAP(r11); \
	194	lis r10,msr@h; \
	195	ori r10,r10,msr@l; \
	196	copyee(r10, r9); \
	197	bl tfer; \
	198	.long hdlr; \
	199	.long ret
	200
	201	#define COPY_EE(d, s) rlwimi d,s,0,16,16
	202	#define NOCOPY(d, s)
	203
	204	#define EXC_XFER_STD(n, hdlr) \
	205	EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \
	206	ret_from_except_full)
	207
	208	#define EXC_XFER_LITE(n, hdlr) \
	209	EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \
	210	ret_from_except)
	211
	212	#define EXC_XFER_EE(n, hdlr) \
	213	EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \
	214	ret_from_except_full)
	215
	216	#define EXC_XFER_EE_LITE(n, hdlr) \
	217	EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \
	218	ret_from_except)
	219
	220	/* Check for a single step debug exception while in an exception
	221	* handler before state has been saved. This is to catch the case
	222	* where an instruction that we are trying to single step causes
	223	* an exception (eg ITLB/DTLB miss) and thus the first instruction of
	224	* the exception handler generates a single step debug exception.
	225	*
	226	* If we get a debug trap on the first instruction of an exception handler,
	227	* we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
	228	* a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
	229	* The exception handler was handling a non-critical interrupt, so it will
	230	* save (and later restore) the MSR via SPRN_CSRR1, which will still have
	231	* the MSR_DE bit set.
	232	*/
eb0cd5fd KG	233	#define DEBUG_DEBUG_EXCEPTION \
eb0cd5fd KG	234	START_EXCEPTION(DebugDebug); \
63dafe57 BB	235	DEBUG_EXCEPTION_PROLOG; \
	236	\
	237	/* \
	238	* If there is a single step or branch-taken exception in an \
	239	* exception entry sequence, it was probably meant to apply to \
	240	* the code where the exception occurred (since exception entry \
	241	* doesn't turn off DE automatically). We simulate the effect \
	242	* of turning off DE on entry to an exception handler by turning \
	243	* off DE in the CSRR1 value and clearing the debug status. \
	244	*/ \
	245	mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
	246	andis. r10,r10,DBSR_IC@h; \
	247	beq+ 2f; \
	248	\
	249	lis r10,KERNELBASE@h; /* check if exception in vectors */ \
	250	ori r10,r10,KERNELBASE@l; \
	251	cmplw r12,r10; \
	252	blt+ 2f; /* addr below exception vectors */ \
	253	\
eb0cd5fd KG	254	lis r10,DebugDebug@h; \
eb0cd5fd KG	255	ori r10,r10,DebugDebug@l; \
63dafe57 BB	256	cmplw r12,r10; \
	257	bgt+ 2f; /* addr above exception vectors */ \
	258	\
	259	/* here it looks like we got an inappropriate debug exception. */ \
	260	1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CDRR1 value */ \
	261	lis r10,DBSR_IC@h; /* clear the IC event */ \
	262	mtspr SPRN_DBSR,r10; \
	263	/* restore state and get out */ \
	264	lwz r10,_CCR(r11); \
	265	lwz r0,GPR0(r11); \
	266	lwz r1,GPR1(r11); \
	267	mtcrf 0x80,r10; \
	268	mtspr SPRN_DSRR0,r12; \
	269	mtspr SPRN_DSRR1,r9; \
	270	lwz r9,GPR9(r11); \
	271	lwz r12,GPR12(r11); \
	272	mtspr DEBUG_SPRG,r8; \
	273	BOOKE_LOAD_EXC_LEVEL_STACK(DEBUG); /* r8 points to the debug stack */ \
369e757b KG	274	lwz r10,GPR10(r8); \
369e757b KG	275	lwz r11,GPR11(r8); \
63dafe57 BB	276	mfspr r8,DEBUG_SPRG; \
	277	\
	278	RFDI; \
	279	b .; \
	280	\
	281	/* continue normal handling for a critical exception... */ \
	282	2: mfspr r4,SPRN_DBSR; \
	283	addi r3,r1,STACK_FRAME_OVERHEAD; \
663276b7	284	EXC_XFER_TEMPLATE(DebugException, 0x2008, (MSR_KERNEL & ~(MSR_ME\|MSR_DE\|MSR_CE)), NOCOPY, debug_transfer_to_handler, ret_from_debug_exc)
eb0cd5fd KG	285
	286	#define DEBUG_CRIT_EXCEPTION \
	287	START_EXCEPTION(DebugCrit); \
63dafe57 BB	288	CRITICAL_EXCEPTION_PROLOG; \
	289	\
	290	/* \
	291	* If there is a single step or branch-taken exception in an \
	292	* exception entry sequence, it was probably meant to apply to \
	293	* the code where the exception occurred (since exception entry \
	294	* doesn't turn off DE automatically). We simulate the effect \
	295	* of turning off DE on entry to an exception handler by turning \
	296	* off DE in the CSRR1 value and clearing the debug status. \
	297	*/ \
	298	mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
	299	andis. r10,r10,DBSR_IC@h; \
	300	beq+ 2f; \
	301	\
	302	lis r10,KERNELBASE@h; /* check if exception in vectors */ \
	303	ori r10,r10,KERNELBASE@l; \
	304	cmplw r12,r10; \
	305	blt+ 2f; /* addr below exception vectors */ \
	306	\
eb0cd5fd KG	307	lis r10,DebugCrit@h; \
eb0cd5fd KG	308	ori r10,r10,DebugCrit@l; \
63dafe57 BB	309	cmplw r12,r10; \
	310	bgt+ 2f; /* addr above exception vectors */ \
	311	\
	312	/* here it looks like we got an inappropriate debug exception. */ \
	313	1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CSRR1 value */ \
	314	lis r10,DBSR_IC@h; /* clear the IC event */ \
	315	mtspr SPRN_DBSR,r10; \
	316	/* restore state and get out */ \
	317	lwz r10,_CCR(r11); \
	318	lwz r0,GPR0(r11); \
	319	lwz r1,GPR1(r11); \
	320	mtcrf 0x80,r10; \
	321	mtspr SPRN_CSRR0,r12; \
	322	mtspr SPRN_CSRR1,r9; \
	323	lwz r9,GPR9(r11); \
	324	lwz r12,GPR12(r11); \
	325	mtspr CRIT_SPRG,r8; \
	326	BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */ \
369e757b KG	327	lwz r10,GPR10(r8); \
369e757b KG	328	lwz r11,GPR11(r8); \
63dafe57 BB	329	mfspr r8,CRIT_SPRG; \
	330	\
	331	rfci; \
	332	b .; \
	333	\
	334	/* continue normal handling for a critical exception... */ \
	335	2: mfspr r4,SPRN_DBSR; \
	336	addi r3,r1,STACK_FRAME_OVERHEAD; \
	337	EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME\|MSR_DE\|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)
63dafe57 BB	338
	339	#define INSTRUCTION_STORAGE_EXCEPTION \
	340	START_EXCEPTION(InstructionStorage) \
	341	NORMAL_EXCEPTION_PROLOG; \
	342	mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \
	343	stw r5,_ESR(r11); \
	344	mr r4,r12; /* Pass SRR0 as arg2 */ \
	345	li r5,0; /* Pass zero as arg3 */ \
	346	EXC_XFER_EE_LITE(0x0400, handle_page_fault)
	347
	348	#define ALIGNMENT_EXCEPTION \
	349	START_EXCEPTION(Alignment) \
	350	NORMAL_EXCEPTION_PROLOG; \
	351	mfspr r4,SPRN_DEAR; /* Grab the DEAR and save it */ \
	352	stw r4,_DEAR(r11); \
	353	addi r3,r1,STACK_FRAME_OVERHEAD; \
	354	EXC_XFER_EE(0x0600, alignment_exception)
	355
	356	#define PROGRAM_EXCEPTION \
	357	START_EXCEPTION(Program) \
	358	NORMAL_EXCEPTION_PROLOG; \
	359	mfspr r4,SPRN_ESR; /* Grab the ESR and save it */ \
	360	stw r4,_ESR(r11); \
	361	addi r3,r1,STACK_FRAME_OVERHEAD; \
	362	EXC_XFER_STD(0x0700, program_check_exception)
	363
	364	#define DECREMENTER_EXCEPTION \
	365	START_EXCEPTION(Decrementer) \
	366	NORMAL_EXCEPTION_PROLOG; \
	367	lis r0,TSR_DIS@h; /* Setup the DEC interrupt mask */ \
	368	mtspr SPRN_TSR,r0; /* Clear the DEC interrupt */ \
	369	addi r3,r1,STACK_FRAME_OVERHEAD; \
	370	EXC_XFER_LITE(0x0900, timer_interrupt)
	371
	372	#define FP_UNAVAILABLE_EXCEPTION \
	373	START_EXCEPTION(FloatingPointUnavailable) \
	374	NORMAL_EXCEPTION_PROLOG; \
	375	bne load_up_fpu; /* if from user, just load it up */ \
	376	addi r3,r1,STACK_FRAME_OVERHEAD; \
66f2d025	377	EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)
63dafe57	378
fca622c5 KG	379	#ifndef __ASSEMBLY__
	380	struct exception_regs {
	381	unsigned long mas0;
	382	unsigned long mas1;
	383	unsigned long mas2;
	384	unsigned long mas3;
	385	unsigned long mas6;
	386	unsigned long mas7;
	387	unsigned long srr0;
	388	unsigned long srr1;
	389	unsigned long csrr0;
	390	unsigned long csrr1;
	391	unsigned long dsrr0;
	392	unsigned long dsrr1;
	393	unsigned long saved_ksp_limit;
	394	};
	395
	396	/* ensure this structure is always sized to a multiple of the stack alignment */
	397	#define STACK_EXC_LVL_FRAME_SIZE _ALIGN_UP(sizeof (struct exception_regs), 16)
	398
	399	#endif /* __ASSEMBLY__ */
63dafe57	400	#endif /* __HEAD_BOOKE_H__ */