Commit | Line | Data |
---|---|---|
14cf11af | 1 | /* |
14cf11af PM |
2 | * Kernel execution entry point code. |
3 | * | |
4 | * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> | |
3c5df5c2 | 5 | * Initial PowerPC version. |
14cf11af | 6 | * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> |
3c5df5c2 | 7 | * Rewritten for PReP |
14cf11af | 8 | * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> |
3c5df5c2 | 9 | * Low-level exception handers, MMU support, and rewrite. |
14cf11af | 10 | * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> |
3c5df5c2 | 11 | * PowerPC 8xx modifications. |
14cf11af | 12 | * Copyright (c) 1998-1999 TiVo, Inc. |
3c5df5c2 | 13 | * PowerPC 403GCX modifications. |
14cf11af | 14 | * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> |
3c5df5c2 | 15 | * PowerPC 403GCX/405GP modifications. |
14cf11af PM |
16 | * Copyright 2000 MontaVista Software Inc. |
17 | * PPC405 modifications | |
3c5df5c2 KG |
18 | * PowerPC 403GCX/405GP modifications. |
19 | * Author: MontaVista Software, Inc. | |
20 | * frank_rowand@mvista.com or source@mvista.com | |
21 | * debbie_chu@mvista.com | |
14cf11af | 22 | * Copyright 2002-2004 MontaVista Software, Inc. |
3c5df5c2 | 23 | * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org> |
14cf11af | 24 | * Copyright 2004 Freescale Semiconductor, Inc |
3c5df5c2 | 25 | * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org> |
14cf11af PM |
26 | * |
27 | * This program is free software; you can redistribute it and/or modify it | |
28 | * under the terms of the GNU General Public License as published by the | |
29 | * Free Software Foundation; either version 2 of the License, or (at your | |
30 | * option) any later version. | |
31 | */ | |
32 | ||
e7039845 | 33 | #include <linux/init.h> |
14cf11af PM |
34 | #include <linux/threads.h> |
35 | #include <asm/processor.h> | |
36 | #include <asm/page.h> | |
37 | #include <asm/mmu.h> | |
38 | #include <asm/pgtable.h> | |
39 | #include <asm/cputable.h> | |
40 | #include <asm/thread_info.h> | |
41 | #include <asm/ppc_asm.h> | |
42 | #include <asm/asm-offsets.h> | |
fc4033b2 | 43 | #include <asm/cache.h> |
14cf11af PM |
44 | #include "head_booke.h" |
45 | ||
46 | /* As with the other PowerPC ports, it is expected that when code | |
47 | * execution begins here, the following registers contain valid, yet | |
48 | * optional, information: | |
49 | * | |
50 | * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) | |
51 | * r4 - Starting address of the init RAM disk | |
52 | * r5 - Ending address of the init RAM disk | |
53 | * r6 - Start of kernel command line string (e.g. "mem=128") | |
54 | * r7 - End of kernel command line string | |
55 | * | |
56 | */ | |
e7039845 | 57 | __HEAD |
748a7683 KG |
58 | _ENTRY(_stext); |
59 | _ENTRY(_start); | |
14cf11af PM |
60 | /* |
61 | * Reserve a word at a fixed location to store the address | |
62 | * of abatron_pteptrs | |
63 | */ | |
64 | nop | |
65 | /* | |
66 | * Save parameters we are passed | |
67 | */ | |
68 | mr r31,r3 | |
69 | mr r30,r4 | |
70 | mr r29,r5 | |
71 | mr r28,r6 | |
72 | mr r27,r7 | |
0aef996b | 73 | li r25,0 /* phys kernel start (low) */ |
14cf11af | 74 | li r24,0 /* CPU number */ |
0aef996b | 75 | li r23,0 /* phys kernel start (high) */ |
14cf11af PM |
76 | |
77 | /* We try to not make any assumptions about how the boot loader | |
78 | * setup or used the TLBs. We invalidate all mappings from the | |
79 | * boot loader and load a single entry in TLB1[0] to map the | |
e8b63761 DF |
80 | * first 64M of kernel memory. Any boot info passed from the |
81 | * bootloader needs to live in this first 64M. | |
14cf11af PM |
82 | * |
83 | * Requirement on bootloader: | |
84 | * - The page we're executing in needs to reside in TLB1 and | |
85 | * have IPROT=1. If not an invalidate broadcast could | |
86 | * evict the entry we're currently executing in. | |
87 | * | |
88 | * r3 = Index of TLB1 were executing in | |
89 | * r4 = Current MSR[IS] | |
90 | * r5 = Index of TLB1 temp mapping | |
91 | * | |
92 | * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0] | |
93 | * if needed | |
94 | */ | |
95 | ||
d5b26db2 | 96 | _ENTRY(__early_start) |
14cf11af PM |
97 | /* 1. Find the index of the entry we're executing in */ |
98 | bl invstr /* Find our address */ | |
99 | invstr: mflr r6 /* Make it accessible */ | |
100 | mfmsr r7 | |
101 | rlwinm r4,r7,27,31,31 /* extract MSR[IS] */ | |
102 | mfspr r7, SPRN_PID0 | |
103 | slwi r7,r7,16 | |
104 | or r7,r7,r4 | |
105 | mtspr SPRN_MAS6,r7 | |
106 | tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */ | |
14cf11af PM |
107 | mfspr r7,SPRN_MAS1 |
108 | andis. r7,r7,MAS1_VALID@h | |
109 | bne match_TLB | |
105c31df KG |
110 | |
111 | mfspr r7,SPRN_MMUCFG | |
112 | rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */ | |
113 | cmpwi r7,3 | |
114 | bne match_TLB /* skip if NPIDS != 3 */ | |
115 | ||
14cf11af PM |
116 | mfspr r7,SPRN_PID1 |
117 | slwi r7,r7,16 | |
118 | or r7,r7,r4 | |
119 | mtspr SPRN_MAS6,r7 | |
120 | tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */ | |
121 | mfspr r7,SPRN_MAS1 | |
122 | andis. r7,r7,MAS1_VALID@h | |
123 | bne match_TLB | |
124 | mfspr r7, SPRN_PID2 | |
125 | slwi r7,r7,16 | |
126 | or r7,r7,r4 | |
127 | mtspr SPRN_MAS6,r7 | |
128 | tlbsx 0,r6 /* Fall through, we had to match */ | |
105c31df | 129 | |
14cf11af PM |
130 | match_TLB: |
131 | mfspr r7,SPRN_MAS0 | |
132 | rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */ | |
133 | ||
134 | mfspr r7,SPRN_MAS1 /* Insure IPROT set */ | |
135 | oris r7,r7,MAS1_IPROT@h | |
136 | mtspr SPRN_MAS1,r7 | |
137 | tlbwe | |
138 | ||
139 | /* 2. Invalidate all entries except the entry we're executing in */ | |
140 | mfspr r9,SPRN_TLB1CFG | |
141 | andi. r9,r9,0xfff | |
142 | li r6,0 /* Set Entry counter to 0 */ | |
143 | 1: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ | |
144 | rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */ | |
145 | mtspr SPRN_MAS0,r7 | |
146 | tlbre | |
147 | mfspr r7,SPRN_MAS1 | |
148 | rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */ | |
149 | cmpw r3,r6 | |
150 | beq skpinv /* Dont update the current execution TLB */ | |
151 | mtspr SPRN_MAS1,r7 | |
152 | tlbwe | |
153 | isync | |
154 | skpinv: addi r6,r6,1 /* Increment */ | |
155 | cmpw r6,r9 /* Are we done? */ | |
156 | bne 1b /* If not, repeat */ | |
157 | ||
158 | /* Invalidate TLB0 */ | |
3c5df5c2 | 159 | li r6,0x04 |
14cf11af | 160 | tlbivax 0,r6 |
0332f000 | 161 | TLBSYNC |
14cf11af | 162 | /* Invalidate TLB1 */ |
3c5df5c2 | 163 | li r6,0x0c |
14cf11af | 164 | tlbivax 0,r6 |
0332f000 | 165 | TLBSYNC |
14cf11af PM |
166 | |
167 | /* 3. Setup a temp mapping and jump to it */ | |
168 | andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */ | |
169 | addi r5, r5, 0x1 | |
170 | lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ | |
171 | rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ | |
172 | mtspr SPRN_MAS0,r7 | |
173 | tlbre | |
174 | ||
0aef996b KG |
175 | /* grab and fixup the RPN */ |
176 | mfspr r6,SPRN_MAS1 /* extract MAS1[SIZE] */ | |
d66c82ea | 177 | rlwinm r6,r6,25,27,31 |
0aef996b KG |
178 | li r8,-1 |
179 | addi r6,r6,10 | |
180 | slw r6,r8,r6 /* convert to mask */ | |
181 | ||
182 | bl 1f /* Find our address */ | |
183 | 1: mflr r7 | |
184 | ||
185 | mfspr r8,SPRN_MAS3 | |
186 | #ifdef CONFIG_PHYS_64BIT | |
187 | mfspr r23,SPRN_MAS7 | |
188 | #endif | |
189 | and r8,r6,r8 | |
190 | subfic r9,r6,-4096 | |
191 | and r9,r9,r7 | |
192 | ||
193 | or r25,r8,r9 | |
194 | ori r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR) | |
195 | ||
196 | /* Just modify the entry ID and EPN for the temp mapping */ | |
14cf11af PM |
197 | lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ |
198 | rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */ | |
199 | mtspr SPRN_MAS0,r7 | |
200 | xori r6,r4,1 /* Setup TMP mapping in the other Address space */ | |
201 | slwi r6,r6,12 | |
202 | oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h | |
d66c82ea | 203 | ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_4K))@l |
14cf11af PM |
204 | mtspr SPRN_MAS1,r6 |
205 | mfspr r6,SPRN_MAS2 | |
0aef996b | 206 | li r7,0 /* temp EPN = 0 */ |
14cf11af PM |
207 | rlwimi r7,r6,0,20,31 |
208 | mtspr SPRN_MAS2,r7 | |
0aef996b | 209 | mtspr SPRN_MAS3,r8 |
14cf11af PM |
210 | tlbwe |
211 | ||
212 | xori r6,r4,1 | |
213 | slwi r6,r6,5 /* setup new context with other address space */ | |
214 | bl 1f /* Find our address */ | |
215 | 1: mflr r9 | |
216 | rlwimi r7,r9,0,20,31 | |
217 | addi r7,r7,24 | |
218 | mtspr SPRN_SRR0,r7 | |
219 | mtspr SPRN_SRR1,r6 | |
220 | rfi | |
221 | ||
222 | /* 4. Clear out PIDs & Search info */ | |
223 | li r6,0 | |
105c31df | 224 | mtspr SPRN_MAS6,r6 |
14cf11af | 225 | mtspr SPRN_PID0,r6 |
105c31df KG |
226 | |
227 | mfspr r7,SPRN_MMUCFG | |
228 | rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */ | |
229 | cmpwi r7,3 | |
230 | bne 2f /* skip if NPIDS != 3 */ | |
231 | ||
14cf11af PM |
232 | mtspr SPRN_PID1,r6 |
233 | mtspr SPRN_PID2,r6 | |
14cf11af PM |
234 | |
235 | /* 5. Invalidate mapping we started in */ | |
105c31df | 236 | 2: |
14cf11af PM |
237 | lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ |
238 | rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ | |
239 | mtspr SPRN_MAS0,r7 | |
240 | tlbre | |
8ce0a7df BB |
241 | mfspr r6,SPRN_MAS1 |
242 | rlwinm r6,r6,0,2,0 /* clear IPROT */ | |
14cf11af PM |
243 | mtspr SPRN_MAS1,r6 |
244 | tlbwe | |
245 | /* Invalidate TLB1 */ | |
3c5df5c2 | 246 | li r9,0x0c |
14cf11af | 247 | tlbivax 0,r9 |
0332f000 | 248 | TLBSYNC |
14cf11af | 249 | |
b3898895 TP |
250 | /* The mapping only needs to be cache-coherent on SMP */ |
251 | #ifdef CONFIG_SMP | |
252 | #define M_IF_SMP MAS2_M | |
253 | #else | |
254 | #define M_IF_SMP 0 | |
255 | #endif | |
256 | ||
14cf11af PM |
257 | /* 6. Setup KERNELBASE mapping in TLB1[0] */ |
258 | lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */ | |
259 | mtspr SPRN_MAS0,r6 | |
260 | lis r6,(MAS1_VALID|MAS1_IPROT)@h | |
d66c82ea | 261 | ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l |
14cf11af | 262 | mtspr SPRN_MAS1,r6 |
d66c82ea KG |
263 | lis r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@h |
264 | ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@l | |
14cf11af | 265 | mtspr SPRN_MAS2,r6 |
0aef996b | 266 | mtspr SPRN_MAS3,r8 |
14cf11af PM |
267 | tlbwe |
268 | ||
269 | /* 7. Jump to KERNELBASE mapping */ | |
b3898895 TP |
270 | lis r6,(KERNELBASE & ~0xfff)@h |
271 | ori r6,r6,(KERNELBASE & ~0xfff)@l | |
14cf11af PM |
272 | lis r7,MSR_KERNEL@h |
273 | ori r7,r7,MSR_KERNEL@l | |
274 | bl 1f /* Find our address */ | |
275 | 1: mflr r9 | |
276 | rlwimi r6,r9,0,20,31 | |
b3898895 | 277 | addi r6,r6,(2f - 1b) |
14cf11af PM |
278 | mtspr SPRN_SRR0,r6 |
279 | mtspr SPRN_SRR1,r7 | |
280 | rfi /* start execution out of TLB1[0] entry */ | |
281 | ||
282 | /* 8. Clear out the temp mapping */ | |
b3898895 | 283 | 2: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ |
14cf11af PM |
284 | rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */ |
285 | mtspr SPRN_MAS0,r7 | |
286 | tlbre | |
8ce0a7df BB |
287 | mfspr r8,SPRN_MAS1 |
288 | rlwinm r8,r8,0,2,0 /* clear IPROT */ | |
14cf11af PM |
289 | mtspr SPRN_MAS1,r8 |
290 | tlbwe | |
291 | /* Invalidate TLB1 */ | |
3c5df5c2 | 292 | li r9,0x0c |
14cf11af | 293 | tlbivax 0,r9 |
0332f000 | 294 | TLBSYNC |
14cf11af PM |
295 | |
296 | /* Establish the interrupt vector offsets */ | |
297 | SET_IVOR(0, CriticalInput); | |
298 | SET_IVOR(1, MachineCheck); | |
299 | SET_IVOR(2, DataStorage); | |
300 | SET_IVOR(3, InstructionStorage); | |
301 | SET_IVOR(4, ExternalInput); | |
302 | SET_IVOR(5, Alignment); | |
303 | SET_IVOR(6, Program); | |
304 | SET_IVOR(7, FloatingPointUnavailable); | |
305 | SET_IVOR(8, SystemCall); | |
306 | SET_IVOR(9, AuxillaryProcessorUnavailable); | |
307 | SET_IVOR(10, Decrementer); | |
308 | SET_IVOR(11, FixedIntervalTimer); | |
309 | SET_IVOR(12, WatchdogTimer); | |
310 | SET_IVOR(13, DataTLBError); | |
311 | SET_IVOR(14, InstructionTLBError); | |
eb0cd5fd | 312 | SET_IVOR(15, DebugCrit); |
14cf11af PM |
313 | |
314 | /* Establish the interrupt vector base */ | |
315 | lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ | |
316 | mtspr SPRN_IVPR,r4 | |
317 | ||
318 | /* Setup the defaults for TLB entries */ | |
d66c82ea | 319 | li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l |
14cf11af PM |
320 | #ifdef CONFIG_E200 |
321 | oris r2,r2,MAS4_TLBSELD(1)@h | |
322 | #endif | |
3c5df5c2 | 323 | mtspr SPRN_MAS4, r2 |
14cf11af PM |
324 | |
325 | #if 0 | |
326 | /* Enable DOZE */ | |
327 | mfspr r2,SPRN_HID0 | |
328 | oris r2,r2,HID0_DOZE@h | |
329 | mtspr SPRN_HID0, r2 | |
330 | #endif | |
14cf11af PM |
331 | |
332 | #if !defined(CONFIG_BDI_SWITCH) | |
333 | /* | |
334 | * The Abatron BDI JTAG debugger does not tolerate others | |
335 | * mucking with the debug registers. | |
336 | */ | |
337 | lis r2,DBCR0_IDM@h | |
338 | mtspr SPRN_DBCR0,r2 | |
a7cb0337 | 339 | isync |
14cf11af PM |
340 | /* clear any residual debug events */ |
341 | li r2,-1 | |
342 | mtspr SPRN_DBSR,r2 | |
343 | #endif | |
344 | ||
d5b26db2 KG |
345 | #ifdef CONFIG_SMP |
346 | /* Check to see if we're the second processor, and jump | |
347 | * to the secondary_start code if so | |
348 | */ | |
349 | mfspr r24,SPRN_PIR | |
350 | cmpwi r24,0 | |
351 | bne __secondary_start | |
352 | #endif | |
353 | ||
14cf11af PM |
354 | /* |
355 | * This is where the main kernel code starts. | |
356 | */ | |
357 | ||
358 | /* ptr to current */ | |
359 | lis r2,init_task@h | |
360 | ori r2,r2,init_task@l | |
361 | ||
362 | /* ptr to current thread */ | |
363 | addi r4,r2,THREAD /* init task's THREAD */ | |
ee43eb78 | 364 | mtspr SPRN_SPRG_THREAD,r4 |
14cf11af PM |
365 | |
366 | /* stack */ | |
367 | lis r1,init_thread_union@h | |
368 | ori r1,r1,init_thread_union@l | |
369 | li r0,0 | |
370 | stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) | |
371 | ||
372 | bl early_init | |
373 | ||
37dd2bad KG |
374 | #ifdef CONFIG_RELOCATABLE |
375 | lis r3,kernstart_addr@ha | |
376 | la r3,kernstart_addr@l(r3) | |
377 | #ifdef CONFIG_PHYS_64BIT | |
378 | stw r23,0(r3) | |
379 | stw r25,4(r3) | |
380 | #else | |
381 | stw r25,0(r3) | |
382 | #endif | |
383 | #endif | |
384 | ||
14cf11af PM |
385 | /* |
386 | * Decide what sort of machine this is and initialize the MMU. | |
387 | */ | |
388 | mr r3,r31 | |
389 | mr r4,r30 | |
390 | mr r5,r29 | |
391 | mr r6,r28 | |
392 | mr r7,r27 | |
393 | bl machine_init | |
394 | bl MMU_init | |
395 | ||
396 | /* Setup PTE pointers for the Abatron bdiGDB */ | |
397 | lis r6, swapper_pg_dir@h | |
398 | ori r6, r6, swapper_pg_dir@l | |
399 | lis r5, abatron_pteptrs@h | |
400 | ori r5, r5, abatron_pteptrs@l | |
401 | lis r4, KERNELBASE@h | |
402 | ori r4, r4, KERNELBASE@l | |
403 | stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */ | |
404 | stw r6, 0(r5) | |
405 | ||
406 | /* Let's move on */ | |
407 | lis r4,start_kernel@h | |
408 | ori r4,r4,start_kernel@l | |
409 | lis r3,MSR_KERNEL@h | |
410 | ori r3,r3,MSR_KERNEL@l | |
411 | mtspr SPRN_SRR0,r4 | |
412 | mtspr SPRN_SRR1,r3 | |
413 | rfi /* change context and jump to start_kernel */ | |
414 | ||
415 | /* Macros to hide the PTE size differences | |
416 | * | |
417 | * FIND_PTE -- walks the page tables given EA & pgdir pointer | |
418 | * r10 -- EA of fault | |
419 | * r11 -- PGDIR pointer | |
420 | * r12 -- free | |
421 | * label 2: is the bailout case | |
422 | * | |
423 | * if we find the pte (fall through): | |
424 | * r11 is low pte word | |
425 | * r12 is pointer to the pte | |
426 | */ | |
427 | #ifdef CONFIG_PTE_64BIT | |
14cf11af | 428 | #define FIND_PTE \ |
3c5df5c2 | 429 | rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \ |
14cf11af PM |
430 | lwzx r11, r12, r11; /* Get pgd/pmd entry */ \ |
431 | rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \ | |
432 | beq 2f; /* Bail if no table */ \ | |
433 | rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \ | |
434 | lwz r11, 4(r12); /* Get pte entry */ | |
435 | #else | |
14cf11af PM |
436 | #define FIND_PTE \ |
437 | rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \ | |
438 | lwz r11, 0(r11); /* Get L1 entry */ \ | |
439 | rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \ | |
440 | beq 2f; /* Bail if no table */ \ | |
441 | rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \ | |
442 | lwz r11, 0(r12); /* Get Linux PTE */ | |
443 | #endif | |
444 | ||
445 | /* | |
446 | * Interrupt vector entry code | |
447 | * | |
448 | * The Book E MMUs are always on so we don't need to handle | |
449 | * interrupts in real mode as with previous PPC processors. In | |
450 | * this case we handle interrupts in the kernel virtual address | |
451 | * space. | |
452 | * | |
453 | * Interrupt vectors are dynamically placed relative to the | |
454 | * interrupt prefix as determined by the address of interrupt_base. | |
455 | * The interrupt vectors offsets are programmed using the labels | |
456 | * for each interrupt vector entry. | |
457 | * | |
458 | * Interrupt vectors must be aligned on a 16 byte boundary. | |
459 | * We align on a 32 byte cache line boundary for good measure. | |
460 | */ | |
461 | ||
462 | interrupt_base: | |
463 | /* Critical Input Interrupt */ | |
dc1c1ca3 | 464 | CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception) |
14cf11af PM |
465 | |
466 | /* Machine Check Interrupt */ | |
467 | #ifdef CONFIG_E200 | |
468 | /* no RFMCI, MCSRRs on E200 */ | |
dc1c1ca3 | 469 | CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception) |
14cf11af | 470 | #else |
dc1c1ca3 | 471 | MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception) |
14cf11af PM |
472 | #endif |
473 | ||
474 | /* Data Storage Interrupt */ | |
475 | START_EXCEPTION(DataStorage) | |
6cfd8990 KG |
476 | NORMAL_EXCEPTION_PROLOG |
477 | mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */ | |
478 | stw r5,_ESR(r11) | |
479 | mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */ | |
480 | andis. r10,r5,(ESR_ILK|ESR_DLK)@h | |
481 | bne 1f | |
482 | EXC_XFER_EE_LITE(0x0300, handle_page_fault) | |
483 | 1: | |
484 | addi r3,r1,STACK_FRAME_OVERHEAD | |
485 | EXC_XFER_EE_LITE(0x0300, CacheLockingException) | |
14cf11af PM |
486 | |
487 | /* Instruction Storage Interrupt */ | |
488 | INSTRUCTION_STORAGE_EXCEPTION | |
489 | ||
490 | /* External Input Interrupt */ | |
491 | EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE) | |
492 | ||
493 | /* Alignment Interrupt */ | |
494 | ALIGNMENT_EXCEPTION | |
495 | ||
496 | /* Program Interrupt */ | |
497 | PROGRAM_EXCEPTION | |
498 | ||
499 | /* Floating Point Unavailable Interrupt */ | |
500 | #ifdef CONFIG_PPC_FPU | |
501 | FP_UNAVAILABLE_EXCEPTION | |
502 | #else | |
503 | #ifdef CONFIG_E200 | |
504 | /* E200 treats 'normal' floating point instructions as FP Unavail exception */ | |
dc1c1ca3 | 505 | EXCEPTION(0x0800, FloatingPointUnavailable, program_check_exception, EXC_XFER_EE) |
14cf11af | 506 | #else |
dc1c1ca3 | 507 | EXCEPTION(0x0800, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE) |
14cf11af PM |
508 | #endif |
509 | #endif | |
510 | ||
511 | /* System Call Interrupt */ | |
512 | START_EXCEPTION(SystemCall) | |
513 | NORMAL_EXCEPTION_PROLOG | |
514 | EXC_XFER_EE_LITE(0x0c00, DoSyscall) | |
515 | ||
516 | /* Auxillary Processor Unavailable Interrupt */ | |
dc1c1ca3 | 517 | EXCEPTION(0x2900, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE) |
14cf11af PM |
518 | |
519 | /* Decrementer Interrupt */ | |
520 | DECREMENTER_EXCEPTION | |
521 | ||
522 | /* Fixed Internal Timer Interrupt */ | |
523 | /* TODO: Add FIT support */ | |
dc1c1ca3 | 524 | EXCEPTION(0x3100, FixedIntervalTimer, unknown_exception, EXC_XFER_EE) |
14cf11af PM |
525 | |
526 | /* Watchdog Timer Interrupt */ | |
527 | #ifdef CONFIG_BOOKE_WDT | |
528 | CRITICAL_EXCEPTION(0x3200, WatchdogTimer, WatchdogException) | |
529 | #else | |
dc1c1ca3 | 530 | CRITICAL_EXCEPTION(0x3200, WatchdogTimer, unknown_exception) |
14cf11af PM |
531 | #endif |
532 | ||
533 | /* Data TLB Error Interrupt */ | |
534 | START_EXCEPTION(DataTLBError) | |
ee43eb78 BH |
535 | mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */ |
536 | mtspr SPRN_SPRG_WSCRATCH1, r11 | |
537 | mtspr SPRN_SPRG_WSCRATCH2, r12 | |
538 | mtspr SPRN_SPRG_WSCRATCH3, r13 | |
14cf11af | 539 | mfcr r11 |
ee43eb78 | 540 | mtspr SPRN_SPRG_WSCRATCH4, r11 |
14cf11af PM |
541 | mfspr r10, SPRN_DEAR /* Get faulting address */ |
542 | ||
543 | /* If we are faulting a kernel address, we have to use the | |
544 | * kernel page tables. | |
545 | */ | |
8a13c4f9 | 546 | lis r11, PAGE_OFFSET@h |
14cf11af PM |
547 | cmplw 5, r10, r11 |
548 | blt 5, 3f | |
549 | lis r11, swapper_pg_dir@h | |
550 | ori r11, r11, swapper_pg_dir@l | |
551 | ||
552 | mfspr r12,SPRN_MAS1 /* Set TID to 0 */ | |
553 | rlwinm r12,r12,0,16,1 | |
554 | mtspr SPRN_MAS1,r12 | |
555 | ||
556 | b 4f | |
557 | ||
558 | /* Get the PGD for the current thread */ | |
559 | 3: | |
ee43eb78 | 560 | mfspr r11,SPRN_SPRG_THREAD |
14cf11af PM |
561 | lwz r11,PGDIR(r11) |
562 | ||
563 | 4: | |
6cfd8990 KG |
564 | /* Mask of required permission bits. Note that while we |
565 | * do copy ESR:ST to _PAGE_RW position as trying to write | |
566 | * to an RO page is pretty common, we don't do it with | |
567 | * _PAGE_DIRTY. We could do it, but it's a fairly rare | |
568 | * event so I'd rather take the overhead when it happens | |
569 | * rather than adding an instruction here. We should measure | |
570 | * whether the whole thing is worth it in the first place | |
571 | * as we could avoid loading SPRN_ESR completely in the first | |
572 | * place... | |
573 | * | |
574 | * TODO: Is it worth doing that mfspr & rlwimi in the first | |
575 | * place or can we save a couple of instructions here ? | |
576 | */ | |
577 | mfspr r12,SPRN_ESR | |
76acc2c1 KG |
578 | #ifdef CONFIG_PTE_64BIT |
579 | li r13,_PAGE_PRESENT | |
580 | oris r13,r13,_PAGE_ACCESSED@h | |
581 | #else | |
6cfd8990 | 582 | li r13,_PAGE_PRESENT|_PAGE_ACCESSED |
76acc2c1 | 583 | #endif |
6cfd8990 KG |
584 | rlwimi r13,r12,11,29,29 |
585 | ||
14cf11af | 586 | FIND_PTE |
6cfd8990 | 587 | andc. r13,r13,r11 /* Check permission */ |
14cf11af PM |
588 | |
589 | #ifdef CONFIG_PTE_64BIT | |
b38fd42f KG |
590 | #ifdef CONFIG_SMP |
591 | subf r10,r11,r12 /* create false data dep */ | |
592 | lwzx r13,r11,r10 /* Get upper pte bits */ | |
593 | #else | |
594 | lwz r13,0(r12) /* Get upper pte bits */ | |
595 | #endif | |
14cf11af | 596 | #endif |
14cf11af | 597 | |
b38fd42f KG |
598 | bne 2f /* Bail if permission/valid mismach */ |
599 | ||
600 | /* Jump to common tlb load */ | |
14cf11af PM |
601 | b finish_tlb_load |
602 | 2: | |
603 | /* The bailout. Restore registers to pre-exception conditions | |
604 | * and call the heavyweights to help us out. | |
605 | */ | |
ee43eb78 | 606 | mfspr r11, SPRN_SPRG_RSCRATCH4 |
14cf11af | 607 | mtcr r11 |
ee43eb78 BH |
608 | mfspr r13, SPRN_SPRG_RSCRATCH3 |
609 | mfspr r12, SPRN_SPRG_RSCRATCH2 | |
610 | mfspr r11, SPRN_SPRG_RSCRATCH1 | |
611 | mfspr r10, SPRN_SPRG_RSCRATCH0 | |
6cfd8990 | 612 | b DataStorage |
14cf11af PM |
613 | |
614 | /* Instruction TLB Error Interrupt */ | |
615 | /* | |
616 | * Nearly the same as above, except we get our | |
617 | * information from different registers and bailout | |
618 | * to a different point. | |
619 | */ | |
620 | START_EXCEPTION(InstructionTLBError) | |
ee43eb78 BH |
621 | mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */ |
622 | mtspr SPRN_SPRG_WSCRATCH1, r11 | |
623 | mtspr SPRN_SPRG_WSCRATCH2, r12 | |
624 | mtspr SPRN_SPRG_WSCRATCH3, r13 | |
14cf11af | 625 | mfcr r11 |
ee43eb78 | 626 | mtspr SPRN_SPRG_WSCRATCH4, r11 |
14cf11af PM |
627 | mfspr r10, SPRN_SRR0 /* Get faulting address */ |
628 | ||
629 | /* If we are faulting a kernel address, we have to use the | |
630 | * kernel page tables. | |
631 | */ | |
8a13c4f9 | 632 | lis r11, PAGE_OFFSET@h |
14cf11af PM |
633 | cmplw 5, r10, r11 |
634 | blt 5, 3f | |
635 | lis r11, swapper_pg_dir@h | |
636 | ori r11, r11, swapper_pg_dir@l | |
637 | ||
638 | mfspr r12,SPRN_MAS1 /* Set TID to 0 */ | |
639 | rlwinm r12,r12,0,16,1 | |
640 | mtspr SPRN_MAS1,r12 | |
641 | ||
642 | b 4f | |
643 | ||
644 | /* Get the PGD for the current thread */ | |
645 | 3: | |
ee43eb78 | 646 | mfspr r11,SPRN_SPRG_THREAD |
14cf11af PM |
647 | lwz r11,PGDIR(r11) |
648 | ||
649 | 4: | |
6cfd8990 | 650 | /* Make up the required permissions */ |
76acc2c1 KG |
651 | #ifdef CONFIG_PTE_64BIT |
652 | li r13,_PAGE_PRESENT | _PAGE_EXEC | |
653 | oris r13,r13,_PAGE_ACCESSED@h | |
654 | #else | |
ea3cc330 | 655 | li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC |
76acc2c1 | 656 | #endif |
6cfd8990 | 657 | |
14cf11af | 658 | FIND_PTE |
6cfd8990 | 659 | andc. r13,r13,r11 /* Check permission */ |
b38fd42f KG |
660 | |
661 | #ifdef CONFIG_PTE_64BIT | |
662 | #ifdef CONFIG_SMP | |
663 | subf r10,r11,r12 /* create false data dep */ | |
664 | lwzx r13,r11,r10 /* Get upper pte bits */ | |
665 | #else | |
666 | lwz r13,0(r12) /* Get upper pte bits */ | |
667 | #endif | |
668 | #endif | |
669 | ||
6cfd8990 | 670 | bne 2f /* Bail if permission mismach */ |
14cf11af | 671 | |
14cf11af PM |
672 | /* Jump to common TLB load point */ |
673 | b finish_tlb_load | |
674 | ||
675 | 2: | |
676 | /* The bailout. Restore registers to pre-exception conditions | |
677 | * and call the heavyweights to help us out. | |
678 | */ | |
ee43eb78 | 679 | mfspr r11, SPRN_SPRG_RSCRATCH4 |
14cf11af | 680 | mtcr r11 |
ee43eb78 BH |
681 | mfspr r13, SPRN_SPRG_RSCRATCH3 |
682 | mfspr r12, SPRN_SPRG_RSCRATCH2 | |
683 | mfspr r11, SPRN_SPRG_RSCRATCH1 | |
684 | mfspr r10, SPRN_SPRG_RSCRATCH0 | |
14cf11af PM |
685 | b InstructionStorage |
686 | ||
687 | #ifdef CONFIG_SPE | |
688 | /* SPE Unavailable */ | |
689 | START_EXCEPTION(SPEUnavailable) | |
690 | NORMAL_EXCEPTION_PROLOG | |
691 | bne load_up_spe | |
3c5df5c2 | 692 | addi r3,r1,STACK_FRAME_OVERHEAD |
14cf11af PM |
693 | EXC_XFER_EE_LITE(0x2010, KernelSPE) |
694 | #else | |
dc1c1ca3 | 695 | EXCEPTION(0x2020, SPEUnavailable, unknown_exception, EXC_XFER_EE) |
14cf11af PM |
696 | #endif /* CONFIG_SPE */ |
697 | ||
698 | /* SPE Floating Point Data */ | |
699 | #ifdef CONFIG_SPE | |
700 | EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE); | |
14cf11af PM |
701 | |
702 | /* SPE Floating Point Round */ | |
6a800f36 LY |
703 | EXCEPTION(0x2050, SPEFloatingPointRound, SPEFloatingPointRoundException, EXC_XFER_EE) |
704 | #else | |
705 | EXCEPTION(0x2040, SPEFloatingPointData, unknown_exception, EXC_XFER_EE) | |
dc1c1ca3 | 706 | EXCEPTION(0x2050, SPEFloatingPointRound, unknown_exception, EXC_XFER_EE) |
6a800f36 | 707 | #endif /* CONFIG_SPE */ |
14cf11af PM |
708 | |
709 | /* Performance Monitor */ | |
dc1c1ca3 | 710 | EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD) |
14cf11af | 711 | |
620165f9 KG |
712 | EXCEPTION(0x2070, Doorbell, doorbell_exception, EXC_XFER_STD) |
713 | ||
714 | CRITICAL_EXCEPTION(0x2080, CriticalDoorbell, unknown_exception) | |
14cf11af PM |
715 | |
716 | /* Debug Interrupt */ | |
eb0cd5fd | 717 | DEBUG_DEBUG_EXCEPTION |
eb0cd5fd | 718 | DEBUG_CRIT_EXCEPTION |
14cf11af PM |
719 | |
720 | /* | |
721 | * Local functions | |
722 | */ | |
723 | ||
14cf11af | 724 | /* |
14cf11af PM |
725 | * Both the instruction and data TLB miss get to this |
726 | * point to load the TLB. | |
b38fd42f | 727 | * r10 - available to use |
3c5df5c2 | 728 | * r11 - TLB (info from Linux PTE) |
6cfd8990 KG |
729 | * r12 - available to use |
730 | * r13 - upper bits of PTE (if PTE_64BIT) or available to use | |
8a13c4f9 | 731 | * CR5 - results of addr >= PAGE_OFFSET |
14cf11af PM |
732 | * MAS0, MAS1 - loaded with proper value when we get here |
733 | * MAS2, MAS3 - will need additional info from Linux PTE | |
734 | * Upon exit, we reload everything and RFI. | |
735 | */ | |
736 | finish_tlb_load: | |
737 | /* | |
738 | * We set execute, because we don't have the granularity to | |
739 | * properly set this at the page level (Linux problem). | |
740 | * Many of these bits are software only. Bits we don't set | |
741 | * here we (properly should) assume have the appropriate value. | |
742 | */ | |
743 | ||
744 | mfspr r12, SPRN_MAS2 | |
745 | #ifdef CONFIG_PTE_64BIT | |
76acc2c1 | 746 | rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */ |
14cf11af PM |
747 | #else |
748 | rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */ | |
d5b26db2 KG |
749 | #endif |
750 | #ifdef CONFIG_SMP | |
751 | ori r12, r12, MAS2_M | |
14cf11af PM |
752 | #endif |
753 | mtspr SPRN_MAS2, r12 | |
754 | ||
76acc2c1 KG |
755 | #ifdef CONFIG_PTE_64BIT |
756 | rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */ | |
757 | andi. r10, r11, _PAGE_DIRTY | |
758 | bne 1f | |
759 | li r10, MAS3_SW | MAS3_UW | |
760 | andc r12, r12, r10 | |
761 | 1: rlwimi r12, r13, 20, 0, 11 /* grab RPN[32:43] */ | |
762 | rlwimi r12, r11, 20, 12, 19 /* grab RPN[44:51] */ | |
763 | mtspr SPRN_MAS3, r12 | |
764 | BEGIN_MMU_FTR_SECTION | |
765 | srwi r10, r13, 12 /* grab RPN[12:31] */ | |
766 | mtspr SPRN_MAS7, r10 | |
767 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS) | |
768 | #else | |
ea3cc330 | 769 | li r10, (_PAGE_EXEC | _PAGE_PRESENT) |
6cfd8990 KG |
770 | rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */ |
771 | and r12, r11, r10 | |
14cf11af | 772 | andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */ |
6cfd8990 KG |
773 | slwi r10, r12, 1 |
774 | or r10, r10, r12 | |
775 | iseleq r12, r12, r10 | |
06b90969 | 776 | rlwimi r11, r12, 0, 20, 31 /* Extract RPN from PTE and merge with perms */ |
14cf11af PM |
777 | mtspr SPRN_MAS3, r11 |
778 | #endif | |
779 | #ifdef CONFIG_E200 | |
780 | /* Round robin TLB1 entries assignment */ | |
781 | mfspr r12, SPRN_MAS0 | |
782 | ||
783 | /* Extract TLB1CFG(NENTRY) */ | |
784 | mfspr r11, SPRN_TLB1CFG | |
785 | andi. r11, r11, 0xfff | |
786 | ||
787 | /* Extract MAS0(NV) */ | |
788 | andi. r13, r12, 0xfff | |
789 | addi r13, r13, 1 | |
790 | cmpw 0, r13, r11 | |
791 | addi r12, r12, 1 | |
792 | ||
793 | /* check if we need to wrap */ | |
794 | blt 7f | |
795 | ||
796 | /* wrap back to first free tlbcam entry */ | |
797 | lis r13, tlbcam_index@ha | |
798 | lwz r13, tlbcam_index@l(r13) | |
799 | rlwimi r12, r13, 0, 20, 31 | |
800 | 7: | |
3c5df5c2 | 801 | mtspr SPRN_MAS0,r12 |
14cf11af PM |
802 | #endif /* CONFIG_E200 */ |
803 | ||
804 | tlbwe | |
805 | ||
806 | /* Done...restore registers and get out of here. */ | |
ee43eb78 | 807 | mfspr r11, SPRN_SPRG_RSCRATCH4 |
14cf11af | 808 | mtcr r11 |
ee43eb78 BH |
809 | mfspr r13, SPRN_SPRG_RSCRATCH3 |
810 | mfspr r12, SPRN_SPRG_RSCRATCH2 | |
811 | mfspr r11, SPRN_SPRG_RSCRATCH1 | |
812 | mfspr r10, SPRN_SPRG_RSCRATCH0 | |
14cf11af PM |
813 | rfi /* Force context change */ |
814 | ||
815 | #ifdef CONFIG_SPE | |
816 | /* Note that the SPE support is closely modeled after the AltiVec | |
817 | * support. Changes to one are likely to be applicable to the | |
818 | * other! */ | |
819 | load_up_spe: | |
820 | /* | |
821 | * Disable SPE for the task which had SPE previously, | |
822 | * and save its SPE registers in its thread_struct. | |
823 | * Enables SPE for use in the kernel on return. | |
824 | * On SMP we know the SPE units are free, since we give it up every | |
825 | * switch. -- Kumar | |
826 | */ | |
827 | mfmsr r5 | |
828 | oris r5,r5,MSR_SPE@h | |
829 | mtmsr r5 /* enable use of SPE now */ | |
830 | isync | |
831 | /* | |
832 | * For SMP, we don't do lazy SPE switching because it just gets too | |
833 | * horrendously complex, especially when a task switches from one CPU | |
834 | * to another. Instead we call giveup_spe in switch_to. | |
835 | */ | |
836 | #ifndef CONFIG_SMP | |
837 | lis r3,last_task_used_spe@ha | |
838 | lwz r4,last_task_used_spe@l(r3) | |
839 | cmpi 0,r4,0 | |
840 | beq 1f | |
841 | addi r4,r4,THREAD /* want THREAD of last_task_used_spe */ | |
842 | SAVE_32EVRS(0,r10,r4) | |
3c5df5c2 | 843 | evxor evr10, evr10, evr10 /* clear out evr10 */ |
14cf11af PM |
844 | evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */ |
845 | li r5,THREAD_ACC | |
3c5df5c2 | 846 | evstddx evr10, r4, r5 /* save off accumulator */ |
14cf11af PM |
847 | lwz r5,PT_REGS(r4) |
848 | lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
849 | lis r10,MSR_SPE@h | |
850 | andc r4,r4,r10 /* disable SPE for previous task */ | |
851 | stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
852 | 1: | |
3c5df5c2 | 853 | #endif /* !CONFIG_SMP */ |
14cf11af PM |
854 | /* enable use of SPE after return */ |
855 | oris r9,r9,MSR_SPE@h | |
ee43eb78 | 856 | mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ |
14cf11af PM |
857 | li r4,1 |
858 | li r10,THREAD_ACC | |
859 | stw r4,THREAD_USED_SPE(r5) | |
860 | evlddx evr4,r10,r5 | |
861 | evmra evr4,evr4 | |
862 | REST_32EVRS(0,r10,r5) | |
863 | #ifndef CONFIG_SMP | |
864 | subi r4,r5,THREAD | |
865 | stw r4,last_task_used_spe@l(r3) | |
3c5df5c2 | 866 | #endif /* !CONFIG_SMP */ |
14cf11af PM |
867 | /* restore registers and return */ |
868 | 2: REST_4GPRS(3, r11) | |
869 | lwz r10,_CCR(r11) | |
870 | REST_GPR(1, r11) | |
871 | mtcr r10 | |
872 | lwz r10,_LINK(r11) | |
873 | mtlr r10 | |
874 | REST_GPR(10, r11) | |
875 | mtspr SPRN_SRR1,r9 | |
876 | mtspr SPRN_SRR0,r12 | |
877 | REST_GPR(9, r11) | |
878 | REST_GPR(12, r11) | |
879 | lwz r11,GPR11(r11) | |
14cf11af PM |
880 | rfi |
881 | ||
882 | /* | |
883 | * SPE unavailable trap from kernel - print a message, but let | |
884 | * the task use SPE in the kernel until it returns to user mode. | |
885 | */ | |
886 | KernelSPE: | |
887 | lwz r3,_MSR(r1) | |
888 | oris r3,r3,MSR_SPE@h | |
889 | stw r3,_MSR(r1) /* enable use of SPE after return */ | |
890 | lis r3,87f@h | |
891 | ori r3,r3,87f@l | |
892 | mr r4,r2 /* current */ | |
893 | lwz r5,_NIP(r1) | |
894 | bl printk | |
895 | b ret_from_except | |
896 | 87: .string "SPE used in kernel (task=%p, pc=%x) \n" | |
897 | .align 4,0 | |
898 | ||
899 | #endif /* CONFIG_SPE */ | |
900 | ||
901 | /* | |
902 | * Global functions | |
903 | */ | |
904 | ||
105c31df KG |
905 | /* Adjust or setup IVORs for e200 */ |
906 | _GLOBAL(__setup_e200_ivors) | |
907 | li r3,DebugDebug@l | |
908 | mtspr SPRN_IVOR15,r3 | |
909 | li r3,SPEUnavailable@l | |
910 | mtspr SPRN_IVOR32,r3 | |
911 | li r3,SPEFloatingPointData@l | |
912 | mtspr SPRN_IVOR33,r3 | |
913 | li r3,SPEFloatingPointRound@l | |
914 | mtspr SPRN_IVOR34,r3 | |
915 | sync | |
916 | blr | |
917 | ||
918 | /* Adjust or setup IVORs for e500v1/v2 */ | |
919 | _GLOBAL(__setup_e500_ivors) | |
920 | li r3,DebugCrit@l | |
921 | mtspr SPRN_IVOR15,r3 | |
922 | li r3,SPEUnavailable@l | |
923 | mtspr SPRN_IVOR32,r3 | |
924 | li r3,SPEFloatingPointData@l | |
925 | mtspr SPRN_IVOR33,r3 | |
926 | li r3,SPEFloatingPointRound@l | |
927 | mtspr SPRN_IVOR34,r3 | |
928 | li r3,PerformanceMonitor@l | |
929 | mtspr SPRN_IVOR35,r3 | |
930 | sync | |
931 | blr | |
932 | ||
933 | /* Adjust or setup IVORs for e500mc */ | |
934 | _GLOBAL(__setup_e500mc_ivors) | |
935 | li r3,DebugDebug@l | |
936 | mtspr SPRN_IVOR15,r3 | |
937 | li r3,PerformanceMonitor@l | |
938 | mtspr SPRN_IVOR35,r3 | |
939 | li r3,Doorbell@l | |
940 | mtspr SPRN_IVOR36,r3 | |
620165f9 KG |
941 | li r3,CriticalDoorbell@l |
942 | mtspr SPRN_IVOR37,r3 | |
105c31df KG |
943 | sync |
944 | blr | |
945 | ||
14cf11af PM |
946 | /* |
947 | * extern void loadcam_entry(unsigned int index) | |
948 | * | |
949 | * Load TLBCAM[index] entry in to the L2 CAM MMU | |
950 | */ | |
951 | _GLOBAL(loadcam_entry) | |
952 | lis r4,TLBCAM@ha | |
953 | addi r4,r4,TLBCAM@l | |
19f5465e | 954 | mulli r5,r3,TLBCAM_SIZE |
14cf11af PM |
955 | add r3,r5,r4 |
956 | lwz r4,0(r3) | |
957 | mtspr SPRN_MAS0,r4 | |
958 | lwz r4,4(r3) | |
959 | mtspr SPRN_MAS1,r4 | |
960 | lwz r4,8(r3) | |
961 | mtspr SPRN_MAS2,r4 | |
962 | lwz r4,12(r3) | |
963 | mtspr SPRN_MAS3,r4 | |
964 | tlbwe | |
965 | isync | |
966 | blr | |
967 | ||
968 | /* | |
969 | * extern void giveup_altivec(struct task_struct *prev) | |
970 | * | |
971 | * The e500 core does not have an AltiVec unit. | |
972 | */ | |
973 | _GLOBAL(giveup_altivec) | |
974 | blr | |
975 | ||
976 | #ifdef CONFIG_SPE | |
977 | /* | |
978 | * extern void giveup_spe(struct task_struct *prev) | |
979 | * | |
980 | */ | |
981 | _GLOBAL(giveup_spe) | |
982 | mfmsr r5 | |
983 | oris r5,r5,MSR_SPE@h | |
14cf11af PM |
984 | mtmsr r5 /* enable use of SPE now */ |
985 | isync | |
986 | cmpi 0,r3,0 | |
987 | beqlr- /* if no previous owner, done */ | |
988 | addi r3,r3,THREAD /* want THREAD of task */ | |
989 | lwz r5,PT_REGS(r3) | |
990 | cmpi 0,r5,0 | |
991 | SAVE_32EVRS(0, r4, r3) | |
3c5df5c2 | 992 | evxor evr6, evr6, evr6 /* clear out evr6 */ |
14cf11af PM |
993 | evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */ |
994 | li r4,THREAD_ACC | |
3c5df5c2 | 995 | evstddx evr6, r4, r3 /* save off accumulator */ |
14cf11af PM |
996 | mfspr r6,SPRN_SPEFSCR |
997 | stw r6,THREAD_SPEFSCR(r3) /* save spefscr register value */ | |
998 | beq 1f | |
999 | lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
1000 | lis r3,MSR_SPE@h | |
1001 | andc r4,r4,r3 /* disable SPE for previous task */ | |
1002 | stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
1003 | 1: | |
1004 | #ifndef CONFIG_SMP | |
1005 | li r5,0 | |
1006 | lis r4,last_task_used_spe@ha | |
1007 | stw r5,last_task_used_spe@l(r4) | |
3c5df5c2 | 1008 | #endif /* !CONFIG_SMP */ |
14cf11af PM |
1009 | blr |
1010 | #endif /* CONFIG_SPE */ | |
1011 | ||
1012 | /* | |
1013 | * extern void giveup_fpu(struct task_struct *prev) | |
1014 | * | |
1015 | * Not all FSL Book-E cores have an FPU | |
1016 | */ | |
1017 | #ifndef CONFIG_PPC_FPU | |
1018 | _GLOBAL(giveup_fpu) | |
1019 | blr | |
1020 | #endif | |
1021 | ||
1022 | /* | |
1023 | * extern void abort(void) | |
1024 | * | |
1025 | * At present, this routine just applies a system reset. | |
1026 | */ | |
1027 | _GLOBAL(abort) | |
1028 | li r13,0 | |
3c5df5c2 | 1029 | mtspr SPRN_DBCR0,r13 /* disable all debug events */ |
a7cb0337 | 1030 | isync |
14cf11af PM |
1031 | mfmsr r13 |
1032 | ori r13,r13,MSR_DE@l /* Enable Debug Events */ | |
1033 | mtmsr r13 | |
a7cb0337 | 1034 | isync |
3c5df5c2 KG |
1035 | mfspr r13,SPRN_DBCR0 |
1036 | lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h | |
1037 | mtspr SPRN_DBCR0,r13 | |
a7cb0337 | 1038 | isync |
14cf11af PM |
1039 | |
1040 | _GLOBAL(set_context) | |
1041 | ||
1042 | #ifdef CONFIG_BDI_SWITCH | |
1043 | /* Context switch the PTE pointer for the Abatron BDI2000. | |
1044 | * The PGDIR is the second parameter. | |
1045 | */ | |
1046 | lis r5, abatron_pteptrs@h | |
1047 | ori r5, r5, abatron_pteptrs@l | |
1048 | stw r4, 0x4(r5) | |
1049 | #endif | |
1050 | mtspr SPRN_PID,r3 | |
1051 | isync /* Force context change */ | |
1052 | blr | |
1053 | ||
fc4033b2 KG |
1054 | _GLOBAL(flush_dcache_L1) |
1055 | mfspr r3,SPRN_L1CFG0 | |
1056 | ||
1057 | rlwinm r5,r3,9,3 /* Extract cache block size */ | |
1058 | twlgti r5,1 /* Only 32 and 64 byte cache blocks | |
1059 | * are currently defined. | |
1060 | */ | |
1061 | li r4,32 | |
1062 | subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) - | |
1063 | * log2(number of ways) | |
1064 | */ | |
1065 | slw r5,r4,r5 /* r5 = cache block size */ | |
1066 | ||
1067 | rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */ | |
1068 | mulli r7,r7,13 /* An 8-way cache will require 13 | |
1069 | * loads per set. | |
1070 | */ | |
1071 | slw r7,r7,r6 | |
1072 | ||
1073 | /* save off HID0 and set DCFA */ | |
1074 | mfspr r8,SPRN_HID0 | |
1075 | ori r9,r8,HID0_DCFA@l | |
1076 | mtspr SPRN_HID0,r9 | |
1077 | isync | |
1078 | ||
1079 | lis r4,KERNELBASE@h | |
1080 | mtctr r7 | |
1081 | ||
1082 | 1: lwz r3,0(r4) /* Load... */ | |
1083 | add r4,r4,r5 | |
1084 | bdnz 1b | |
1085 | ||
1086 | msync | |
1087 | lis r4,KERNELBASE@h | |
1088 | mtctr r7 | |
1089 | ||
1090 | 1: dcbf 0,r4 /* ...and flush. */ | |
1091 | add r4,r4,r5 | |
1092 | bdnz 1b | |
1093 | ||
1094 | /* restore HID0 */ | |
1095 | mtspr SPRN_HID0,r8 | |
1096 | isync | |
1097 | ||
1098 | blr | |
1099 | ||
d5b26db2 KG |
1100 | #ifdef CONFIG_SMP |
1101 | /* When we get here, r24 needs to hold the CPU # */ | |
1102 | .globl __secondary_start | |
1103 | __secondary_start: | |
1104 | lis r3,__secondary_hold_acknowledge@h | |
1105 | ori r3,r3,__secondary_hold_acknowledge@l | |
1106 | stw r24,0(r3) | |
1107 | ||
1108 | li r3,0 | |
1109 | mr r4,r24 /* Why? */ | |
1110 | bl call_setup_cpu | |
1111 | ||
1112 | lis r3,tlbcam_index@ha | |
1113 | lwz r3,tlbcam_index@l(r3) | |
1114 | mtctr r3 | |
1115 | li r26,0 /* r26 safe? */ | |
1116 | ||
1117 | /* Load each CAM entry */ | |
1118 | 1: mr r3,r26 | |
1119 | bl loadcam_entry | |
1120 | addi r26,r26,1 | |
1121 | bdnz 1b | |
1122 | ||
1123 | /* get current_thread_info and current */ | |
1124 | lis r1,secondary_ti@ha | |
1125 | lwz r1,secondary_ti@l(r1) | |
1126 | lwz r2,TI_TASK(r1) | |
1127 | ||
1128 | /* stack */ | |
1129 | addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD | |
1130 | li r0,0 | |
1131 | stw r0,0(r1) | |
1132 | ||
1133 | /* ptr to current thread */ | |
1134 | addi r4,r2,THREAD /* address of our thread_struct */ | |
ee43eb78 | 1135 | mtspr SPRN_SPRG_THREAD,r4 |
d5b26db2 KG |
1136 | |
1137 | /* Setup the defaults for TLB entries */ | |
d66c82ea | 1138 | li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l |
d5b26db2 KG |
1139 | mtspr SPRN_MAS4,r4 |
1140 | ||
1141 | /* Jump to start_secondary */ | |
1142 | lis r4,MSR_KERNEL@h | |
1143 | ori r4,r4,MSR_KERNEL@l | |
1144 | lis r3,start_secondary@h | |
1145 | ori r3,r3,start_secondary@l | |
1146 | mtspr SPRN_SRR0,r3 | |
1147 | mtspr SPRN_SRR1,r4 | |
1148 | sync | |
1149 | rfi | |
1150 | sync | |
1151 | ||
1152 | .globl __secondary_hold_acknowledge | |
1153 | __secondary_hold_acknowledge: | |
1154 | .long -1 | |
1155 | #endif | |
1156 | ||
14cf11af PM |
1157 | /* |
1158 | * We put a few things here that have to be page-aligned. This stuff | |
1159 | * goes at the beginning of the data segment, which is page-aligned. | |
1160 | */ | |
1161 | .data | |
ea703ce2 KG |
1162 | .align 12 |
1163 | .globl sdata | |
1164 | sdata: | |
1165 | .globl empty_zero_page | |
1166 | empty_zero_page: | |
14cf11af | 1167 | .space 4096 |
ea703ce2 KG |
1168 | .globl swapper_pg_dir |
1169 | swapper_pg_dir: | |
bee86f14 | 1170 | .space PGD_TABLE_SIZE |
14cf11af | 1171 | |
14cf11af PM |
1172 | /* |
1173 | * Room for two PTE pointers, usually the kernel and current user pointers | |
1174 | * to their respective root page table. | |
1175 | */ | |
1176 | abatron_pteptrs: | |
1177 | .space 8 |