Commit | Line | Data |
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14cf11af | 1 | /* |
14cf11af PM |
2 | * Kernel execution entry point code. |
3 | * | |
4 | * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> | |
3c5df5c2 | 5 | * Initial PowerPC version. |
14cf11af | 6 | * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> |
3c5df5c2 | 7 | * Rewritten for PReP |
14cf11af | 8 | * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> |
3c5df5c2 | 9 | * Low-level exception handers, MMU support, and rewrite. |
14cf11af | 10 | * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> |
3c5df5c2 | 11 | * PowerPC 8xx modifications. |
14cf11af | 12 | * Copyright (c) 1998-1999 TiVo, Inc. |
3c5df5c2 | 13 | * PowerPC 403GCX modifications. |
14cf11af | 14 | * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> |
3c5df5c2 | 15 | * PowerPC 403GCX/405GP modifications. |
14cf11af PM |
16 | * Copyright 2000 MontaVista Software Inc. |
17 | * PPC405 modifications | |
3c5df5c2 KG |
18 | * PowerPC 403GCX/405GP modifications. |
19 | * Author: MontaVista Software, Inc. | |
20 | * frank_rowand@mvista.com or source@mvista.com | |
21 | * debbie_chu@mvista.com | |
14cf11af | 22 | * Copyright 2002-2004 MontaVista Software, Inc. |
3c5df5c2 | 23 | * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org> |
14cf11af | 24 | * Copyright 2004 Freescale Semiconductor, Inc |
3c5df5c2 | 25 | * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org> |
14cf11af PM |
26 | * |
27 | * This program is free software; you can redistribute it and/or modify it | |
28 | * under the terms of the GNU General Public License as published by the | |
29 | * Free Software Foundation; either version 2 of the License, or (at your | |
30 | * option) any later version. | |
31 | */ | |
32 | ||
14cf11af PM |
33 | #include <linux/threads.h> |
34 | #include <asm/processor.h> | |
35 | #include <asm/page.h> | |
36 | #include <asm/mmu.h> | |
37 | #include <asm/pgtable.h> | |
38 | #include <asm/cputable.h> | |
39 | #include <asm/thread_info.h> | |
40 | #include <asm/ppc_asm.h> | |
41 | #include <asm/asm-offsets.h> | |
fc4033b2 | 42 | #include <asm/cache.h> |
14cf11af PM |
43 | #include "head_booke.h" |
44 | ||
45 | /* As with the other PowerPC ports, it is expected that when code | |
46 | * execution begins here, the following registers contain valid, yet | |
47 | * optional, information: | |
48 | * | |
49 | * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) | |
50 | * r4 - Starting address of the init RAM disk | |
51 | * r5 - Ending address of the init RAM disk | |
52 | * r6 - Start of kernel command line string (e.g. "mem=128") | |
53 | * r7 - End of kernel command line string | |
54 | * | |
55 | */ | |
748a7683 KG |
56 | .section .text.head, "ax" |
57 | _ENTRY(_stext); | |
58 | _ENTRY(_start); | |
14cf11af PM |
59 | /* |
60 | * Reserve a word at a fixed location to store the address | |
61 | * of abatron_pteptrs | |
62 | */ | |
63 | nop | |
64 | /* | |
65 | * Save parameters we are passed | |
66 | */ | |
67 | mr r31,r3 | |
68 | mr r30,r4 | |
69 | mr r29,r5 | |
70 | mr r28,r6 | |
71 | mr r27,r7 | |
0aef996b | 72 | li r25,0 /* phys kernel start (low) */ |
14cf11af | 73 | li r24,0 /* CPU number */ |
0aef996b | 74 | li r23,0 /* phys kernel start (high) */ |
14cf11af PM |
75 | |
76 | /* We try to not make any assumptions about how the boot loader | |
77 | * setup or used the TLBs. We invalidate all mappings from the | |
78 | * boot loader and load a single entry in TLB1[0] to map the | |
e8b63761 DF |
79 | * first 64M of kernel memory. Any boot info passed from the |
80 | * bootloader needs to live in this first 64M. | |
14cf11af PM |
81 | * |
82 | * Requirement on bootloader: | |
83 | * - The page we're executing in needs to reside in TLB1 and | |
84 | * have IPROT=1. If not an invalidate broadcast could | |
85 | * evict the entry we're currently executing in. | |
86 | * | |
87 | * r3 = Index of TLB1 were executing in | |
88 | * r4 = Current MSR[IS] | |
89 | * r5 = Index of TLB1 temp mapping | |
90 | * | |
91 | * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0] | |
92 | * if needed | |
93 | */ | |
94 | ||
95 | /* 1. Find the index of the entry we're executing in */ | |
96 | bl invstr /* Find our address */ | |
97 | invstr: mflr r6 /* Make it accessible */ | |
98 | mfmsr r7 | |
99 | rlwinm r4,r7,27,31,31 /* extract MSR[IS] */ | |
100 | mfspr r7, SPRN_PID0 | |
101 | slwi r7,r7,16 | |
102 | or r7,r7,r4 | |
103 | mtspr SPRN_MAS6,r7 | |
104 | tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */ | |
105 | #ifndef CONFIG_E200 | |
106 | mfspr r7,SPRN_MAS1 | |
107 | andis. r7,r7,MAS1_VALID@h | |
108 | bne match_TLB | |
109 | mfspr r7,SPRN_PID1 | |
110 | slwi r7,r7,16 | |
111 | or r7,r7,r4 | |
112 | mtspr SPRN_MAS6,r7 | |
113 | tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */ | |
114 | mfspr r7,SPRN_MAS1 | |
115 | andis. r7,r7,MAS1_VALID@h | |
116 | bne match_TLB | |
117 | mfspr r7, SPRN_PID2 | |
118 | slwi r7,r7,16 | |
119 | or r7,r7,r4 | |
120 | mtspr SPRN_MAS6,r7 | |
121 | tlbsx 0,r6 /* Fall through, we had to match */ | |
122 | #endif | |
123 | match_TLB: | |
124 | mfspr r7,SPRN_MAS0 | |
125 | rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */ | |
126 | ||
127 | mfspr r7,SPRN_MAS1 /* Insure IPROT set */ | |
128 | oris r7,r7,MAS1_IPROT@h | |
129 | mtspr SPRN_MAS1,r7 | |
130 | tlbwe | |
131 | ||
132 | /* 2. Invalidate all entries except the entry we're executing in */ | |
133 | mfspr r9,SPRN_TLB1CFG | |
134 | andi. r9,r9,0xfff | |
135 | li r6,0 /* Set Entry counter to 0 */ | |
136 | 1: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ | |
137 | rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */ | |
138 | mtspr SPRN_MAS0,r7 | |
139 | tlbre | |
140 | mfspr r7,SPRN_MAS1 | |
141 | rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */ | |
142 | cmpw r3,r6 | |
143 | beq skpinv /* Dont update the current execution TLB */ | |
144 | mtspr SPRN_MAS1,r7 | |
145 | tlbwe | |
146 | isync | |
147 | skpinv: addi r6,r6,1 /* Increment */ | |
148 | cmpw r6,r9 /* Are we done? */ | |
149 | bne 1b /* If not, repeat */ | |
150 | ||
151 | /* Invalidate TLB0 */ | |
3c5df5c2 | 152 | li r6,0x04 |
14cf11af | 153 | tlbivax 0,r6 |
0332f000 | 154 | TLBSYNC |
14cf11af | 155 | /* Invalidate TLB1 */ |
3c5df5c2 | 156 | li r6,0x0c |
14cf11af | 157 | tlbivax 0,r6 |
0332f000 | 158 | TLBSYNC |
14cf11af PM |
159 | |
160 | /* 3. Setup a temp mapping and jump to it */ | |
161 | andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */ | |
162 | addi r5, r5, 0x1 | |
163 | lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ | |
164 | rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ | |
165 | mtspr SPRN_MAS0,r7 | |
166 | tlbre | |
167 | ||
0aef996b KG |
168 | /* grab and fixup the RPN */ |
169 | mfspr r6,SPRN_MAS1 /* extract MAS1[SIZE] */ | |
170 | rlwinm r6,r6,25,27,30 | |
171 | li r8,-1 | |
172 | addi r6,r6,10 | |
173 | slw r6,r8,r6 /* convert to mask */ | |
174 | ||
175 | bl 1f /* Find our address */ | |
176 | 1: mflr r7 | |
177 | ||
178 | mfspr r8,SPRN_MAS3 | |
179 | #ifdef CONFIG_PHYS_64BIT | |
180 | mfspr r23,SPRN_MAS7 | |
181 | #endif | |
182 | and r8,r6,r8 | |
183 | subfic r9,r6,-4096 | |
184 | and r9,r9,r7 | |
185 | ||
186 | or r25,r8,r9 | |
187 | ori r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR) | |
188 | ||
189 | /* Just modify the entry ID and EPN for the temp mapping */ | |
14cf11af PM |
190 | lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ |
191 | rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */ | |
192 | mtspr SPRN_MAS0,r7 | |
193 | xori r6,r4,1 /* Setup TMP mapping in the other Address space */ | |
194 | slwi r6,r6,12 | |
195 | oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h | |
196 | ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l | |
197 | mtspr SPRN_MAS1,r6 | |
198 | mfspr r6,SPRN_MAS2 | |
0aef996b | 199 | li r7,0 /* temp EPN = 0 */ |
14cf11af PM |
200 | rlwimi r7,r6,0,20,31 |
201 | mtspr SPRN_MAS2,r7 | |
0aef996b | 202 | mtspr SPRN_MAS3,r8 |
14cf11af PM |
203 | tlbwe |
204 | ||
205 | xori r6,r4,1 | |
206 | slwi r6,r6,5 /* setup new context with other address space */ | |
207 | bl 1f /* Find our address */ | |
208 | 1: mflr r9 | |
209 | rlwimi r7,r9,0,20,31 | |
210 | addi r7,r7,24 | |
211 | mtspr SPRN_SRR0,r7 | |
212 | mtspr SPRN_SRR1,r6 | |
213 | rfi | |
214 | ||
215 | /* 4. Clear out PIDs & Search info */ | |
216 | li r6,0 | |
217 | mtspr SPRN_PID0,r6 | |
218 | #ifndef CONFIG_E200 | |
219 | mtspr SPRN_PID1,r6 | |
220 | mtspr SPRN_PID2,r6 | |
221 | #endif | |
222 | mtspr SPRN_MAS6,r6 | |
223 | ||
224 | /* 5. Invalidate mapping we started in */ | |
225 | lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ | |
226 | rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ | |
227 | mtspr SPRN_MAS0,r7 | |
228 | tlbre | |
8ce0a7df BB |
229 | mfspr r6,SPRN_MAS1 |
230 | rlwinm r6,r6,0,2,0 /* clear IPROT */ | |
14cf11af PM |
231 | mtspr SPRN_MAS1,r6 |
232 | tlbwe | |
233 | /* Invalidate TLB1 */ | |
3c5df5c2 | 234 | li r9,0x0c |
14cf11af | 235 | tlbivax 0,r9 |
0332f000 | 236 | TLBSYNC |
14cf11af PM |
237 | |
238 | /* 6. Setup KERNELBASE mapping in TLB1[0] */ | |
239 | lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */ | |
240 | mtspr SPRN_MAS0,r6 | |
241 | lis r6,(MAS1_VALID|MAS1_IPROT)@h | |
e8b63761 | 242 | ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l |
14cf11af PM |
243 | mtspr SPRN_MAS1,r6 |
244 | li r7,0 | |
e8b63761 DF |
245 | lis r6,PAGE_OFFSET@h |
246 | ori r6,r6,PAGE_OFFSET@l | |
14cf11af PM |
247 | rlwimi r6,r7,0,20,31 |
248 | mtspr SPRN_MAS2,r6 | |
0aef996b | 249 | mtspr SPRN_MAS3,r8 |
14cf11af PM |
250 | tlbwe |
251 | ||
252 | /* 7. Jump to KERNELBASE mapping */ | |
e8b63761 DF |
253 | lis r6,KERNELBASE@h |
254 | ori r6,r6,KERNELBASE@l | |
255 | rlwimi r6,r7,0,20,31 | |
14cf11af PM |
256 | lis r7,MSR_KERNEL@h |
257 | ori r7,r7,MSR_KERNEL@l | |
258 | bl 1f /* Find our address */ | |
259 | 1: mflr r9 | |
260 | rlwimi r6,r9,0,20,31 | |
261 | addi r6,r6,24 | |
262 | mtspr SPRN_SRR0,r6 | |
263 | mtspr SPRN_SRR1,r7 | |
264 | rfi /* start execution out of TLB1[0] entry */ | |
265 | ||
266 | /* 8. Clear out the temp mapping */ | |
267 | lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ | |
268 | rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */ | |
269 | mtspr SPRN_MAS0,r7 | |
270 | tlbre | |
8ce0a7df BB |
271 | mfspr r8,SPRN_MAS1 |
272 | rlwinm r8,r8,0,2,0 /* clear IPROT */ | |
14cf11af PM |
273 | mtspr SPRN_MAS1,r8 |
274 | tlbwe | |
275 | /* Invalidate TLB1 */ | |
3c5df5c2 | 276 | li r9,0x0c |
14cf11af | 277 | tlbivax 0,r9 |
0332f000 | 278 | TLBSYNC |
14cf11af PM |
279 | |
280 | /* Establish the interrupt vector offsets */ | |
281 | SET_IVOR(0, CriticalInput); | |
282 | SET_IVOR(1, MachineCheck); | |
283 | SET_IVOR(2, DataStorage); | |
284 | SET_IVOR(3, InstructionStorage); | |
285 | SET_IVOR(4, ExternalInput); | |
286 | SET_IVOR(5, Alignment); | |
287 | SET_IVOR(6, Program); | |
288 | SET_IVOR(7, FloatingPointUnavailable); | |
289 | SET_IVOR(8, SystemCall); | |
290 | SET_IVOR(9, AuxillaryProcessorUnavailable); | |
291 | SET_IVOR(10, Decrementer); | |
292 | SET_IVOR(11, FixedIntervalTimer); | |
293 | SET_IVOR(12, WatchdogTimer); | |
294 | SET_IVOR(13, DataTLBError); | |
295 | SET_IVOR(14, InstructionTLBError); | |
eb0cd5fd | 296 | SET_IVOR(15, DebugDebug); |
3dfa8773 | 297 | #if defined(CONFIG_E500) && !defined(CONFIG_PPC_E500MC) |
eb0cd5fd KG |
298 | SET_IVOR(15, DebugCrit); |
299 | #endif | |
14cf11af PM |
300 | SET_IVOR(32, SPEUnavailable); |
301 | SET_IVOR(33, SPEFloatingPointData); | |
302 | SET_IVOR(34, SPEFloatingPointRound); | |
303 | #ifndef CONFIG_E200 | |
304 | SET_IVOR(35, PerformanceMonitor); | |
305 | #endif | |
3dfa8773 KG |
306 | #ifdef CONFIG_PPC_E500MC |
307 | SET_IVOR(36, Doorbell); | |
308 | #endif | |
14cf11af PM |
309 | |
310 | /* Establish the interrupt vector base */ | |
311 | lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ | |
312 | mtspr SPRN_IVPR,r4 | |
313 | ||
314 | /* Setup the defaults for TLB entries */ | |
315 | li r2,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l | |
316 | #ifdef CONFIG_E200 | |
317 | oris r2,r2,MAS4_TLBSELD(1)@h | |
318 | #endif | |
3c5df5c2 | 319 | mtspr SPRN_MAS4, r2 |
14cf11af PM |
320 | |
321 | #if 0 | |
322 | /* Enable DOZE */ | |
323 | mfspr r2,SPRN_HID0 | |
324 | oris r2,r2,HID0_DOZE@h | |
325 | mtspr SPRN_HID0, r2 | |
326 | #endif | |
327 | #ifdef CONFIG_E200 | |
328 | /* enable dedicated debug exception handling resources (Debug APU) */ | |
329 | mfspr r2,SPRN_HID0 | |
3c5df5c2 | 330 | ori r2,r2,HID0_DAPUEN@l |
14cf11af PM |
331 | mtspr SPRN_HID0,r2 |
332 | #endif | |
333 | ||
334 | #if !defined(CONFIG_BDI_SWITCH) | |
335 | /* | |
336 | * The Abatron BDI JTAG debugger does not tolerate others | |
337 | * mucking with the debug registers. | |
338 | */ | |
339 | lis r2,DBCR0_IDM@h | |
340 | mtspr SPRN_DBCR0,r2 | |
a7cb0337 | 341 | isync |
14cf11af PM |
342 | /* clear any residual debug events */ |
343 | li r2,-1 | |
344 | mtspr SPRN_DBSR,r2 | |
345 | #endif | |
346 | ||
347 | /* | |
348 | * This is where the main kernel code starts. | |
349 | */ | |
350 | ||
351 | /* ptr to current */ | |
352 | lis r2,init_task@h | |
353 | ori r2,r2,init_task@l | |
354 | ||
355 | /* ptr to current thread */ | |
356 | addi r4,r2,THREAD /* init task's THREAD */ | |
357 | mtspr SPRN_SPRG3,r4 | |
358 | ||
359 | /* stack */ | |
360 | lis r1,init_thread_union@h | |
361 | ori r1,r1,init_thread_union@l | |
362 | li r0,0 | |
363 | stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) | |
364 | ||
365 | bl early_init | |
366 | ||
37dd2bad KG |
367 | #ifdef CONFIG_RELOCATABLE |
368 | lis r3,kernstart_addr@ha | |
369 | la r3,kernstart_addr@l(r3) | |
370 | #ifdef CONFIG_PHYS_64BIT | |
371 | stw r23,0(r3) | |
372 | stw r25,4(r3) | |
373 | #else | |
374 | stw r25,0(r3) | |
375 | #endif | |
376 | #endif | |
377 | ||
14cf11af PM |
378 | mfspr r3,SPRN_TLB1CFG |
379 | andi. r3,r3,0xfff | |
380 | lis r4,num_tlbcam_entries@ha | |
381 | stw r3,num_tlbcam_entries@l(r4) | |
382 | /* | |
383 | * Decide what sort of machine this is and initialize the MMU. | |
384 | */ | |
385 | mr r3,r31 | |
386 | mr r4,r30 | |
387 | mr r5,r29 | |
388 | mr r6,r28 | |
389 | mr r7,r27 | |
390 | bl machine_init | |
391 | bl MMU_init | |
392 | ||
393 | /* Setup PTE pointers for the Abatron bdiGDB */ | |
394 | lis r6, swapper_pg_dir@h | |
395 | ori r6, r6, swapper_pg_dir@l | |
396 | lis r5, abatron_pteptrs@h | |
397 | ori r5, r5, abatron_pteptrs@l | |
398 | lis r4, KERNELBASE@h | |
399 | ori r4, r4, KERNELBASE@l | |
400 | stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */ | |
401 | stw r6, 0(r5) | |
402 | ||
403 | /* Let's move on */ | |
404 | lis r4,start_kernel@h | |
405 | ori r4,r4,start_kernel@l | |
406 | lis r3,MSR_KERNEL@h | |
407 | ori r3,r3,MSR_KERNEL@l | |
408 | mtspr SPRN_SRR0,r4 | |
409 | mtspr SPRN_SRR1,r3 | |
410 | rfi /* change context and jump to start_kernel */ | |
411 | ||
412 | /* Macros to hide the PTE size differences | |
413 | * | |
414 | * FIND_PTE -- walks the page tables given EA & pgdir pointer | |
415 | * r10 -- EA of fault | |
416 | * r11 -- PGDIR pointer | |
417 | * r12 -- free | |
418 | * label 2: is the bailout case | |
419 | * | |
420 | * if we find the pte (fall through): | |
421 | * r11 is low pte word | |
422 | * r12 is pointer to the pte | |
423 | */ | |
424 | #ifdef CONFIG_PTE_64BIT | |
425 | #define PTE_FLAGS_OFFSET 4 | |
426 | #define FIND_PTE \ | |
3c5df5c2 | 427 | rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \ |
14cf11af PM |
428 | lwzx r11, r12, r11; /* Get pgd/pmd entry */ \ |
429 | rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \ | |
430 | beq 2f; /* Bail if no table */ \ | |
431 | rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \ | |
432 | lwz r11, 4(r12); /* Get pte entry */ | |
433 | #else | |
434 | #define PTE_FLAGS_OFFSET 0 | |
435 | #define FIND_PTE \ | |
436 | rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \ | |
437 | lwz r11, 0(r11); /* Get L1 entry */ \ | |
438 | rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \ | |
439 | beq 2f; /* Bail if no table */ \ | |
440 | rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \ | |
441 | lwz r11, 0(r12); /* Get Linux PTE */ | |
442 | #endif | |
443 | ||
444 | /* | |
445 | * Interrupt vector entry code | |
446 | * | |
447 | * The Book E MMUs are always on so we don't need to handle | |
448 | * interrupts in real mode as with previous PPC processors. In | |
449 | * this case we handle interrupts in the kernel virtual address | |
450 | * space. | |
451 | * | |
452 | * Interrupt vectors are dynamically placed relative to the | |
453 | * interrupt prefix as determined by the address of interrupt_base. | |
454 | * The interrupt vectors offsets are programmed using the labels | |
455 | * for each interrupt vector entry. | |
456 | * | |
457 | * Interrupt vectors must be aligned on a 16 byte boundary. | |
458 | * We align on a 32 byte cache line boundary for good measure. | |
459 | */ | |
460 | ||
461 | interrupt_base: | |
462 | /* Critical Input Interrupt */ | |
dc1c1ca3 | 463 | CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception) |
14cf11af PM |
464 | |
465 | /* Machine Check Interrupt */ | |
466 | #ifdef CONFIG_E200 | |
467 | /* no RFMCI, MCSRRs on E200 */ | |
dc1c1ca3 | 468 | CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception) |
14cf11af | 469 | #else |
dc1c1ca3 | 470 | MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception) |
14cf11af PM |
471 | #endif |
472 | ||
473 | /* Data Storage Interrupt */ | |
474 | START_EXCEPTION(DataStorage) | |
6cfd8990 KG |
475 | NORMAL_EXCEPTION_PROLOG |
476 | mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */ | |
477 | stw r5,_ESR(r11) | |
478 | mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */ | |
479 | andis. r10,r5,(ESR_ILK|ESR_DLK)@h | |
480 | bne 1f | |
481 | EXC_XFER_EE_LITE(0x0300, handle_page_fault) | |
482 | 1: | |
483 | addi r3,r1,STACK_FRAME_OVERHEAD | |
484 | EXC_XFER_EE_LITE(0x0300, CacheLockingException) | |
14cf11af PM |
485 | |
486 | /* Instruction Storage Interrupt */ | |
487 | INSTRUCTION_STORAGE_EXCEPTION | |
488 | ||
489 | /* External Input Interrupt */ | |
490 | EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE) | |
491 | ||
492 | /* Alignment Interrupt */ | |
493 | ALIGNMENT_EXCEPTION | |
494 | ||
495 | /* Program Interrupt */ | |
496 | PROGRAM_EXCEPTION | |
497 | ||
498 | /* Floating Point Unavailable Interrupt */ | |
499 | #ifdef CONFIG_PPC_FPU | |
500 | FP_UNAVAILABLE_EXCEPTION | |
501 | #else | |
502 | #ifdef CONFIG_E200 | |
503 | /* E200 treats 'normal' floating point instructions as FP Unavail exception */ | |
dc1c1ca3 | 504 | EXCEPTION(0x0800, FloatingPointUnavailable, program_check_exception, EXC_XFER_EE) |
14cf11af | 505 | #else |
dc1c1ca3 | 506 | EXCEPTION(0x0800, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE) |
14cf11af PM |
507 | #endif |
508 | #endif | |
509 | ||
510 | /* System Call Interrupt */ | |
511 | START_EXCEPTION(SystemCall) | |
512 | NORMAL_EXCEPTION_PROLOG | |
513 | EXC_XFER_EE_LITE(0x0c00, DoSyscall) | |
514 | ||
515 | /* Auxillary Processor Unavailable Interrupt */ | |
dc1c1ca3 | 516 | EXCEPTION(0x2900, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE) |
14cf11af PM |
517 | |
518 | /* Decrementer Interrupt */ | |
519 | DECREMENTER_EXCEPTION | |
520 | ||
521 | /* Fixed Internal Timer Interrupt */ | |
522 | /* TODO: Add FIT support */ | |
dc1c1ca3 | 523 | EXCEPTION(0x3100, FixedIntervalTimer, unknown_exception, EXC_XFER_EE) |
14cf11af PM |
524 | |
525 | /* Watchdog Timer Interrupt */ | |
526 | #ifdef CONFIG_BOOKE_WDT | |
527 | CRITICAL_EXCEPTION(0x3200, WatchdogTimer, WatchdogException) | |
528 | #else | |
dc1c1ca3 | 529 | CRITICAL_EXCEPTION(0x3200, WatchdogTimer, unknown_exception) |
14cf11af PM |
530 | #endif |
531 | ||
532 | /* Data TLB Error Interrupt */ | |
533 | START_EXCEPTION(DataTLBError) | |
534 | mtspr SPRN_SPRG0, r10 /* Save some working registers */ | |
535 | mtspr SPRN_SPRG1, r11 | |
536 | mtspr SPRN_SPRG4W, r12 | |
537 | mtspr SPRN_SPRG5W, r13 | |
538 | mfcr r11 | |
539 | mtspr SPRN_SPRG7W, r11 | |
540 | mfspr r10, SPRN_DEAR /* Get faulting address */ | |
541 | ||
542 | /* If we are faulting a kernel address, we have to use the | |
543 | * kernel page tables. | |
544 | */ | |
8a13c4f9 | 545 | lis r11, PAGE_OFFSET@h |
14cf11af PM |
546 | cmplw 5, r10, r11 |
547 | blt 5, 3f | |
548 | lis r11, swapper_pg_dir@h | |
549 | ori r11, r11, swapper_pg_dir@l | |
550 | ||
551 | mfspr r12,SPRN_MAS1 /* Set TID to 0 */ | |
552 | rlwinm r12,r12,0,16,1 | |
553 | mtspr SPRN_MAS1,r12 | |
554 | ||
555 | b 4f | |
556 | ||
557 | /* Get the PGD for the current thread */ | |
558 | 3: | |
559 | mfspr r11,SPRN_SPRG3 | |
560 | lwz r11,PGDIR(r11) | |
561 | ||
562 | 4: | |
6cfd8990 KG |
563 | /* Mask of required permission bits. Note that while we |
564 | * do copy ESR:ST to _PAGE_RW position as trying to write | |
565 | * to an RO page is pretty common, we don't do it with | |
566 | * _PAGE_DIRTY. We could do it, but it's a fairly rare | |
567 | * event so I'd rather take the overhead when it happens | |
568 | * rather than adding an instruction here. We should measure | |
569 | * whether the whole thing is worth it in the first place | |
570 | * as we could avoid loading SPRN_ESR completely in the first | |
571 | * place... | |
572 | * | |
573 | * TODO: Is it worth doing that mfspr & rlwimi in the first | |
574 | * place or can we save a couple of instructions here ? | |
575 | */ | |
576 | mfspr r12,SPRN_ESR | |
577 | li r13,_PAGE_PRESENT|_PAGE_ACCESSED | |
578 | rlwimi r13,r12,11,29,29 | |
579 | ||
14cf11af | 580 | FIND_PTE |
6cfd8990 KG |
581 | andc. r13,r13,r11 /* Check permission */ |
582 | bne 2f /* Bail if permission mismach */ | |
14cf11af PM |
583 | |
584 | #ifdef CONFIG_PTE_64BIT | |
585 | lwz r13, 0(r12) | |
586 | #endif | |
14cf11af PM |
587 | |
588 | /* Jump to common tlb load */ | |
589 | b finish_tlb_load | |
590 | 2: | |
591 | /* The bailout. Restore registers to pre-exception conditions | |
592 | * and call the heavyweights to help us out. | |
593 | */ | |
594 | mfspr r11, SPRN_SPRG7R | |
595 | mtcr r11 | |
596 | mfspr r13, SPRN_SPRG5R | |
597 | mfspr r12, SPRN_SPRG4R | |
598 | mfspr r11, SPRN_SPRG1 | |
599 | mfspr r10, SPRN_SPRG0 | |
6cfd8990 | 600 | b DataStorage |
14cf11af PM |
601 | |
602 | /* Instruction TLB Error Interrupt */ | |
603 | /* | |
604 | * Nearly the same as above, except we get our | |
605 | * information from different registers and bailout | |
606 | * to a different point. | |
607 | */ | |
608 | START_EXCEPTION(InstructionTLBError) | |
609 | mtspr SPRN_SPRG0, r10 /* Save some working registers */ | |
610 | mtspr SPRN_SPRG1, r11 | |
611 | mtspr SPRN_SPRG4W, r12 | |
612 | mtspr SPRN_SPRG5W, r13 | |
613 | mfcr r11 | |
614 | mtspr SPRN_SPRG7W, r11 | |
615 | mfspr r10, SPRN_SRR0 /* Get faulting address */ | |
616 | ||
617 | /* If we are faulting a kernel address, we have to use the | |
618 | * kernel page tables. | |
619 | */ | |
8a13c4f9 | 620 | lis r11, PAGE_OFFSET@h |
14cf11af PM |
621 | cmplw 5, r10, r11 |
622 | blt 5, 3f | |
623 | lis r11, swapper_pg_dir@h | |
624 | ori r11, r11, swapper_pg_dir@l | |
625 | ||
626 | mfspr r12,SPRN_MAS1 /* Set TID to 0 */ | |
627 | rlwinm r12,r12,0,16,1 | |
628 | mtspr SPRN_MAS1,r12 | |
629 | ||
630 | b 4f | |
631 | ||
632 | /* Get the PGD for the current thread */ | |
633 | 3: | |
634 | mfspr r11,SPRN_SPRG3 | |
635 | lwz r11,PGDIR(r11) | |
636 | ||
637 | 4: | |
6cfd8990 KG |
638 | /* Make up the required permissions */ |
639 | li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_HWEXEC | |
640 | ||
14cf11af | 641 | FIND_PTE |
6cfd8990 KG |
642 | andc. r13,r13,r11 /* Check permission */ |
643 | bne 2f /* Bail if permission mismach */ | |
14cf11af PM |
644 | |
645 | #ifdef CONFIG_PTE_64BIT | |
646 | lwz r13, 0(r12) | |
647 | #endif | |
14cf11af PM |
648 | |
649 | /* Jump to common TLB load point */ | |
650 | b finish_tlb_load | |
651 | ||
652 | 2: | |
653 | /* The bailout. Restore registers to pre-exception conditions | |
654 | * and call the heavyweights to help us out. | |
655 | */ | |
656 | mfspr r11, SPRN_SPRG7R | |
657 | mtcr r11 | |
658 | mfspr r13, SPRN_SPRG5R | |
659 | mfspr r12, SPRN_SPRG4R | |
660 | mfspr r11, SPRN_SPRG1 | |
661 | mfspr r10, SPRN_SPRG0 | |
662 | b InstructionStorage | |
663 | ||
664 | #ifdef CONFIG_SPE | |
665 | /* SPE Unavailable */ | |
666 | START_EXCEPTION(SPEUnavailable) | |
667 | NORMAL_EXCEPTION_PROLOG | |
668 | bne load_up_spe | |
3c5df5c2 | 669 | addi r3,r1,STACK_FRAME_OVERHEAD |
14cf11af PM |
670 | EXC_XFER_EE_LITE(0x2010, KernelSPE) |
671 | #else | |
dc1c1ca3 | 672 | EXCEPTION(0x2020, SPEUnavailable, unknown_exception, EXC_XFER_EE) |
14cf11af PM |
673 | #endif /* CONFIG_SPE */ |
674 | ||
675 | /* SPE Floating Point Data */ | |
676 | #ifdef CONFIG_SPE | |
677 | EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE); | |
678 | #else | |
dc1c1ca3 | 679 | EXCEPTION(0x2040, SPEFloatingPointData, unknown_exception, EXC_XFER_EE) |
14cf11af PM |
680 | #endif /* CONFIG_SPE */ |
681 | ||
682 | /* SPE Floating Point Round */ | |
dc1c1ca3 | 683 | EXCEPTION(0x2050, SPEFloatingPointRound, unknown_exception, EXC_XFER_EE) |
14cf11af PM |
684 | |
685 | /* Performance Monitor */ | |
dc1c1ca3 | 686 | EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD) |
14cf11af | 687 | |
3dfa8773 KG |
688 | #ifdef CONFIG_PPC_E500MC |
689 | EXCEPTION(0x2070, Doorbell, unknown_exception, EXC_XFER_EE) | |
690 | #endif | |
14cf11af PM |
691 | |
692 | /* Debug Interrupt */ | |
eb0cd5fd | 693 | DEBUG_DEBUG_EXCEPTION |
3dfa8773 | 694 | #if defined(CONFIG_E500) && !defined(CONFIG_PPC_E500MC) |
eb0cd5fd KG |
695 | DEBUG_CRIT_EXCEPTION |
696 | #endif | |
14cf11af PM |
697 | |
698 | /* | |
699 | * Local functions | |
700 | */ | |
701 | ||
14cf11af | 702 | /* |
14cf11af PM |
703 | * Both the instruction and data TLB miss get to this |
704 | * point to load the TLB. | |
3c5df5c2 KG |
705 | * r10 - EA of fault |
706 | * r11 - TLB (info from Linux PTE) | |
6cfd8990 KG |
707 | * r12 - available to use |
708 | * r13 - upper bits of PTE (if PTE_64BIT) or available to use | |
8a13c4f9 | 709 | * CR5 - results of addr >= PAGE_OFFSET |
14cf11af PM |
710 | * MAS0, MAS1 - loaded with proper value when we get here |
711 | * MAS2, MAS3 - will need additional info from Linux PTE | |
712 | * Upon exit, we reload everything and RFI. | |
713 | */ | |
714 | finish_tlb_load: | |
715 | /* | |
716 | * We set execute, because we don't have the granularity to | |
717 | * properly set this at the page level (Linux problem). | |
718 | * Many of these bits are software only. Bits we don't set | |
719 | * here we (properly should) assume have the appropriate value. | |
720 | */ | |
721 | ||
722 | mfspr r12, SPRN_MAS2 | |
723 | #ifdef CONFIG_PTE_64BIT | |
724 | rlwimi r12, r11, 26, 24, 31 /* extract ...WIMGE from pte */ | |
725 | #else | |
726 | rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */ | |
727 | #endif | |
728 | mtspr SPRN_MAS2, r12 | |
729 | ||
6cfd8990 KG |
730 | li r10, (_PAGE_HWEXEC | _PAGE_PRESENT) |
731 | rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */ | |
732 | and r12, r11, r10 | |
14cf11af | 733 | andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */ |
6cfd8990 KG |
734 | slwi r10, r12, 1 |
735 | or r10, r10, r12 | |
736 | iseleq r12, r12, r10 | |
737 | ||
14cf11af PM |
738 | #ifdef CONFIG_PTE_64BIT |
739 | 2: rlwimi r12, r13, 24, 0, 7 /* grab RPN[32:39] */ | |
740 | rlwimi r12, r11, 24, 8, 19 /* grab RPN[40:51] */ | |
741 | mtspr SPRN_MAS3, r12 | |
742 | BEGIN_FTR_SECTION | |
743 | srwi r10, r13, 8 /* grab RPN[8:31] */ | |
744 | mtspr SPRN_MAS7, r10 | |
745 | END_FTR_SECTION_IFSET(CPU_FTR_BIG_PHYS) | |
746 | #else | |
747 | 2: rlwimi r11, r12, 0, 20, 31 /* Extract RPN from PTE and merge with perms */ | |
748 | mtspr SPRN_MAS3, r11 | |
749 | #endif | |
750 | #ifdef CONFIG_E200 | |
751 | /* Round robin TLB1 entries assignment */ | |
752 | mfspr r12, SPRN_MAS0 | |
753 | ||
754 | /* Extract TLB1CFG(NENTRY) */ | |
755 | mfspr r11, SPRN_TLB1CFG | |
756 | andi. r11, r11, 0xfff | |
757 | ||
758 | /* Extract MAS0(NV) */ | |
759 | andi. r13, r12, 0xfff | |
760 | addi r13, r13, 1 | |
761 | cmpw 0, r13, r11 | |
762 | addi r12, r12, 1 | |
763 | ||
764 | /* check if we need to wrap */ | |
765 | blt 7f | |
766 | ||
767 | /* wrap back to first free tlbcam entry */ | |
768 | lis r13, tlbcam_index@ha | |
769 | lwz r13, tlbcam_index@l(r13) | |
770 | rlwimi r12, r13, 0, 20, 31 | |
771 | 7: | |
3c5df5c2 | 772 | mtspr SPRN_MAS0,r12 |
14cf11af PM |
773 | #endif /* CONFIG_E200 */ |
774 | ||
775 | tlbwe | |
776 | ||
777 | /* Done...restore registers and get out of here. */ | |
778 | mfspr r11, SPRN_SPRG7R | |
779 | mtcr r11 | |
780 | mfspr r13, SPRN_SPRG5R | |
781 | mfspr r12, SPRN_SPRG4R | |
782 | mfspr r11, SPRN_SPRG1 | |
783 | mfspr r10, SPRN_SPRG0 | |
784 | rfi /* Force context change */ | |
785 | ||
786 | #ifdef CONFIG_SPE | |
787 | /* Note that the SPE support is closely modeled after the AltiVec | |
788 | * support. Changes to one are likely to be applicable to the | |
789 | * other! */ | |
790 | load_up_spe: | |
791 | /* | |
792 | * Disable SPE for the task which had SPE previously, | |
793 | * and save its SPE registers in its thread_struct. | |
794 | * Enables SPE for use in the kernel on return. | |
795 | * On SMP we know the SPE units are free, since we give it up every | |
796 | * switch. -- Kumar | |
797 | */ | |
798 | mfmsr r5 | |
799 | oris r5,r5,MSR_SPE@h | |
800 | mtmsr r5 /* enable use of SPE now */ | |
801 | isync | |
802 | /* | |
803 | * For SMP, we don't do lazy SPE switching because it just gets too | |
804 | * horrendously complex, especially when a task switches from one CPU | |
805 | * to another. Instead we call giveup_spe in switch_to. | |
806 | */ | |
807 | #ifndef CONFIG_SMP | |
808 | lis r3,last_task_used_spe@ha | |
809 | lwz r4,last_task_used_spe@l(r3) | |
810 | cmpi 0,r4,0 | |
811 | beq 1f | |
812 | addi r4,r4,THREAD /* want THREAD of last_task_used_spe */ | |
813 | SAVE_32EVRS(0,r10,r4) | |
3c5df5c2 | 814 | evxor evr10, evr10, evr10 /* clear out evr10 */ |
14cf11af PM |
815 | evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */ |
816 | li r5,THREAD_ACC | |
3c5df5c2 | 817 | evstddx evr10, r4, r5 /* save off accumulator */ |
14cf11af PM |
818 | lwz r5,PT_REGS(r4) |
819 | lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
820 | lis r10,MSR_SPE@h | |
821 | andc r4,r4,r10 /* disable SPE for previous task */ | |
822 | stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
823 | 1: | |
3c5df5c2 | 824 | #endif /* !CONFIG_SMP */ |
14cf11af PM |
825 | /* enable use of SPE after return */ |
826 | oris r9,r9,MSR_SPE@h | |
827 | mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */ | |
828 | li r4,1 | |
829 | li r10,THREAD_ACC | |
830 | stw r4,THREAD_USED_SPE(r5) | |
831 | evlddx evr4,r10,r5 | |
832 | evmra evr4,evr4 | |
833 | REST_32EVRS(0,r10,r5) | |
834 | #ifndef CONFIG_SMP | |
835 | subi r4,r5,THREAD | |
836 | stw r4,last_task_used_spe@l(r3) | |
3c5df5c2 | 837 | #endif /* !CONFIG_SMP */ |
14cf11af PM |
838 | /* restore registers and return */ |
839 | 2: REST_4GPRS(3, r11) | |
840 | lwz r10,_CCR(r11) | |
841 | REST_GPR(1, r11) | |
842 | mtcr r10 | |
843 | lwz r10,_LINK(r11) | |
844 | mtlr r10 | |
845 | REST_GPR(10, r11) | |
846 | mtspr SPRN_SRR1,r9 | |
847 | mtspr SPRN_SRR0,r12 | |
848 | REST_GPR(9, r11) | |
849 | REST_GPR(12, r11) | |
850 | lwz r11,GPR11(r11) | |
14cf11af PM |
851 | rfi |
852 | ||
853 | /* | |
854 | * SPE unavailable trap from kernel - print a message, but let | |
855 | * the task use SPE in the kernel until it returns to user mode. | |
856 | */ | |
857 | KernelSPE: | |
858 | lwz r3,_MSR(r1) | |
859 | oris r3,r3,MSR_SPE@h | |
860 | stw r3,_MSR(r1) /* enable use of SPE after return */ | |
861 | lis r3,87f@h | |
862 | ori r3,r3,87f@l | |
863 | mr r4,r2 /* current */ | |
864 | lwz r5,_NIP(r1) | |
865 | bl printk | |
866 | b ret_from_except | |
867 | 87: .string "SPE used in kernel (task=%p, pc=%x) \n" | |
868 | .align 4,0 | |
869 | ||
870 | #endif /* CONFIG_SPE */ | |
871 | ||
872 | /* | |
873 | * Global functions | |
874 | */ | |
875 | ||
876 | /* | |
877 | * extern void loadcam_entry(unsigned int index) | |
878 | * | |
879 | * Load TLBCAM[index] entry in to the L2 CAM MMU | |
880 | */ | |
881 | _GLOBAL(loadcam_entry) | |
882 | lis r4,TLBCAM@ha | |
883 | addi r4,r4,TLBCAM@l | |
884 | mulli r5,r3,20 | |
885 | add r3,r5,r4 | |
886 | lwz r4,0(r3) | |
887 | mtspr SPRN_MAS0,r4 | |
888 | lwz r4,4(r3) | |
889 | mtspr SPRN_MAS1,r4 | |
890 | lwz r4,8(r3) | |
891 | mtspr SPRN_MAS2,r4 | |
892 | lwz r4,12(r3) | |
893 | mtspr SPRN_MAS3,r4 | |
894 | tlbwe | |
895 | isync | |
896 | blr | |
897 | ||
898 | /* | |
899 | * extern void giveup_altivec(struct task_struct *prev) | |
900 | * | |
901 | * The e500 core does not have an AltiVec unit. | |
902 | */ | |
903 | _GLOBAL(giveup_altivec) | |
904 | blr | |
905 | ||
906 | #ifdef CONFIG_SPE | |
907 | /* | |
908 | * extern void giveup_spe(struct task_struct *prev) | |
909 | * | |
910 | */ | |
911 | _GLOBAL(giveup_spe) | |
912 | mfmsr r5 | |
913 | oris r5,r5,MSR_SPE@h | |
14cf11af PM |
914 | mtmsr r5 /* enable use of SPE now */ |
915 | isync | |
916 | cmpi 0,r3,0 | |
917 | beqlr- /* if no previous owner, done */ | |
918 | addi r3,r3,THREAD /* want THREAD of task */ | |
919 | lwz r5,PT_REGS(r3) | |
920 | cmpi 0,r5,0 | |
921 | SAVE_32EVRS(0, r4, r3) | |
3c5df5c2 | 922 | evxor evr6, evr6, evr6 /* clear out evr6 */ |
14cf11af PM |
923 | evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */ |
924 | li r4,THREAD_ACC | |
3c5df5c2 | 925 | evstddx evr6, r4, r3 /* save off accumulator */ |
14cf11af PM |
926 | mfspr r6,SPRN_SPEFSCR |
927 | stw r6,THREAD_SPEFSCR(r3) /* save spefscr register value */ | |
928 | beq 1f | |
929 | lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
930 | lis r3,MSR_SPE@h | |
931 | andc r4,r4,r3 /* disable SPE for previous task */ | |
932 | stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
933 | 1: | |
934 | #ifndef CONFIG_SMP | |
935 | li r5,0 | |
936 | lis r4,last_task_used_spe@ha | |
937 | stw r5,last_task_used_spe@l(r4) | |
3c5df5c2 | 938 | #endif /* !CONFIG_SMP */ |
14cf11af PM |
939 | blr |
940 | #endif /* CONFIG_SPE */ | |
941 | ||
942 | /* | |
943 | * extern void giveup_fpu(struct task_struct *prev) | |
944 | * | |
945 | * Not all FSL Book-E cores have an FPU | |
946 | */ | |
947 | #ifndef CONFIG_PPC_FPU | |
948 | _GLOBAL(giveup_fpu) | |
949 | blr | |
950 | #endif | |
951 | ||
952 | /* | |
953 | * extern void abort(void) | |
954 | * | |
955 | * At present, this routine just applies a system reset. | |
956 | */ | |
957 | _GLOBAL(abort) | |
958 | li r13,0 | |
3c5df5c2 | 959 | mtspr SPRN_DBCR0,r13 /* disable all debug events */ |
a7cb0337 | 960 | isync |
14cf11af PM |
961 | mfmsr r13 |
962 | ori r13,r13,MSR_DE@l /* Enable Debug Events */ | |
963 | mtmsr r13 | |
a7cb0337 | 964 | isync |
3c5df5c2 KG |
965 | mfspr r13,SPRN_DBCR0 |
966 | lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h | |
967 | mtspr SPRN_DBCR0,r13 | |
a7cb0337 | 968 | isync |
14cf11af PM |
969 | |
970 | _GLOBAL(set_context) | |
971 | ||
972 | #ifdef CONFIG_BDI_SWITCH | |
973 | /* Context switch the PTE pointer for the Abatron BDI2000. | |
974 | * The PGDIR is the second parameter. | |
975 | */ | |
976 | lis r5, abatron_pteptrs@h | |
977 | ori r5, r5, abatron_pteptrs@l | |
978 | stw r4, 0x4(r5) | |
979 | #endif | |
980 | mtspr SPRN_PID,r3 | |
981 | isync /* Force context change */ | |
982 | blr | |
983 | ||
fc4033b2 KG |
984 | _GLOBAL(flush_dcache_L1) |
985 | mfspr r3,SPRN_L1CFG0 | |
986 | ||
987 | rlwinm r5,r3,9,3 /* Extract cache block size */ | |
988 | twlgti r5,1 /* Only 32 and 64 byte cache blocks | |
989 | * are currently defined. | |
990 | */ | |
991 | li r4,32 | |
992 | subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) - | |
993 | * log2(number of ways) | |
994 | */ | |
995 | slw r5,r4,r5 /* r5 = cache block size */ | |
996 | ||
997 | rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */ | |
998 | mulli r7,r7,13 /* An 8-way cache will require 13 | |
999 | * loads per set. | |
1000 | */ | |
1001 | slw r7,r7,r6 | |
1002 | ||
1003 | /* save off HID0 and set DCFA */ | |
1004 | mfspr r8,SPRN_HID0 | |
1005 | ori r9,r8,HID0_DCFA@l | |
1006 | mtspr SPRN_HID0,r9 | |
1007 | isync | |
1008 | ||
1009 | lis r4,KERNELBASE@h | |
1010 | mtctr r7 | |
1011 | ||
1012 | 1: lwz r3,0(r4) /* Load... */ | |
1013 | add r4,r4,r5 | |
1014 | bdnz 1b | |
1015 | ||
1016 | msync | |
1017 | lis r4,KERNELBASE@h | |
1018 | mtctr r7 | |
1019 | ||
1020 | 1: dcbf 0,r4 /* ...and flush. */ | |
1021 | add r4,r4,r5 | |
1022 | bdnz 1b | |
1023 | ||
1024 | /* restore HID0 */ | |
1025 | mtspr SPRN_HID0,r8 | |
1026 | isync | |
1027 | ||
1028 | blr | |
1029 | ||
14cf11af PM |
1030 | /* |
1031 | * We put a few things here that have to be page-aligned. This stuff | |
1032 | * goes at the beginning of the data segment, which is page-aligned. | |
1033 | */ | |
1034 | .data | |
ea703ce2 KG |
1035 | .align 12 |
1036 | .globl sdata | |
1037 | sdata: | |
1038 | .globl empty_zero_page | |
1039 | empty_zero_page: | |
14cf11af | 1040 | .space 4096 |
ea703ce2 KG |
1041 | .globl swapper_pg_dir |
1042 | swapper_pg_dir: | |
bee86f14 | 1043 | .space PGD_TABLE_SIZE |
14cf11af | 1044 | |
14cf11af PM |
1045 | /* |
1046 | * Room for two PTE pointers, usually the kernel and current user pointers | |
1047 | * to their respective root page table. | |
1048 | */ | |
1049 | abatron_pteptrs: | |
1050 | .space 8 |