Commit | Line | Data |
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14cf11af | 1 | /* |
14cf11af PM |
2 | * Kernel execution entry point code. |
3 | * | |
4 | * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> | |
3c5df5c2 | 5 | * Initial PowerPC version. |
14cf11af | 6 | * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> |
3c5df5c2 | 7 | * Rewritten for PReP |
14cf11af | 8 | * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> |
3c5df5c2 | 9 | * Low-level exception handers, MMU support, and rewrite. |
14cf11af | 10 | * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> |
3c5df5c2 | 11 | * PowerPC 8xx modifications. |
14cf11af | 12 | * Copyright (c) 1998-1999 TiVo, Inc. |
3c5df5c2 | 13 | * PowerPC 403GCX modifications. |
14cf11af | 14 | * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> |
3c5df5c2 | 15 | * PowerPC 403GCX/405GP modifications. |
14cf11af PM |
16 | * Copyright 2000 MontaVista Software Inc. |
17 | * PPC405 modifications | |
3c5df5c2 KG |
18 | * PowerPC 403GCX/405GP modifications. |
19 | * Author: MontaVista Software, Inc. | |
20 | * frank_rowand@mvista.com or source@mvista.com | |
21 | * debbie_chu@mvista.com | |
14cf11af | 22 | * Copyright 2002-2004 MontaVista Software, Inc. |
3c5df5c2 | 23 | * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org> |
14cf11af | 24 | * Copyright 2004 Freescale Semiconductor, Inc |
3c5df5c2 | 25 | * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org> |
14cf11af PM |
26 | * |
27 | * This program is free software; you can redistribute it and/or modify it | |
28 | * under the terms of the GNU General Public License as published by the | |
29 | * Free Software Foundation; either version 2 of the License, or (at your | |
30 | * option) any later version. | |
31 | */ | |
32 | ||
e7039845 | 33 | #include <linux/init.h> |
14cf11af PM |
34 | #include <linux/threads.h> |
35 | #include <asm/processor.h> | |
36 | #include <asm/page.h> | |
37 | #include <asm/mmu.h> | |
38 | #include <asm/pgtable.h> | |
39 | #include <asm/cputable.h> | |
40 | #include <asm/thread_info.h> | |
41 | #include <asm/ppc_asm.h> | |
42 | #include <asm/asm-offsets.h> | |
fc4033b2 | 43 | #include <asm/cache.h> |
46f52210 | 44 | #include <asm/ptrace.h> |
14cf11af PM |
45 | #include "head_booke.h" |
46 | ||
47 | /* As with the other PowerPC ports, it is expected that when code | |
48 | * execution begins here, the following registers contain valid, yet | |
49 | * optional, information: | |
50 | * | |
51 | * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) | |
52 | * r4 - Starting address of the init RAM disk | |
53 | * r5 - Ending address of the init RAM disk | |
54 | * r6 - Start of kernel command line string (e.g. "mem=128") | |
55 | * r7 - End of kernel command line string | |
56 | * | |
57 | */ | |
e7039845 | 58 | __HEAD |
748a7683 KG |
59 | _ENTRY(_stext); |
60 | _ENTRY(_start); | |
14cf11af PM |
61 | /* |
62 | * Reserve a word at a fixed location to store the address | |
63 | * of abatron_pteptrs | |
64 | */ | |
65 | nop | |
6dece0eb SW |
66 | |
67 | /* Translate device tree address to physical, save in r30/r31 */ | |
68 | mfmsr r16 | |
69 | mfspr r17,SPRN_PID | |
70 | rlwinm r17,r17,16,0x3fff0000 /* turn PID into MAS6[SPID] */ | |
71 | rlwimi r17,r16,28,0x00000001 /* turn MSR[DS] into MAS6[SAS] */ | |
72 | mtspr SPRN_MAS6,r17 | |
73 | ||
74 | tlbsx 0,r3 /* must succeed */ | |
75 | ||
76 | mfspr r16,SPRN_MAS1 | |
77 | mfspr r20,SPRN_MAS3 | |
78 | rlwinm r17,r16,25,0x1f /* r17 = log2(page size) */ | |
79 | li r18,1024 | |
80 | slw r18,r18,r17 /* r18 = page size */ | |
81 | addi r18,r18,-1 | |
82 | and r19,r3,r18 /* r19 = page offset */ | |
7d0d3ad5 MM |
83 | andc r31,r20,r18 /* r31 = page base */ |
84 | or r31,r31,r19 /* r31 = devtree phys addr */ | |
7c732cba | 85 | #ifdef CONFIG_PHYS_64BIT |
6dece0eb | 86 | mfspr r30,SPRN_MAS7 |
7c732cba | 87 | #endif |
6dece0eb SW |
88 | |
89 | li r25,0 /* phys kernel start (low) */ | |
90 | li r24,0 /* CPU number */ | |
91 | li r23,0 /* phys kernel start (high) */ | |
14cf11af PM |
92 | |
93 | /* We try to not make any assumptions about how the boot loader | |
94 | * setup or used the TLBs. We invalidate all mappings from the | |
95 | * boot loader and load a single entry in TLB1[0] to map the | |
e8b63761 DF |
96 | * first 64M of kernel memory. Any boot info passed from the |
97 | * bootloader needs to live in this first 64M. | |
14cf11af PM |
98 | * |
99 | * Requirement on bootloader: | |
100 | * - The page we're executing in needs to reside in TLB1 and | |
101 | * have IPROT=1. If not an invalidate broadcast could | |
102 | * evict the entry we're currently executing in. | |
103 | * | |
104 | * r3 = Index of TLB1 were executing in | |
105 | * r4 = Current MSR[IS] | |
106 | * r5 = Index of TLB1 temp mapping | |
107 | * | |
108 | * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0] | |
109 | * if needed | |
110 | */ | |
111 | ||
d5b26db2 | 112 | _ENTRY(__early_start) |
105c31df | 113 | |
b3df895a | 114 | #define ENTRY_MAPPING_BOOT_SETUP |
7c08ce71 | 115 | #include "fsl_booke_entry_mapping.S" |
b3df895a | 116 | #undef ENTRY_MAPPING_BOOT_SETUP |
14cf11af PM |
117 | |
118 | /* Establish the interrupt vector offsets */ | |
119 | SET_IVOR(0, CriticalInput); | |
120 | SET_IVOR(1, MachineCheck); | |
121 | SET_IVOR(2, DataStorage); | |
122 | SET_IVOR(3, InstructionStorage); | |
123 | SET_IVOR(4, ExternalInput); | |
124 | SET_IVOR(5, Alignment); | |
125 | SET_IVOR(6, Program); | |
126 | SET_IVOR(7, FloatingPointUnavailable); | |
127 | SET_IVOR(8, SystemCall); | |
128 | SET_IVOR(9, AuxillaryProcessorUnavailable); | |
129 | SET_IVOR(10, Decrementer); | |
130 | SET_IVOR(11, FixedIntervalTimer); | |
131 | SET_IVOR(12, WatchdogTimer); | |
132 | SET_IVOR(13, DataTLBError); | |
133 | SET_IVOR(14, InstructionTLBError); | |
eb0cd5fd | 134 | SET_IVOR(15, DebugCrit); |
14cf11af PM |
135 | |
136 | /* Establish the interrupt vector base */ | |
137 | lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ | |
138 | mtspr SPRN_IVPR,r4 | |
139 | ||
140 | /* Setup the defaults for TLB entries */ | |
d66c82ea | 141 | li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l |
14cf11af PM |
142 | #ifdef CONFIG_E200 |
143 | oris r2,r2,MAS4_TLBSELD(1)@h | |
144 | #endif | |
3c5df5c2 | 145 | mtspr SPRN_MAS4, r2 |
14cf11af PM |
146 | |
147 | #if 0 | |
148 | /* Enable DOZE */ | |
149 | mfspr r2,SPRN_HID0 | |
150 | oris r2,r2,HID0_DOZE@h | |
151 | mtspr SPRN_HID0, r2 | |
152 | #endif | |
14cf11af PM |
153 | |
154 | #if !defined(CONFIG_BDI_SWITCH) | |
155 | /* | |
156 | * The Abatron BDI JTAG debugger does not tolerate others | |
157 | * mucking with the debug registers. | |
158 | */ | |
159 | lis r2,DBCR0_IDM@h | |
160 | mtspr SPRN_DBCR0,r2 | |
a7cb0337 | 161 | isync |
14cf11af PM |
162 | /* clear any residual debug events */ |
163 | li r2,-1 | |
164 | mtspr SPRN_DBSR,r2 | |
165 | #endif | |
166 | ||
d5b26db2 KG |
167 | #ifdef CONFIG_SMP |
168 | /* Check to see if we're the second processor, and jump | |
169 | * to the secondary_start code if so | |
170 | */ | |
2ed38b23 MM |
171 | lis r24, boot_cpuid@h |
172 | ori r24, r24, boot_cpuid@l | |
173 | lwz r24, 0(r24) | |
174 | cmpwi r24, -1 | |
175 | mfspr r24,SPRN_PIR | |
d5b26db2 KG |
176 | bne __secondary_start |
177 | #endif | |
178 | ||
14cf11af PM |
179 | /* |
180 | * This is where the main kernel code starts. | |
181 | */ | |
182 | ||
183 | /* ptr to current */ | |
184 | lis r2,init_task@h | |
185 | ori r2,r2,init_task@l | |
186 | ||
187 | /* ptr to current thread */ | |
188 | addi r4,r2,THREAD /* init task's THREAD */ | |
ee43eb78 | 189 | mtspr SPRN_SPRG_THREAD,r4 |
14cf11af PM |
190 | |
191 | /* stack */ | |
192 | lis r1,init_thread_union@h | |
193 | ori r1,r1,init_thread_union@l | |
194 | li r0,0 | |
195 | stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) | |
196 | ||
9778b696 | 197 | CURRENT_THREAD_INFO(r22, r1) |
2ed38b23 MM |
198 | stw r24, TI_CPU(r22) |
199 | ||
14cf11af PM |
200 | bl early_init |
201 | ||
0f890c8d | 202 | #ifdef CONFIG_DYNAMIC_MEMSTART |
37dd2bad KG |
203 | lis r3,kernstart_addr@ha |
204 | la r3,kernstart_addr@l(r3) | |
205 | #ifdef CONFIG_PHYS_64BIT | |
206 | stw r23,0(r3) | |
207 | stw r25,4(r3) | |
208 | #else | |
209 | stw r25,0(r3) | |
210 | #endif | |
211 | #endif | |
212 | ||
14cf11af PM |
213 | /* |
214 | * Decide what sort of machine this is and initialize the MMU. | |
215 | */ | |
6dece0eb SW |
216 | mr r3,r30 |
217 | mr r4,r31 | |
14cf11af PM |
218 | bl machine_init |
219 | bl MMU_init | |
220 | ||
221 | /* Setup PTE pointers for the Abatron bdiGDB */ | |
222 | lis r6, swapper_pg_dir@h | |
223 | ori r6, r6, swapper_pg_dir@l | |
224 | lis r5, abatron_pteptrs@h | |
225 | ori r5, r5, abatron_pteptrs@l | |
226 | lis r4, KERNELBASE@h | |
227 | ori r4, r4, KERNELBASE@l | |
228 | stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */ | |
229 | stw r6, 0(r5) | |
230 | ||
231 | /* Let's move on */ | |
232 | lis r4,start_kernel@h | |
233 | ori r4,r4,start_kernel@l | |
234 | lis r3,MSR_KERNEL@h | |
235 | ori r3,r3,MSR_KERNEL@l | |
236 | mtspr SPRN_SRR0,r4 | |
237 | mtspr SPRN_SRR1,r3 | |
238 | rfi /* change context and jump to start_kernel */ | |
239 | ||
240 | /* Macros to hide the PTE size differences | |
241 | * | |
242 | * FIND_PTE -- walks the page tables given EA & pgdir pointer | |
243 | * r10 -- EA of fault | |
244 | * r11 -- PGDIR pointer | |
245 | * r12 -- free | |
246 | * label 2: is the bailout case | |
247 | * | |
248 | * if we find the pte (fall through): | |
249 | * r11 is low pte word | |
250 | * r12 is pointer to the pte | |
41151e77 | 251 | * r10 is the pshift from the PGD, if we're a hugepage |
14cf11af PM |
252 | */ |
253 | #ifdef CONFIG_PTE_64BIT | |
41151e77 BB |
254 | #ifdef CONFIG_HUGETLB_PAGE |
255 | #define FIND_PTE \ | |
256 | rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \ | |
257 | lwzx r11, r12, r11; /* Get pgd/pmd entry */ \ | |
258 | rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \ | |
259 | blt 1000f; /* Normal non-huge page */ \ | |
260 | beq 2f; /* Bail if no table */ \ | |
261 | oris r11, r11, PD_HUGE@h; /* Put back address bit */ \ | |
262 | andi. r10, r11, HUGEPD_SHIFT_MASK@l; /* extract size field */ \ | |
263 | xor r12, r10, r11; /* drop size bits from pointer */ \ | |
264 | b 1001f; \ | |
265 | 1000: rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \ | |
266 | li r10, 0; /* clear r10 */ \ | |
267 | 1001: lwz r11, 4(r12); /* Get pte entry */ | |
268 | #else | |
14cf11af | 269 | #define FIND_PTE \ |
3c5df5c2 | 270 | rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \ |
14cf11af PM |
271 | lwzx r11, r12, r11; /* Get pgd/pmd entry */ \ |
272 | rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \ | |
273 | beq 2f; /* Bail if no table */ \ | |
274 | rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \ | |
275 | lwz r11, 4(r12); /* Get pte entry */ | |
41151e77 BB |
276 | #endif /* HUGEPAGE */ |
277 | #else /* !PTE_64BIT */ | |
14cf11af PM |
278 | #define FIND_PTE \ |
279 | rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \ | |
280 | lwz r11, 0(r11); /* Get L1 entry */ \ | |
281 | rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \ | |
282 | beq 2f; /* Bail if no table */ \ | |
283 | rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \ | |
284 | lwz r11, 0(r12); /* Get Linux PTE */ | |
285 | #endif | |
286 | ||
287 | /* | |
288 | * Interrupt vector entry code | |
289 | * | |
290 | * The Book E MMUs are always on so we don't need to handle | |
291 | * interrupts in real mode as with previous PPC processors. In | |
292 | * this case we handle interrupts in the kernel virtual address | |
293 | * space. | |
294 | * | |
295 | * Interrupt vectors are dynamically placed relative to the | |
296 | * interrupt prefix as determined by the address of interrupt_base. | |
297 | * The interrupt vectors offsets are programmed using the labels | |
298 | * for each interrupt vector entry. | |
299 | * | |
300 | * Interrupt vectors must be aligned on a 16 byte boundary. | |
301 | * We align on a 32 byte cache line boundary for good measure. | |
302 | */ | |
303 | ||
304 | interrupt_base: | |
305 | /* Critical Input Interrupt */ | |
cfac5784 | 306 | CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception) |
14cf11af PM |
307 | |
308 | /* Machine Check Interrupt */ | |
309 | #ifdef CONFIG_E200 | |
310 | /* no RFMCI, MCSRRs on E200 */ | |
cfac5784 SW |
311 | CRITICAL_EXCEPTION(0x0200, MACHINE_CHECK, MachineCheck, \ |
312 | machine_check_exception) | |
14cf11af | 313 | #else |
dc1c1ca3 | 314 | MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception) |
14cf11af PM |
315 | #endif |
316 | ||
317 | /* Data Storage Interrupt */ | |
318 | START_EXCEPTION(DataStorage) | |
cfac5784 | 319 | NORMAL_EXCEPTION_PROLOG(DATA_STORAGE) |
6cfd8990 KG |
320 | mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */ |
321 | stw r5,_ESR(r11) | |
322 | mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */ | |
323 | andis. r10,r5,(ESR_ILK|ESR_DLK)@h | |
324 | bne 1f | |
a546498f | 325 | EXC_XFER_LITE(0x0300, handle_page_fault) |
6cfd8990 KG |
326 | 1: |
327 | addi r3,r1,STACK_FRAME_OVERHEAD | |
328 | EXC_XFER_EE_LITE(0x0300, CacheLockingException) | |
14cf11af PM |
329 | |
330 | /* Instruction Storage Interrupt */ | |
331 | INSTRUCTION_STORAGE_EXCEPTION | |
332 | ||
333 | /* External Input Interrupt */ | |
cfac5784 | 334 | EXCEPTION(0x0500, EXTERNAL, ExternalInput, do_IRQ, EXC_XFER_LITE) |
14cf11af PM |
335 | |
336 | /* Alignment Interrupt */ | |
337 | ALIGNMENT_EXCEPTION | |
338 | ||
339 | /* Program Interrupt */ | |
340 | PROGRAM_EXCEPTION | |
341 | ||
342 | /* Floating Point Unavailable Interrupt */ | |
343 | #ifdef CONFIG_PPC_FPU | |
344 | FP_UNAVAILABLE_EXCEPTION | |
345 | #else | |
346 | #ifdef CONFIG_E200 | |
347 | /* E200 treats 'normal' floating point instructions as FP Unavail exception */ | |
cfac5784 SW |
348 | EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \ |
349 | program_check_exception, EXC_XFER_EE) | |
14cf11af | 350 | #else |
cfac5784 SW |
351 | EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \ |
352 | unknown_exception, EXC_XFER_EE) | |
14cf11af PM |
353 | #endif |
354 | #endif | |
355 | ||
356 | /* System Call Interrupt */ | |
357 | START_EXCEPTION(SystemCall) | |
cfac5784 | 358 | NORMAL_EXCEPTION_PROLOG(SYSCALL) |
14cf11af PM |
359 | EXC_XFER_EE_LITE(0x0c00, DoSyscall) |
360 | ||
25985edc | 361 | /* Auxiliary Processor Unavailable Interrupt */ |
cfac5784 SW |
362 | EXCEPTION(0x2900, AP_UNAVAIL, AuxillaryProcessorUnavailable, \ |
363 | unknown_exception, EXC_XFER_EE) | |
14cf11af PM |
364 | |
365 | /* Decrementer Interrupt */ | |
366 | DECREMENTER_EXCEPTION | |
367 | ||
368 | /* Fixed Internal Timer Interrupt */ | |
369 | /* TODO: Add FIT support */ | |
cfac5784 SW |
370 | EXCEPTION(0x3100, FIT, FixedIntervalTimer, \ |
371 | unknown_exception, EXC_XFER_EE) | |
14cf11af PM |
372 | |
373 | /* Watchdog Timer Interrupt */ | |
374 | #ifdef CONFIG_BOOKE_WDT | |
cfac5784 | 375 | CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, WatchdogException) |
14cf11af | 376 | #else |
cfac5784 | 377 | CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, unknown_exception) |
14cf11af PM |
378 | #endif |
379 | ||
380 | /* Data TLB Error Interrupt */ | |
381 | START_EXCEPTION(DataTLBError) | |
ee43eb78 | 382 | mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */ |
1325a684 AK |
383 | mfspr r10, SPRN_SPRG_THREAD |
384 | stw r11, THREAD_NORMSAVE(0)(r10) | |
73196cd3 SW |
385 | #ifdef CONFIG_KVM_BOOKE_HV |
386 | BEGIN_FTR_SECTION | |
387 | mfspr r11, SPRN_SRR1 | |
388 | END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) | |
389 | #endif | |
1325a684 AK |
390 | stw r12, THREAD_NORMSAVE(1)(r10) |
391 | stw r13, THREAD_NORMSAVE(2)(r10) | |
392 | mfcr r13 | |
393 | stw r13, THREAD_NORMSAVE(3)(r10) | |
73196cd3 | 394 | DO_KVM BOOKE_INTERRUPT_DTLB_MISS SPRN_SRR1 |
14cf11af PM |
395 | mfspr r10, SPRN_DEAR /* Get faulting address */ |
396 | ||
397 | /* If we are faulting a kernel address, we have to use the | |
398 | * kernel page tables. | |
399 | */ | |
8a13c4f9 | 400 | lis r11, PAGE_OFFSET@h |
14cf11af PM |
401 | cmplw 5, r10, r11 |
402 | blt 5, 3f | |
403 | lis r11, swapper_pg_dir@h | |
404 | ori r11, r11, swapper_pg_dir@l | |
405 | ||
406 | mfspr r12,SPRN_MAS1 /* Set TID to 0 */ | |
407 | rlwinm r12,r12,0,16,1 | |
408 | mtspr SPRN_MAS1,r12 | |
409 | ||
410 | b 4f | |
411 | ||
412 | /* Get the PGD for the current thread */ | |
413 | 3: | |
ee43eb78 | 414 | mfspr r11,SPRN_SPRG_THREAD |
14cf11af PM |
415 | lwz r11,PGDIR(r11) |
416 | ||
417 | 4: | |
6cfd8990 KG |
418 | /* Mask of required permission bits. Note that while we |
419 | * do copy ESR:ST to _PAGE_RW position as trying to write | |
420 | * to an RO page is pretty common, we don't do it with | |
421 | * _PAGE_DIRTY. We could do it, but it's a fairly rare | |
422 | * event so I'd rather take the overhead when it happens | |
423 | * rather than adding an instruction here. We should measure | |
424 | * whether the whole thing is worth it in the first place | |
425 | * as we could avoid loading SPRN_ESR completely in the first | |
426 | * place... | |
427 | * | |
428 | * TODO: Is it worth doing that mfspr & rlwimi in the first | |
429 | * place or can we save a couple of instructions here ? | |
430 | */ | |
431 | mfspr r12,SPRN_ESR | |
76acc2c1 KG |
432 | #ifdef CONFIG_PTE_64BIT |
433 | li r13,_PAGE_PRESENT | |
434 | oris r13,r13,_PAGE_ACCESSED@h | |
435 | #else | |
6cfd8990 | 436 | li r13,_PAGE_PRESENT|_PAGE_ACCESSED |
76acc2c1 | 437 | #endif |
6cfd8990 KG |
438 | rlwimi r13,r12,11,29,29 |
439 | ||
14cf11af | 440 | FIND_PTE |
6cfd8990 | 441 | andc. r13,r13,r11 /* Check permission */ |
14cf11af PM |
442 | |
443 | #ifdef CONFIG_PTE_64BIT | |
b38fd42f | 444 | #ifdef CONFIG_SMP |
41151e77 BB |
445 | subf r13,r11,r12 /* create false data dep */ |
446 | lwzx r13,r11,r13 /* Get upper pte bits */ | |
b38fd42f KG |
447 | #else |
448 | lwz r13,0(r12) /* Get upper pte bits */ | |
449 | #endif | |
14cf11af | 450 | #endif |
14cf11af | 451 | |
b38fd42f KG |
452 | bne 2f /* Bail if permission/valid mismach */ |
453 | ||
454 | /* Jump to common tlb load */ | |
14cf11af PM |
455 | b finish_tlb_load |
456 | 2: | |
457 | /* The bailout. Restore registers to pre-exception conditions | |
458 | * and call the heavyweights to help us out. | |
459 | */ | |
1325a684 AK |
460 | mfspr r10, SPRN_SPRG_THREAD |
461 | lwz r11, THREAD_NORMSAVE(3)(r10) | |
14cf11af | 462 | mtcr r11 |
1325a684 AK |
463 | lwz r13, THREAD_NORMSAVE(2)(r10) |
464 | lwz r12, THREAD_NORMSAVE(1)(r10) | |
465 | lwz r11, THREAD_NORMSAVE(0)(r10) | |
ee43eb78 | 466 | mfspr r10, SPRN_SPRG_RSCRATCH0 |
6cfd8990 | 467 | b DataStorage |
14cf11af PM |
468 | |
469 | /* Instruction TLB Error Interrupt */ | |
470 | /* | |
471 | * Nearly the same as above, except we get our | |
472 | * information from different registers and bailout | |
473 | * to a different point. | |
474 | */ | |
475 | START_EXCEPTION(InstructionTLBError) | |
ee43eb78 | 476 | mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */ |
1325a684 AK |
477 | mfspr r10, SPRN_SPRG_THREAD |
478 | stw r11, THREAD_NORMSAVE(0)(r10) | |
73196cd3 SW |
479 | #ifdef CONFIG_KVM_BOOKE_HV |
480 | BEGIN_FTR_SECTION | |
481 | mfspr r11, SPRN_SRR1 | |
482 | END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) | |
483 | #endif | |
1325a684 AK |
484 | stw r12, THREAD_NORMSAVE(1)(r10) |
485 | stw r13, THREAD_NORMSAVE(2)(r10) | |
486 | mfcr r13 | |
487 | stw r13, THREAD_NORMSAVE(3)(r10) | |
73196cd3 | 488 | DO_KVM BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR1 |
14cf11af PM |
489 | mfspr r10, SPRN_SRR0 /* Get faulting address */ |
490 | ||
491 | /* If we are faulting a kernel address, we have to use the | |
492 | * kernel page tables. | |
493 | */ | |
8a13c4f9 | 494 | lis r11, PAGE_OFFSET@h |
14cf11af PM |
495 | cmplw 5, r10, r11 |
496 | blt 5, 3f | |
497 | lis r11, swapper_pg_dir@h | |
498 | ori r11, r11, swapper_pg_dir@l | |
499 | ||
500 | mfspr r12,SPRN_MAS1 /* Set TID to 0 */ | |
501 | rlwinm r12,r12,0,16,1 | |
502 | mtspr SPRN_MAS1,r12 | |
503 | ||
78e2e68a LY |
504 | /* Make up the required permissions for kernel code */ |
505 | #ifdef CONFIG_PTE_64BIT | |
506 | li r13,_PAGE_PRESENT | _PAGE_BAP_SX | |
507 | oris r13,r13,_PAGE_ACCESSED@h | |
508 | #else | |
509 | li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC | |
510 | #endif | |
14cf11af PM |
511 | b 4f |
512 | ||
513 | /* Get the PGD for the current thread */ | |
514 | 3: | |
ee43eb78 | 515 | mfspr r11,SPRN_SPRG_THREAD |
14cf11af PM |
516 | lwz r11,PGDIR(r11) |
517 | ||
78e2e68a | 518 | /* Make up the required permissions for user code */ |
76acc2c1 | 519 | #ifdef CONFIG_PTE_64BIT |
78e2e68a | 520 | li r13,_PAGE_PRESENT | _PAGE_BAP_UX |
76acc2c1 KG |
521 | oris r13,r13,_PAGE_ACCESSED@h |
522 | #else | |
ea3cc330 | 523 | li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC |
76acc2c1 | 524 | #endif |
6cfd8990 | 525 | |
78e2e68a | 526 | 4: |
14cf11af | 527 | FIND_PTE |
6cfd8990 | 528 | andc. r13,r13,r11 /* Check permission */ |
b38fd42f KG |
529 | |
530 | #ifdef CONFIG_PTE_64BIT | |
531 | #ifdef CONFIG_SMP | |
41151e77 BB |
532 | subf r13,r11,r12 /* create false data dep */ |
533 | lwzx r13,r11,r13 /* Get upper pte bits */ | |
b38fd42f KG |
534 | #else |
535 | lwz r13,0(r12) /* Get upper pte bits */ | |
536 | #endif | |
537 | #endif | |
538 | ||
6cfd8990 | 539 | bne 2f /* Bail if permission mismach */ |
14cf11af | 540 | |
14cf11af PM |
541 | /* Jump to common TLB load point */ |
542 | b finish_tlb_load | |
543 | ||
544 | 2: | |
545 | /* The bailout. Restore registers to pre-exception conditions | |
546 | * and call the heavyweights to help us out. | |
547 | */ | |
1325a684 AK |
548 | mfspr r10, SPRN_SPRG_THREAD |
549 | lwz r11, THREAD_NORMSAVE(3)(r10) | |
14cf11af | 550 | mtcr r11 |
1325a684 AK |
551 | lwz r13, THREAD_NORMSAVE(2)(r10) |
552 | lwz r12, THREAD_NORMSAVE(1)(r10) | |
553 | lwz r11, THREAD_NORMSAVE(0)(r10) | |
ee43eb78 | 554 | mfspr r10, SPRN_SPRG_RSCRATCH0 |
14cf11af PM |
555 | b InstructionStorage |
556 | ||
557 | #ifdef CONFIG_SPE | |
558 | /* SPE Unavailable */ | |
559 | START_EXCEPTION(SPEUnavailable) | |
c58ce397 | 560 | NORMAL_EXCEPTION_PROLOG(SPE_ALTIVEC_UNAVAIL) |
2dc3d4cc LY |
561 | beq 1f |
562 | bl load_up_spe | |
563 | b fast_exception_return | |
564 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
14cf11af PM |
565 | EXC_XFER_EE_LITE(0x2010, KernelSPE) |
566 | #else | |
c58ce397 | 567 | EXCEPTION(0x2020, SPE_ALTIVEC_UNAVAIL, SPEUnavailable, \ |
cfac5784 | 568 | unknown_exception, EXC_XFER_EE) |
14cf11af PM |
569 | #endif /* CONFIG_SPE */ |
570 | ||
571 | /* SPE Floating Point Data */ | |
572 | #ifdef CONFIG_SPE | |
c58ce397 MC |
573 | EXCEPTION(0x2030, SPE_FP_DATA_ALTIVEC_ASSIST, SPEFloatingPointData, |
574 | SPEFloatingPointException, EXC_XFER_EE) | |
14cf11af PM |
575 | |
576 | /* SPE Floating Point Round */ | |
cfac5784 SW |
577 | EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \ |
578 | SPEFloatingPointRoundException, EXC_XFER_EE) | |
6a800f36 | 579 | #else |
c58ce397 | 580 | EXCEPTION(0x2040, SPE_FP_DATA_ALTIVEC_ASSIST, SPEFloatingPointData, |
cfac5784 SW |
581 | unknown_exception, EXC_XFER_EE) |
582 | EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \ | |
583 | unknown_exception, EXC_XFER_EE) | |
6a800f36 | 584 | #endif /* CONFIG_SPE */ |
14cf11af PM |
585 | |
586 | /* Performance Monitor */ | |
cfac5784 SW |
587 | EXCEPTION(0x2060, PERFORMANCE_MONITOR, PerformanceMonitor, \ |
588 | performance_monitor_exception, EXC_XFER_STD) | |
14cf11af | 589 | |
cfac5784 | 590 | EXCEPTION(0x2070, DOORBELL, Doorbell, doorbell_exception, EXC_XFER_STD) |
620165f9 | 591 | |
cfac5784 SW |
592 | CRITICAL_EXCEPTION(0x2080, DOORBELL_CRITICAL, \ |
593 | CriticalDoorbell, unknown_exception) | |
14cf11af PM |
594 | |
595 | /* Debug Interrupt */ | |
eb0cd5fd | 596 | DEBUG_DEBUG_EXCEPTION |
eb0cd5fd | 597 | DEBUG_CRIT_EXCEPTION |
14cf11af | 598 | |
73196cd3 SW |
599 | GUEST_DOORBELL_EXCEPTION |
600 | ||
601 | CRITICAL_EXCEPTION(0, GUEST_DBELL_CRIT, CriticalGuestDoorbell, \ | |
602 | unknown_exception) | |
603 | ||
604 | /* Hypercall */ | |
605 | EXCEPTION(0, HV_SYSCALL, Hypercall, unknown_exception, EXC_XFER_EE) | |
606 | ||
607 | /* Embedded Hypervisor Privilege */ | |
608 | EXCEPTION(0, HV_PRIV, Ehvpriv, unknown_exception, EXC_XFER_EE) | |
609 | ||
fc2a6cfe BB |
610 | interrupt_end: |
611 | ||
14cf11af PM |
612 | /* |
613 | * Local functions | |
614 | */ | |
615 | ||
14cf11af | 616 | /* |
14cf11af PM |
617 | * Both the instruction and data TLB miss get to this |
618 | * point to load the TLB. | |
41151e77 | 619 | * r10 - tsize encoding (if HUGETLB_PAGE) or available to use |
3c5df5c2 | 620 | * r11 - TLB (info from Linux PTE) |
6cfd8990 KG |
621 | * r12 - available to use |
622 | * r13 - upper bits of PTE (if PTE_64BIT) or available to use | |
8a13c4f9 | 623 | * CR5 - results of addr >= PAGE_OFFSET |
14cf11af PM |
624 | * MAS0, MAS1 - loaded with proper value when we get here |
625 | * MAS2, MAS3 - will need additional info from Linux PTE | |
626 | * Upon exit, we reload everything and RFI. | |
627 | */ | |
628 | finish_tlb_load: | |
41151e77 BB |
629 | #ifdef CONFIG_HUGETLB_PAGE |
630 | cmpwi 6, r10, 0 /* check for huge page */ | |
631 | beq 6, finish_tlb_load_cont /* !huge */ | |
632 | ||
633 | /* Alas, we need more scratch registers for hugepages */ | |
634 | mfspr r12, SPRN_SPRG_THREAD | |
635 | stw r14, THREAD_NORMSAVE(4)(r12) | |
636 | stw r15, THREAD_NORMSAVE(5)(r12) | |
637 | stw r16, THREAD_NORMSAVE(6)(r12) | |
638 | stw r17, THREAD_NORMSAVE(7)(r12) | |
639 | ||
640 | /* Get the next_tlbcam_idx percpu var */ | |
641 | #ifdef CONFIG_SMP | |
642 | lwz r12, THREAD_INFO-THREAD(r12) | |
643 | lwz r15, TI_CPU(r12) | |
644 | lis r14, __per_cpu_offset@h | |
645 | ori r14, r14, __per_cpu_offset@l | |
646 | rlwinm r15, r15, 2, 0, 29 | |
647 | lwzx r16, r14, r15 | |
648 | #else | |
649 | li r16, 0 | |
650 | #endif | |
651 | lis r17, next_tlbcam_idx@h | |
652 | ori r17, r17, next_tlbcam_idx@l | |
653 | add r17, r17, r16 /* r17 = *next_tlbcam_idx */ | |
654 | lwz r15, 0(r17) /* r15 = next_tlbcam_idx */ | |
655 | ||
656 | lis r14, MAS0_TLBSEL(1)@h /* select TLB1 (TLBCAM) */ | |
657 | rlwimi r14, r15, 16, 4, 15 /* next_tlbcam_idx entry */ | |
658 | mtspr SPRN_MAS0, r14 | |
659 | ||
660 | /* Extract TLB1CFG(NENTRY) */ | |
661 | mfspr r16, SPRN_TLB1CFG | |
662 | andi. r16, r16, 0xfff | |
663 | ||
664 | /* Update next_tlbcam_idx, wrapping when necessary */ | |
665 | addi r15, r15, 1 | |
666 | cmpw r15, r16 | |
667 | blt 100f | |
668 | lis r14, tlbcam_index@h | |
669 | ori r14, r14, tlbcam_index@l | |
670 | lwz r15, 0(r14) | |
671 | 100: stw r15, 0(r17) | |
672 | ||
673 | /* | |
674 | * Calc MAS1_TSIZE from r10 (which has pshift encoded) | |
675 | * tlb_enc = (pshift - 10). | |
676 | */ | |
677 | subi r15, r10, 10 | |
678 | mfspr r16, SPRN_MAS1 | |
679 | rlwimi r16, r15, 7, 20, 24 | |
680 | mtspr SPRN_MAS1, r16 | |
681 | ||
682 | /* copy the pshift for use later */ | |
683 | mr r14, r10 | |
684 | ||
685 | /* fall through */ | |
686 | ||
687 | #endif /* CONFIG_HUGETLB_PAGE */ | |
688 | ||
14cf11af PM |
689 | /* |
690 | * We set execute, because we don't have the granularity to | |
691 | * properly set this at the page level (Linux problem). | |
692 | * Many of these bits are software only. Bits we don't set | |
693 | * here we (properly should) assume have the appropriate value. | |
694 | */ | |
41151e77 | 695 | finish_tlb_load_cont: |
76acc2c1 KG |
696 | #ifdef CONFIG_PTE_64BIT |
697 | rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */ | |
698 | andi. r10, r11, _PAGE_DIRTY | |
699 | bne 1f | |
700 | li r10, MAS3_SW | MAS3_UW | |
701 | andc r12, r12, r10 | |
702 | 1: rlwimi r12, r13, 20, 0, 11 /* grab RPN[32:43] */ | |
703 | rlwimi r12, r11, 20, 12, 19 /* grab RPN[44:51] */ | |
41151e77 | 704 | 2: mtspr SPRN_MAS3, r12 |
76acc2c1 KG |
705 | BEGIN_MMU_FTR_SECTION |
706 | srwi r10, r13, 12 /* grab RPN[12:31] */ | |
707 | mtspr SPRN_MAS7, r10 | |
708 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS) | |
709 | #else | |
ea3cc330 | 710 | li r10, (_PAGE_EXEC | _PAGE_PRESENT) |
41151e77 | 711 | mr r13, r11 |
6cfd8990 KG |
712 | rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */ |
713 | and r12, r11, r10 | |
14cf11af | 714 | andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */ |
6cfd8990 KG |
715 | slwi r10, r12, 1 |
716 | or r10, r10, r12 | |
717 | iseleq r12, r12, r10 | |
41151e77 BB |
718 | rlwimi r13, r12, 0, 20, 31 /* Get RPN from PTE, merge w/ perms */ |
719 | mtspr SPRN_MAS3, r13 | |
14cf11af | 720 | #endif |
41151e77 BB |
721 | |
722 | mfspr r12, SPRN_MAS2 | |
723 | #ifdef CONFIG_PTE_64BIT | |
724 | rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */ | |
725 | #else | |
726 | rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */ | |
727 | #endif | |
728 | #ifdef CONFIG_HUGETLB_PAGE | |
729 | beq 6, 3f /* don't mask if page isn't huge */ | |
730 | li r13, 1 | |
731 | slw r13, r13, r14 | |
732 | subi r13, r13, 1 | |
733 | rlwinm r13, r13, 0, 0, 19 /* bottom bits used for WIMGE/etc */ | |
734 | andc r12, r12, r13 /* mask off ea bits within the page */ | |
735 | #endif | |
736 | 3: mtspr SPRN_MAS2, r12 | |
737 | ||
14cf11af PM |
738 | #ifdef CONFIG_E200 |
739 | /* Round robin TLB1 entries assignment */ | |
740 | mfspr r12, SPRN_MAS0 | |
741 | ||
742 | /* Extract TLB1CFG(NENTRY) */ | |
743 | mfspr r11, SPRN_TLB1CFG | |
744 | andi. r11, r11, 0xfff | |
745 | ||
746 | /* Extract MAS0(NV) */ | |
747 | andi. r13, r12, 0xfff | |
748 | addi r13, r13, 1 | |
749 | cmpw 0, r13, r11 | |
750 | addi r12, r12, 1 | |
751 | ||
752 | /* check if we need to wrap */ | |
753 | blt 7f | |
754 | ||
755 | /* wrap back to first free tlbcam entry */ | |
756 | lis r13, tlbcam_index@ha | |
757 | lwz r13, tlbcam_index@l(r13) | |
758 | rlwimi r12, r13, 0, 20, 31 | |
759 | 7: | |
3c5df5c2 | 760 | mtspr SPRN_MAS0,r12 |
14cf11af PM |
761 | #endif /* CONFIG_E200 */ |
762 | ||
41151e77 | 763 | tlb_write_entry: |
14cf11af PM |
764 | tlbwe |
765 | ||
766 | /* Done...restore registers and get out of here. */ | |
1325a684 | 767 | mfspr r10, SPRN_SPRG_THREAD |
41151e77 BB |
768 | #ifdef CONFIG_HUGETLB_PAGE |
769 | beq 6, 8f /* skip restore for 4k page faults */ | |
770 | lwz r14, THREAD_NORMSAVE(4)(r10) | |
771 | lwz r15, THREAD_NORMSAVE(5)(r10) | |
772 | lwz r16, THREAD_NORMSAVE(6)(r10) | |
773 | lwz r17, THREAD_NORMSAVE(7)(r10) | |
774 | #endif | |
775 | 8: lwz r11, THREAD_NORMSAVE(3)(r10) | |
14cf11af | 776 | mtcr r11 |
1325a684 AK |
777 | lwz r13, THREAD_NORMSAVE(2)(r10) |
778 | lwz r12, THREAD_NORMSAVE(1)(r10) | |
779 | lwz r11, THREAD_NORMSAVE(0)(r10) | |
ee43eb78 | 780 | mfspr r10, SPRN_SPRG_RSCRATCH0 |
14cf11af PM |
781 | rfi /* Force context change */ |
782 | ||
783 | #ifdef CONFIG_SPE | |
784 | /* Note that the SPE support is closely modeled after the AltiVec | |
785 | * support. Changes to one are likely to be applicable to the | |
786 | * other! */ | |
2dc3d4cc | 787 | _GLOBAL(load_up_spe) |
14cf11af PM |
788 | /* |
789 | * Disable SPE for the task which had SPE previously, | |
790 | * and save its SPE registers in its thread_struct. | |
791 | * Enables SPE for use in the kernel on return. | |
792 | * On SMP we know the SPE units are free, since we give it up every | |
793 | * switch. -- Kumar | |
794 | */ | |
795 | mfmsr r5 | |
796 | oris r5,r5,MSR_SPE@h | |
797 | mtmsr r5 /* enable use of SPE now */ | |
798 | isync | |
799 | /* | |
800 | * For SMP, we don't do lazy SPE switching because it just gets too | |
801 | * horrendously complex, especially when a task switches from one CPU | |
802 | * to another. Instead we call giveup_spe in switch_to. | |
803 | */ | |
804 | #ifndef CONFIG_SMP | |
805 | lis r3,last_task_used_spe@ha | |
806 | lwz r4,last_task_used_spe@l(r3) | |
807 | cmpi 0,r4,0 | |
808 | beq 1f | |
809 | addi r4,r4,THREAD /* want THREAD of last_task_used_spe */ | |
c51584d5 | 810 | SAVE_32EVRS(0,r10,r4,THREAD_EVR0) |
3c5df5c2 | 811 | evxor evr10, evr10, evr10 /* clear out evr10 */ |
14cf11af PM |
812 | evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */ |
813 | li r5,THREAD_ACC | |
3c5df5c2 | 814 | evstddx evr10, r4, r5 /* save off accumulator */ |
14cf11af PM |
815 | lwz r5,PT_REGS(r4) |
816 | lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
817 | lis r10,MSR_SPE@h | |
818 | andc r4,r4,r10 /* disable SPE for previous task */ | |
819 | stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
820 | 1: | |
3c5df5c2 | 821 | #endif /* !CONFIG_SMP */ |
14cf11af PM |
822 | /* enable use of SPE after return */ |
823 | oris r9,r9,MSR_SPE@h | |
ee43eb78 | 824 | mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ |
14cf11af PM |
825 | li r4,1 |
826 | li r10,THREAD_ACC | |
827 | stw r4,THREAD_USED_SPE(r5) | |
828 | evlddx evr4,r10,r5 | |
829 | evmra evr4,evr4 | |
c51584d5 | 830 | REST_32EVRS(0,r10,r5,THREAD_EVR0) |
14cf11af PM |
831 | #ifndef CONFIG_SMP |
832 | subi r4,r5,THREAD | |
833 | stw r4,last_task_used_spe@l(r3) | |
3c5df5c2 | 834 | #endif /* !CONFIG_SMP */ |
2dc3d4cc | 835 | blr |
14cf11af PM |
836 | |
837 | /* | |
838 | * SPE unavailable trap from kernel - print a message, but let | |
839 | * the task use SPE in the kernel until it returns to user mode. | |
840 | */ | |
841 | KernelSPE: | |
842 | lwz r3,_MSR(r1) | |
843 | oris r3,r3,MSR_SPE@h | |
844 | stw r3,_MSR(r1) /* enable use of SPE after return */ | |
09156a7a | 845 | #ifdef CONFIG_PRINTK |
14cf11af PM |
846 | lis r3,87f@h |
847 | ori r3,r3,87f@l | |
848 | mr r4,r2 /* current */ | |
849 | lwz r5,_NIP(r1) | |
850 | bl printk | |
09156a7a | 851 | #endif |
14cf11af | 852 | b ret_from_except |
09156a7a | 853 | #ifdef CONFIG_PRINTK |
14cf11af | 854 | 87: .string "SPE used in kernel (task=%p, pc=%x) \n" |
09156a7a | 855 | #endif |
14cf11af PM |
856 | .align 4,0 |
857 | ||
858 | #endif /* CONFIG_SPE */ | |
859 | ||
860 | /* | |
861 | * Global functions | |
862 | */ | |
863 | ||
105c31df KG |
864 | /* Adjust or setup IVORs for e200 */ |
865 | _GLOBAL(__setup_e200_ivors) | |
866 | li r3,DebugDebug@l | |
867 | mtspr SPRN_IVOR15,r3 | |
868 | li r3,SPEUnavailable@l | |
869 | mtspr SPRN_IVOR32,r3 | |
870 | li r3,SPEFloatingPointData@l | |
871 | mtspr SPRN_IVOR33,r3 | |
872 | li r3,SPEFloatingPointRound@l | |
873 | mtspr SPRN_IVOR34,r3 | |
874 | sync | |
875 | blr | |
876 | ||
877 | /* Adjust or setup IVORs for e500v1/v2 */ | |
878 | _GLOBAL(__setup_e500_ivors) | |
879 | li r3,DebugCrit@l | |
880 | mtspr SPRN_IVOR15,r3 | |
881 | li r3,SPEUnavailable@l | |
882 | mtspr SPRN_IVOR32,r3 | |
883 | li r3,SPEFloatingPointData@l | |
884 | mtspr SPRN_IVOR33,r3 | |
885 | li r3,SPEFloatingPointRound@l | |
886 | mtspr SPRN_IVOR34,r3 | |
887 | li r3,PerformanceMonitor@l | |
888 | mtspr SPRN_IVOR35,r3 | |
889 | sync | |
890 | blr | |
891 | ||
892 | /* Adjust or setup IVORs for e500mc */ | |
893 | _GLOBAL(__setup_e500mc_ivors) | |
894 | li r3,DebugDebug@l | |
895 | mtspr SPRN_IVOR15,r3 | |
896 | li r3,PerformanceMonitor@l | |
897 | mtspr SPRN_IVOR35,r3 | |
898 | li r3,Doorbell@l | |
899 | mtspr SPRN_IVOR36,r3 | |
620165f9 KG |
900 | li r3,CriticalDoorbell@l |
901 | mtspr SPRN_IVOR37,r3 | |
7e0f4872 VS |
902 | sync |
903 | blr | |
73196cd3 | 904 | |
7e0f4872 VS |
905 | /* setup ehv ivors for */ |
906 | _GLOBAL(__setup_ehv_ivors) | |
73196cd3 SW |
907 | li r3,GuestDoorbell@l |
908 | mtspr SPRN_IVOR38,r3 | |
909 | li r3,CriticalGuestDoorbell@l | |
910 | mtspr SPRN_IVOR39,r3 | |
911 | li r3,Hypercall@l | |
912 | mtspr SPRN_IVOR40,r3 | |
913 | li r3,Ehvpriv@l | |
914 | mtspr SPRN_IVOR41,r3 | |
105c31df KG |
915 | sync |
916 | blr | |
917 | ||
14cf11af PM |
918 | #ifdef CONFIG_SPE |
919 | /* | |
920 | * extern void giveup_spe(struct task_struct *prev) | |
921 | * | |
922 | */ | |
923 | _GLOBAL(giveup_spe) | |
924 | mfmsr r5 | |
925 | oris r5,r5,MSR_SPE@h | |
14cf11af PM |
926 | mtmsr r5 /* enable use of SPE now */ |
927 | isync | |
928 | cmpi 0,r3,0 | |
929 | beqlr- /* if no previous owner, done */ | |
930 | addi r3,r3,THREAD /* want THREAD of task */ | |
931 | lwz r5,PT_REGS(r3) | |
932 | cmpi 0,r5,0 | |
c51584d5 | 933 | SAVE_32EVRS(0, r4, r3, THREAD_EVR0) |
3c5df5c2 | 934 | evxor evr6, evr6, evr6 /* clear out evr6 */ |
14cf11af PM |
935 | evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */ |
936 | li r4,THREAD_ACC | |
3c5df5c2 | 937 | evstddx evr6, r4, r3 /* save off accumulator */ |
14cf11af PM |
938 | beq 1f |
939 | lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
940 | lis r3,MSR_SPE@h | |
941 | andc r4,r4,r3 /* disable SPE for previous task */ | |
942 | stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
943 | 1: | |
944 | #ifndef CONFIG_SMP | |
945 | li r5,0 | |
946 | lis r4,last_task_used_spe@ha | |
947 | stw r5,last_task_used_spe@l(r4) | |
3c5df5c2 | 948 | #endif /* !CONFIG_SMP */ |
14cf11af PM |
949 | blr |
950 | #endif /* CONFIG_SPE */ | |
951 | ||
14cf11af PM |
952 | /* |
953 | * extern void abort(void) | |
954 | * | |
955 | * At present, this routine just applies a system reset. | |
956 | */ | |
957 | _GLOBAL(abort) | |
958 | li r13,0 | |
3c5df5c2 | 959 | mtspr SPRN_DBCR0,r13 /* disable all debug events */ |
a7cb0337 | 960 | isync |
14cf11af PM |
961 | mfmsr r13 |
962 | ori r13,r13,MSR_DE@l /* Enable Debug Events */ | |
963 | mtmsr r13 | |
a7cb0337 | 964 | isync |
3c5df5c2 KG |
965 | mfspr r13,SPRN_DBCR0 |
966 | lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h | |
967 | mtspr SPRN_DBCR0,r13 | |
a7cb0337 | 968 | isync |
14cf11af PM |
969 | |
970 | _GLOBAL(set_context) | |
971 | ||
972 | #ifdef CONFIG_BDI_SWITCH | |
973 | /* Context switch the PTE pointer for the Abatron BDI2000. | |
974 | * The PGDIR is the second parameter. | |
975 | */ | |
976 | lis r5, abatron_pteptrs@h | |
977 | ori r5, r5, abatron_pteptrs@l | |
978 | stw r4, 0x4(r5) | |
979 | #endif | |
980 | mtspr SPRN_PID,r3 | |
981 | isync /* Force context change */ | |
982 | blr | |
983 | ||
fc4033b2 KG |
984 | _GLOBAL(flush_dcache_L1) |
985 | mfspr r3,SPRN_L1CFG0 | |
986 | ||
987 | rlwinm r5,r3,9,3 /* Extract cache block size */ | |
988 | twlgti r5,1 /* Only 32 and 64 byte cache blocks | |
989 | * are currently defined. | |
990 | */ | |
991 | li r4,32 | |
992 | subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) - | |
993 | * log2(number of ways) | |
994 | */ | |
995 | slw r5,r4,r5 /* r5 = cache block size */ | |
996 | ||
997 | rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */ | |
998 | mulli r7,r7,13 /* An 8-way cache will require 13 | |
999 | * loads per set. | |
1000 | */ | |
1001 | slw r7,r7,r6 | |
1002 | ||
1003 | /* save off HID0 and set DCFA */ | |
1004 | mfspr r8,SPRN_HID0 | |
1005 | ori r9,r8,HID0_DCFA@l | |
1006 | mtspr SPRN_HID0,r9 | |
1007 | isync | |
1008 | ||
1009 | lis r4,KERNELBASE@h | |
1010 | mtctr r7 | |
1011 | ||
1012 | 1: lwz r3,0(r4) /* Load... */ | |
1013 | add r4,r4,r5 | |
1014 | bdnz 1b | |
1015 | ||
1016 | msync | |
1017 | lis r4,KERNELBASE@h | |
1018 | mtctr r7 | |
1019 | ||
1020 | 1: dcbf 0,r4 /* ...and flush. */ | |
1021 | add r4,r4,r5 | |
1022 | bdnz 1b | |
1023 | ||
1024 | /* restore HID0 */ | |
1025 | mtspr SPRN_HID0,r8 | |
1026 | isync | |
1027 | ||
1028 | blr | |
1029 | ||
d0832a75 ZC |
1030 | /* Flush L1 d-cache, invalidate and disable d-cache and i-cache */ |
1031 | _GLOBAL(__flush_disable_L1) | |
1032 | mflr r10 | |
1033 | bl flush_dcache_L1 /* Flush L1 d-cache */ | |
1034 | mtlr r10 | |
1035 | ||
1036 | mfspr r4, SPRN_L1CSR0 /* Invalidate and disable d-cache */ | |
1037 | li r5, 2 | |
1038 | rlwimi r4, r5, 0, 3 | |
1039 | ||
1040 | msync | |
1041 | isync | |
1042 | mtspr SPRN_L1CSR0, r4 | |
1043 | isync | |
1044 | ||
1045 | 1: mfspr r4, SPRN_L1CSR0 /* Wait for the invalidate to finish */ | |
1046 | andi. r4, r4, 2 | |
1047 | bne 1b | |
1048 | ||
1049 | mfspr r4, SPRN_L1CSR1 /* Invalidate and disable i-cache */ | |
1050 | li r5, 2 | |
1051 | rlwimi r4, r5, 0, 3 | |
1052 | ||
1053 | mtspr SPRN_L1CSR1, r4 | |
1054 | isync | |
1055 | ||
1056 | blr | |
1057 | ||
d5b26db2 KG |
1058 | #ifdef CONFIG_SMP |
1059 | /* When we get here, r24 needs to hold the CPU # */ | |
1060 | .globl __secondary_start | |
1061 | __secondary_start: | |
1062 | lis r3,__secondary_hold_acknowledge@h | |
1063 | ori r3,r3,__secondary_hold_acknowledge@l | |
1064 | stw r24,0(r3) | |
1065 | ||
1066 | li r3,0 | |
1067 | mr r4,r24 /* Why? */ | |
1068 | bl call_setup_cpu | |
1069 | ||
1070 | lis r3,tlbcam_index@ha | |
1071 | lwz r3,tlbcam_index@l(r3) | |
1072 | mtctr r3 | |
1073 | li r26,0 /* r26 safe? */ | |
1074 | ||
1075 | /* Load each CAM entry */ | |
1076 | 1: mr r3,r26 | |
1077 | bl loadcam_entry | |
1078 | addi r26,r26,1 | |
1079 | bdnz 1b | |
1080 | ||
1081 | /* get current_thread_info and current */ | |
1082 | lis r1,secondary_ti@ha | |
1083 | lwz r1,secondary_ti@l(r1) | |
1084 | lwz r2,TI_TASK(r1) | |
1085 | ||
1086 | /* stack */ | |
1087 | addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD | |
1088 | li r0,0 | |
1089 | stw r0,0(r1) | |
1090 | ||
1091 | /* ptr to current thread */ | |
1092 | addi r4,r2,THREAD /* address of our thread_struct */ | |
ee43eb78 | 1093 | mtspr SPRN_SPRG_THREAD,r4 |
d5b26db2 KG |
1094 | |
1095 | /* Setup the defaults for TLB entries */ | |
d66c82ea | 1096 | li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l |
d5b26db2 KG |
1097 | mtspr SPRN_MAS4,r4 |
1098 | ||
1099 | /* Jump to start_secondary */ | |
1100 | lis r4,MSR_KERNEL@h | |
1101 | ori r4,r4,MSR_KERNEL@l | |
1102 | lis r3,start_secondary@h | |
1103 | ori r3,r3,start_secondary@l | |
1104 | mtspr SPRN_SRR0,r3 | |
1105 | mtspr SPRN_SRR1,r4 | |
1106 | sync | |
1107 | rfi | |
1108 | sync | |
1109 | ||
1110 | .globl __secondary_hold_acknowledge | |
1111 | __secondary_hold_acknowledge: | |
1112 | .long -1 | |
1113 | #endif | |
1114 | ||
14cf11af PM |
1115 | /* |
1116 | * We put a few things here that have to be page-aligned. This stuff | |
1117 | * goes at the beginning of the data segment, which is page-aligned. | |
1118 | */ | |
1119 | .data | |
ea703ce2 KG |
1120 | .align 12 |
1121 | .globl sdata | |
1122 | sdata: | |
1123 | .globl empty_zero_page | |
1124 | empty_zero_page: | |
14cf11af | 1125 | .space 4096 |
ea703ce2 KG |
1126 | .globl swapper_pg_dir |
1127 | swapper_pg_dir: | |
bee86f14 | 1128 | .space PGD_TABLE_SIZE |
14cf11af | 1129 | |
14cf11af PM |
1130 | /* |
1131 | * Room for two PTE pointers, usually the kernel and current user pointers | |
1132 | * to their respective root page table. | |
1133 | */ | |
1134 | abatron_pteptrs: | |
1135 | .space 8 |