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[deliverable/linux.git] / arch / powerpc / kernel / head_fsl_booke.S
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14cf11af 1/*
14cf11af
PM		 2 * Kernel execution entry point code.
3 *
4 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
5 * Initial PowerPC version.
6 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Rewritten for PReP
8 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
9 * Low-level exception handers, MMU support, and rewrite.
10 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
11 * PowerPC 8xx modifications.
12 * Copyright (c) 1998-1999 TiVo, Inc.
13 * PowerPC 403GCX modifications.
14 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
15 * PowerPC 403GCX/405GP modifications.
16 * Copyright 2000 MontaVista Software Inc.
17 * PPC405 modifications
18 * PowerPC 403GCX/405GP modifications.
19 * Author: MontaVista Software, Inc.
20 * frank_rowand@mvista.com or source@mvista.com
21 * debbie_chu@mvista.com
22 * Copyright 2002-2004 MontaVista Software, Inc.
23 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
24 * Copyright 2004 Freescale Semiconductor, Inc
4c8d3d99 25 * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
14cf11af
PM		 26 *
27 * This program is free software; you can redistribute it and/or modify it
28 * under the terms of the GNU General Public License as published by the
29 * Free Software Foundation; either version 2 of the License, or (at your
30 * option) any later version.
31 */
32
14cf11af
PM		 33#include <linux/threads.h>
34#include <asm/processor.h>
35#include <asm/page.h>
36#include <asm/mmu.h>
37#include <asm/pgtable.h>
38#include <asm/cputable.h>
39#include <asm/thread_info.h>
40#include <asm/ppc_asm.h>
41#include <asm/asm-offsets.h>
42#include "head_booke.h"
43
44/* As with the other PowerPC ports, it is expected that when code
45 * execution begins here, the following registers contain valid, yet
46 * optional, information:
47 *
48 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
49 * r4 - Starting address of the init RAM disk
50 * r5 - Ending address of the init RAM disk
51 * r6 - Start of kernel command line string (e.g. "mem=128")
52 * r7 - End of kernel command line string
53 *
54 */
55 .text
56_GLOBAL(_stext)
57_GLOBAL(_start)
58 /*
59 * Reserve a word at a fixed location to store the address
60 * of abatron_pteptrs
61 */
62 nop
63/*
64 * Save parameters we are passed
65 */
66 mr r31,r3
67 mr r30,r4
68 mr r29,r5
69 mr r28,r6
70 mr r27,r7
71 li r24,0 /* CPU number */
72
73/* We try to not make any assumptions about how the boot loader
74 * setup or used the TLBs. We invalidate all mappings from the
75 * boot loader and load a single entry in TLB1[0] to map the
76 * first 16M of kernel memory. Any boot info passed from the
77 * bootloader needs to live in this first 16M.
78 *
79 * Requirement on bootloader:
80 * - The page we're executing in needs to reside in TLB1 and
81 * have IPROT=1. If not an invalidate broadcast could
82 * evict the entry we're currently executing in.
83 *
84 * r3 = Index of TLB1 were executing in
85 * r4 = Current MSR[IS]
86 * r5 = Index of TLB1 temp mapping
87 *
88 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
89 * if needed
90 */
91
92/* 1. Find the index of the entry we're executing in */
93 bl invstr /* Find our address */
94invstr: mflr r6 /* Make it accessible */
95 mfmsr r7
96 rlwinm r4,r7,27,31,31 /* extract MSR[IS] */
97 mfspr r7, SPRN_PID0
98 slwi r7,r7,16
99 or r7,r7,r4
100 mtspr SPRN_MAS6,r7
101 tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */
102#ifndef CONFIG_E200
103 mfspr r7,SPRN_MAS1
104 andis. r7,r7,MAS1_VALID@h
105 bne match_TLB
106 mfspr r7,SPRN_PID1
107 slwi r7,r7,16
108 or r7,r7,r4
109 mtspr SPRN_MAS6,r7
110 tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */
111 mfspr r7,SPRN_MAS1
112 andis. r7,r7,MAS1_VALID@h
113 bne match_TLB
114 mfspr r7, SPRN_PID2
115 slwi r7,r7,16
116 or r7,r7,r4
117 mtspr SPRN_MAS6,r7
118 tlbsx 0,r6 /* Fall through, we had to match */
119#endif
120match_TLB:
121 mfspr r7,SPRN_MAS0
122 rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */
123
124 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
125 oris r7,r7,MAS1_IPROT@h
126 mtspr SPRN_MAS1,r7
127 tlbwe
128
129/* 2. Invalidate all entries except the entry we're executing in */
130 mfspr r9,SPRN_TLB1CFG
131 andi. r9,r9,0xfff
132 li r6,0 /* Set Entry counter to 0 */
1331: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
134 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
135 mtspr SPRN_MAS0,r7
136 tlbre
137 mfspr r7,SPRN_MAS1
138 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
139 cmpw r3,r6
140 beq skpinv /* Dont update the current execution TLB */
141 mtspr SPRN_MAS1,r7
142 tlbwe
143 isync
144skpinv: addi r6,r6,1 /* Increment */
145 cmpw r6,r9 /* Are we done? */
146 bne 1b /* If not, repeat */
147
148 /* Invalidate TLB0 */
149 li r6,0x04
150 tlbivax 0,r6
151#ifdef CONFIG_SMP
152 tlbsync
153#endif
154 /* Invalidate TLB1 */
155 li r6,0x0c
156 tlbivax 0,r6
157#ifdef CONFIG_SMP
158 tlbsync
159#endif
160 msync
161
162/* 3. Setup a temp mapping and jump to it */
163 andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */
164 addi r5, r5, 0x1
165 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
166 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
167 mtspr SPRN_MAS0,r7
168 tlbre
169
170 /* Just modify the entry ID and EPN for the temp mapping */
171 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
172 rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
173 mtspr SPRN_MAS0,r7
174 xori r6,r4,1 /* Setup TMP mapping in the other Address space */
175 slwi r6,r6,12
176 oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h
177 ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
178 mtspr SPRN_MAS1,r6
179 mfspr r6,SPRN_MAS2
180 li r7,0 /* temp EPN = 0 */
181 rlwimi r7,r6,0,20,31
182 mtspr SPRN_MAS2,r7
183 tlbwe
184
185 xori r6,r4,1
186 slwi r6,r6,5 /* setup new context with other address space */
187 bl 1f /* Find our address */
1881: mflr r9
189 rlwimi r7,r9,0,20,31
190 addi r7,r7,24
191 mtspr SPRN_SRR0,r7
192 mtspr SPRN_SRR1,r6
193 rfi
194
195/* 4. Clear out PIDs & Search info */
196 li r6,0
197 mtspr SPRN_PID0,r6
198#ifndef CONFIG_E200
199 mtspr SPRN_PID1,r6
200 mtspr SPRN_PID2,r6
201#endif
202 mtspr SPRN_MAS6,r6
203
204/* 5. Invalidate mapping we started in */
205 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
206 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
207 mtspr SPRN_MAS0,r7
208 tlbre
209 li r6,0
210 mtspr SPRN_MAS1,r6
211 tlbwe
212 /* Invalidate TLB1 */
213 li r9,0x0c
214 tlbivax 0,r9
215#ifdef CONFIG_SMP
216 tlbsync
217#endif
218 msync
219
220/* 6. Setup KERNELBASE mapping in TLB1[0] */
221 lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
222 mtspr SPRN_MAS0,r6
223 lis r6,(MAS1_VALID|MAS1_IPROT)@h
224 ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_16M))@l
225 mtspr SPRN_MAS1,r6
226 li r7,0
227 lis r6,KERNELBASE@h
228 ori r6,r6,KERNELBASE@l
229 rlwimi r6,r7,0,20,31
230 mtspr SPRN_MAS2,r6
231 li r7,(MAS3_SX|MAS3_SW|MAS3_SR)
232 mtspr SPRN_MAS3,r7
233 tlbwe
234
235/* 7. Jump to KERNELBASE mapping */
236 lis r7,MSR_KERNEL@h
237 ori r7,r7,MSR_KERNEL@l
238 bl 1f /* Find our address */
2391: mflr r9
240 rlwimi r6,r9,0,20,31
241 addi r6,r6,24
242 mtspr SPRN_SRR0,r6
243 mtspr SPRN_SRR1,r7
244 rfi /* start execution out of TLB1[0] entry */
245
246/* 8. Clear out the temp mapping */
247 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
248 rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
249 mtspr SPRN_MAS0,r7
250 tlbre
251 mtspr SPRN_MAS1,r8
252 tlbwe
253 /* Invalidate TLB1 */
254 li r9,0x0c
255 tlbivax 0,r9
256#ifdef CONFIG_SMP
257 tlbsync
258#endif
259 msync
260
261 /* Establish the interrupt vector offsets */
262 SET_IVOR(0, CriticalInput);
263 SET_IVOR(1, MachineCheck);
264 SET_IVOR(2, DataStorage);
265 SET_IVOR(3, InstructionStorage);
266 SET_IVOR(4, ExternalInput);
267 SET_IVOR(5, Alignment);
268 SET_IVOR(6, Program);
269 SET_IVOR(7, FloatingPointUnavailable);
270 SET_IVOR(8, SystemCall);
271 SET_IVOR(9, AuxillaryProcessorUnavailable);
272 SET_IVOR(10, Decrementer);
273 SET_IVOR(11, FixedIntervalTimer);
274 SET_IVOR(12, WatchdogTimer);
275 SET_IVOR(13, DataTLBError);
276 SET_IVOR(14, InstructionTLBError);
277 SET_IVOR(15, Debug);
278 SET_IVOR(32, SPEUnavailable);
279 SET_IVOR(33, SPEFloatingPointData);
280 SET_IVOR(34, SPEFloatingPointRound);
281#ifndef CONFIG_E200
282 SET_IVOR(35, PerformanceMonitor);
283#endif
284
285 /* Establish the interrupt vector base */
286 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
287 mtspr SPRN_IVPR,r4
288
289 /* Setup the defaults for TLB entries */
290 li r2,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l
291#ifdef CONFIG_E200
292 oris r2,r2,MAS4_TLBSELD(1)@h
293#endif
294 mtspr SPRN_MAS4, r2
295
296#if 0
297 /* Enable DOZE */
298 mfspr r2,SPRN_HID0
299 oris r2,r2,HID0_DOZE@h
300 mtspr SPRN_HID0, r2
301#endif
302#ifdef CONFIG_E200
303 /* enable dedicated debug exception handling resources (Debug APU) */
304 mfspr r2,SPRN_HID0
305 ori r2,r2,HID0_DAPUEN@l
306 mtspr SPRN_HID0,r2
307#endif
308
309#if !defined(CONFIG_BDI_SWITCH)
310 /*
311 * The Abatron BDI JTAG debugger does not tolerate others
312 * mucking with the debug registers.
313 */
314 lis r2,DBCR0_IDM@h
315 mtspr SPRN_DBCR0,r2
a7cb0337 316 isync
14cf11af
PM		 317 /* clear any residual debug events */
318 li r2,-1
319 mtspr SPRN_DBSR,r2
320#endif
321
322 /*
323 * This is where the main kernel code starts.
324 */
325
326 /* ptr to current */
327 lis r2,init_task@h
328 ori r2,r2,init_task@l
329
330 /* ptr to current thread */
331 addi r4,r2,THREAD /* init task's THREAD */
332 mtspr SPRN_SPRG3,r4
333
334 /* stack */
335 lis r1,init_thread_union@h
336 ori r1,r1,init_thread_union@l
337 li r0,0
338 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
339
340 bl early_init
341
342 mfspr r3,SPRN_TLB1CFG
343 andi. r3,r3,0xfff
344 lis r4,num_tlbcam_entries@ha
345 stw r3,num_tlbcam_entries@l(r4)
346/*
347 * Decide what sort of machine this is and initialize the MMU.
348 */
349 mr r3,r31
350 mr r4,r30
351 mr r5,r29
352 mr r6,r28
353 mr r7,r27
354 bl machine_init
355 bl MMU_init
356
357 /* Setup PTE pointers for the Abatron bdiGDB */
358 lis r6, swapper_pg_dir@h
359 ori r6, r6, swapper_pg_dir@l
360 lis r5, abatron_pteptrs@h
361 ori r5, r5, abatron_pteptrs@l
362 lis r4, KERNELBASE@h
363 ori r4, r4, KERNELBASE@l
364 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
365 stw r6, 0(r5)
366
367 /* Let's move on */
368 lis r4,start_kernel@h
369 ori r4,r4,start_kernel@l
370 lis r3,MSR_KERNEL@h
371 ori r3,r3,MSR_KERNEL@l
372 mtspr SPRN_SRR0,r4
373 mtspr SPRN_SRR1,r3
374 rfi /* change context and jump to start_kernel */
375
376/* Macros to hide the PTE size differences
377 *
378 * FIND_PTE -- walks the page tables given EA & pgdir pointer
379 * r10 -- EA of fault
380 * r11 -- PGDIR pointer
381 * r12 -- free
382 * label 2: is the bailout case
383 *
384 * if we find the pte (fall through):
385 * r11 is low pte word
386 * r12 is pointer to the pte
387 */
388#ifdef CONFIG_PTE_64BIT
389#define PTE_FLAGS_OFFSET 4
390#define FIND_PTE \
391 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
392 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
393 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
394 beq 2f; /* Bail if no table */ \
395 rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
396 lwz r11, 4(r12); /* Get pte entry */
397#else
398#define PTE_FLAGS_OFFSET 0
399#define FIND_PTE \
400 rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
401 lwz r11, 0(r11); /* Get L1 entry */ \
402 rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \
403 beq 2f; /* Bail if no table */ \
404 rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \
405 lwz r11, 0(r12); /* Get Linux PTE */
406#endif
407
408/*
409 * Interrupt vector entry code
410 *
411 * The Book E MMUs are always on so we don't need to handle
412 * interrupts in real mode as with previous PPC processors. In
413 * this case we handle interrupts in the kernel virtual address
414 * space.
415 *
416 * Interrupt vectors are dynamically placed relative to the
417 * interrupt prefix as determined by the address of interrupt_base.
418 * The interrupt vectors offsets are programmed using the labels
419 * for each interrupt vector entry.
420 *
421 * Interrupt vectors must be aligned on a 16 byte boundary.
422 * We align on a 32 byte cache line boundary for good measure.
423 */
424
425interrupt_base:
426 /* Critical Input Interrupt */
dc1c1ca3 427 CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception)
14cf11af
PM		 428
429 /* Machine Check Interrupt */
430#ifdef CONFIG_E200
431 /* no RFMCI, MCSRRs on E200 */
dc1c1ca3 432 CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
14cf11af 433#else
dc1c1ca3 434 MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
14cf11af
PM		 435#endif
436
437 /* Data Storage Interrupt */
438 START_EXCEPTION(DataStorage)
439 mtspr SPRN_SPRG0, r10 /* Save some working registers */
440 mtspr SPRN_SPRG1, r11
441 mtspr SPRN_SPRG4W, r12
442 mtspr SPRN_SPRG5W, r13
443 mfcr r11
444 mtspr SPRN_SPRG7W, r11
445
446 /*
447 * Check if it was a store fault, if not then bail
448 * because a user tried to access a kernel or
449 * read-protected page. Otherwise, get the
450 * offending address and handle it.
451 */
452 mfspr r10, SPRN_ESR
453 andis. r10, r10, ESR_ST@h
454 beq 2f
455
456 mfspr r10, SPRN_DEAR /* Get faulting address */
457
458 /* If we are faulting a kernel address, we have to use the
459 * kernel page tables.
460 */
461 lis r11, TASK_SIZE@h
462 ori r11, r11, TASK_SIZE@l
463 cmplw 0, r10, r11
464 bge 2f
465
466 /* Get the PGD for the current thread */
4673:
468 mfspr r11,SPRN_SPRG3
469 lwz r11,PGDIR(r11)
4704:
471 FIND_PTE
472
473 /* Are _PAGE_USER & _PAGE_RW set & _PAGE_HWWRITE not? */
474 andi. r13, r11, _PAGE_RW|_PAGE_USER|_PAGE_HWWRITE
475 cmpwi 0, r13, _PAGE_RW|_PAGE_USER
476 bne 2f /* Bail if not */
477
478 /* Update 'changed'. */
479 ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
480 stw r11, PTE_FLAGS_OFFSET(r12) /* Update Linux page table */
481
482 /* MAS2 not updated as the entry does exist in the tlb, this
483 fault taken to detect state transition (eg: COW -> DIRTY)
484 */
485 andi. r11, r11, _PAGE_HWEXEC
486 rlwimi r11, r11, 31, 27, 27 /* SX <- _PAGE_HWEXEC */
487 ori r11, r11, (MAS3_UW|MAS3_SW|MAS3_UR|MAS3_SR)@l /* set static perms */
488
489 /* update search PID in MAS6, AS = 0 */
490 mfspr r12, SPRN_PID0
491 slwi r12, r12, 16
492 mtspr SPRN_MAS6, r12
493
494 /* find the TLB index that caused the fault. It has to be here. */
495 tlbsx 0, r10
496
497 /* only update the perm bits, assume the RPN is fine */
498 mfspr r12, SPRN_MAS3
499 rlwimi r12, r11, 0, 20, 31
500 mtspr SPRN_MAS3,r12
501 tlbwe
502
503 /* Done...restore registers and get out of here. */
504 mfspr r11, SPRN_SPRG7R
505 mtcr r11
506 mfspr r13, SPRN_SPRG5R
507 mfspr r12, SPRN_SPRG4R
508 mfspr r11, SPRN_SPRG1
509 mfspr r10, SPRN_SPRG0
510 rfi /* Force context change */
511
5122:
513 /*
514 * The bailout. Restore registers to pre-exception conditions
515 * and call the heavyweights to help us out.
516 */
517 mfspr r11, SPRN_SPRG7R
518 mtcr r11
519 mfspr r13, SPRN_SPRG5R
520 mfspr r12, SPRN_SPRG4R
521 mfspr r11, SPRN_SPRG1
522 mfspr r10, SPRN_SPRG0
523 b data_access
524
525 /* Instruction Storage Interrupt */
526 INSTRUCTION_STORAGE_EXCEPTION
527
528 /* External Input Interrupt */
529 EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
530
531 /* Alignment Interrupt */
532 ALIGNMENT_EXCEPTION
533
534 /* Program Interrupt */
535 PROGRAM_EXCEPTION
536
537 /* Floating Point Unavailable Interrupt */
538#ifdef CONFIG_PPC_FPU
539 FP_UNAVAILABLE_EXCEPTION
540#else
541#ifdef CONFIG_E200
542 /* E200 treats 'normal' floating point instructions as FP Unavail exception */
dc1c1ca3 543 EXCEPTION(0x0800, FloatingPointUnavailable, program_check_exception, EXC_XFER_EE)
14cf11af 544#else
dc1c1ca3 545 EXCEPTION(0x0800, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE)
14cf11af
PM		 546#endif
547#endif
548
549 /* System Call Interrupt */
550 START_EXCEPTION(SystemCall)
551 NORMAL_EXCEPTION_PROLOG
552 EXC_XFER_EE_LITE(0x0c00, DoSyscall)
553
554 /* Auxillary Processor Unavailable Interrupt */
dc1c1ca3 555 EXCEPTION(0x2900, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE)
14cf11af
PM		 556
557 /* Decrementer Interrupt */
558 DECREMENTER_EXCEPTION
559
560 /* Fixed Internal Timer Interrupt */
561 /* TODO: Add FIT support */
dc1c1ca3 562 EXCEPTION(0x3100, FixedIntervalTimer, unknown_exception, EXC_XFER_EE)
14cf11af
PM		 563
564 /* Watchdog Timer Interrupt */
565#ifdef CONFIG_BOOKE_WDT
566 CRITICAL_EXCEPTION(0x3200, WatchdogTimer, WatchdogException)
567#else
dc1c1ca3 568 CRITICAL_EXCEPTION(0x3200, WatchdogTimer, unknown_exception)
14cf11af
PM		 569#endif
570
571 /* Data TLB Error Interrupt */
572 START_EXCEPTION(DataTLBError)
573 mtspr SPRN_SPRG0, r10 /* Save some working registers */
574 mtspr SPRN_SPRG1, r11
575 mtspr SPRN_SPRG4W, r12
576 mtspr SPRN_SPRG5W, r13
577 mfcr r11
578 mtspr SPRN_SPRG7W, r11
579 mfspr r10, SPRN_DEAR /* Get faulting address */
580
581 /* If we are faulting a kernel address, we have to use the
582 * kernel page tables.
583 */
584 lis r11, TASK_SIZE@h
585 ori r11, r11, TASK_SIZE@l
586 cmplw 5, r10, r11
587 blt 5, 3f
588 lis r11, swapper_pg_dir@h
589 ori r11, r11, swapper_pg_dir@l
590
591 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
592 rlwinm r12,r12,0,16,1
593 mtspr SPRN_MAS1,r12
594
595 b 4f
596
597 /* Get the PGD for the current thread */
5983:
599 mfspr r11,SPRN_SPRG3
600 lwz r11,PGDIR(r11)
601
6024:
603 FIND_PTE
604 andi. r13, r11, _PAGE_PRESENT /* Is the page present? */
605 beq 2f /* Bail if not present */
606
607#ifdef CONFIG_PTE_64BIT
608 lwz r13, 0(r12)
609#endif
610 ori r11, r11, _PAGE_ACCESSED
611 stw r11, PTE_FLAGS_OFFSET(r12)
612
613 /* Jump to common tlb load */
614 b finish_tlb_load
6152:
616 /* The bailout. Restore registers to pre-exception conditions
617 * and call the heavyweights to help us out.
618 */
619 mfspr r11, SPRN_SPRG7R
620 mtcr r11
621 mfspr r13, SPRN_SPRG5R
622 mfspr r12, SPRN_SPRG4R
623 mfspr r11, SPRN_SPRG1
624 mfspr r10, SPRN_SPRG0
625 b data_access
626
627 /* Instruction TLB Error Interrupt */
628 /*
629 * Nearly the same as above, except we get our
630 * information from different registers and bailout
631 * to a different point.
632 */
633 START_EXCEPTION(InstructionTLBError)
634 mtspr SPRN_SPRG0, r10 /* Save some working registers */
635 mtspr SPRN_SPRG1, r11
636 mtspr SPRN_SPRG4W, r12
637 mtspr SPRN_SPRG5W, r13
638 mfcr r11
639 mtspr SPRN_SPRG7W, r11
640 mfspr r10, SPRN_SRR0 /* Get faulting address */
641
642 /* If we are faulting a kernel address, we have to use the
643 * kernel page tables.
644 */
645 lis r11, TASK_SIZE@h
646 ori r11, r11, TASK_SIZE@l
647 cmplw 5, r10, r11
648 blt 5, 3f
649 lis r11, swapper_pg_dir@h
650 ori r11, r11, swapper_pg_dir@l
651
652 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
653 rlwinm r12,r12,0,16,1
654 mtspr SPRN_MAS1,r12
655
656 b 4f
657
658 /* Get the PGD for the current thread */
6593:
660 mfspr r11,SPRN_SPRG3
661 lwz r11,PGDIR(r11)
662
6634:
664 FIND_PTE
665 andi. r13, r11, _PAGE_PRESENT /* Is the page present? */
666 beq 2f /* Bail if not present */
667
668#ifdef CONFIG_PTE_64BIT
669 lwz r13, 0(r12)
670#endif
671 ori r11, r11, _PAGE_ACCESSED
672 stw r11, PTE_FLAGS_OFFSET(r12)
673
674 /* Jump to common TLB load point */
675 b finish_tlb_load
676
6772:
678 /* The bailout. Restore registers to pre-exception conditions
679 * and call the heavyweights to help us out.
680 */
681 mfspr r11, SPRN_SPRG7R
682 mtcr r11
683 mfspr r13, SPRN_SPRG5R
684 mfspr r12, SPRN_SPRG4R
685 mfspr r11, SPRN_SPRG1
686 mfspr r10, SPRN_SPRG0
687 b InstructionStorage
688
689#ifdef CONFIG_SPE
690 /* SPE Unavailable */
691 START_EXCEPTION(SPEUnavailable)
692 NORMAL_EXCEPTION_PROLOG
693 bne load_up_spe
694 addi r3,r1,STACK_FRAME_OVERHEAD
695 EXC_XFER_EE_LITE(0x2010, KernelSPE)
696#else
dc1c1ca3 697 EXCEPTION(0x2020, SPEUnavailable, unknown_exception, EXC_XFER_EE)
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PM		 698#endif /* CONFIG_SPE */
699
700 /* SPE Floating Point Data */
701#ifdef CONFIG_SPE
702 EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE);
703#else
dc1c1ca3 704 EXCEPTION(0x2040, SPEFloatingPointData, unknown_exception, EXC_XFER_EE)
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PM		 705#endif /* CONFIG_SPE */
706
707 /* SPE Floating Point Round */
dc1c1ca3 708 EXCEPTION(0x2050, SPEFloatingPointRound, unknown_exception, EXC_XFER_EE)
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PM		 709
710 /* Performance Monitor */
dc1c1ca3 711 EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD)
14cf11af
PM		 712
713
714 /* Debug Interrupt */
715 DEBUG_EXCEPTION
716
717/*
718 * Local functions
719 */
720
721 /*
722 * Data TLB exceptions will bail out to this point
723 * if they can't resolve the lightweight TLB fault.
724 */
725data_access:
726 NORMAL_EXCEPTION_PROLOG
727 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
728 stw r5,_ESR(r11)
729 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
730 andis. r10,r5,(ESR_ILK|ESR_DLK)@h
731 bne 1f
732 EXC_XFER_EE_LITE(0x0300, handle_page_fault)
7331:
734 addi r3,r1,STACK_FRAME_OVERHEAD
735 EXC_XFER_EE_LITE(0x0300, CacheLockingException)
736
737/*
738
739 * Both the instruction and data TLB miss get to this
740 * point to load the TLB.
741 * r10 - EA of fault
742 * r11 - TLB (info from Linux PTE)
743 * r12, r13 - available to use
744 * CR5 - results of addr < TASK_SIZE
745 * MAS0, MAS1 - loaded with proper value when we get here
746 * MAS2, MAS3 - will need additional info from Linux PTE
747 * Upon exit, we reload everything and RFI.
748 */
749finish_tlb_load:
750 /*
751 * We set execute, because we don't have the granularity to
752 * properly set this at the page level (Linux problem).
753 * Many of these bits are software only. Bits we don't set
754 * here we (properly should) assume have the appropriate value.
755 */
756
757 mfspr r12, SPRN_MAS2
758#ifdef CONFIG_PTE_64BIT
759 rlwimi r12, r11, 26, 24, 31 /* extract ...WIMGE from pte */
760#else
761 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
762#endif
763 mtspr SPRN_MAS2, r12
764
765 bge 5, 1f
766
767 /* is user addr */
768 andi. r12, r11, (_PAGE_USER | _PAGE_HWWRITE | _PAGE_HWEXEC)
769 andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
770 srwi r10, r12, 1
771 or r12, r12, r10 /* Copy user perms into supervisor */
772 iseleq r12, 0, r12
773 b 2f
774
775 /* is kernel addr */
7761: rlwinm r12, r11, 31, 29, 29 /* Extract _PAGE_HWWRITE into SW */
777 ori r12, r12, (MAS3_SX | MAS3_SR)
778
779#ifdef CONFIG_PTE_64BIT
7802: rlwimi r12, r13, 24, 0, 7 /* grab RPN[32:39] */
781 rlwimi r12, r11, 24, 8, 19 /* grab RPN[40:51] */
782 mtspr SPRN_MAS3, r12
783BEGIN_FTR_SECTION
784 srwi r10, r13, 8 /* grab RPN[8:31] */
785 mtspr SPRN_MAS7, r10
786END_FTR_SECTION_IFSET(CPU_FTR_BIG_PHYS)
787#else
7882: rlwimi r11, r12, 0, 20, 31 /* Extract RPN from PTE and merge with perms */
789 mtspr SPRN_MAS3, r11
790#endif
791#ifdef CONFIG_E200
792 /* Round robin TLB1 entries assignment */
793 mfspr r12, SPRN_MAS0
794
795 /* Extract TLB1CFG(NENTRY) */
796 mfspr r11, SPRN_TLB1CFG
797 andi. r11, r11, 0xfff
798
799 /* Extract MAS0(NV) */
800 andi. r13, r12, 0xfff
801 addi r13, r13, 1
802 cmpw 0, r13, r11
803 addi r12, r12, 1
804
805 /* check if we need to wrap */
806 blt 7f
807
808 /* wrap back to first free tlbcam entry */
809 lis r13, tlbcam_index@ha
810 lwz r13, tlbcam_index@l(r13)
811 rlwimi r12, r13, 0, 20, 31
8127:
813 mtspr SPRN_MAS0,r12
814#endif /* CONFIG_E200 */
815
816 tlbwe
817
818 /* Done...restore registers and get out of here. */
819 mfspr r11, SPRN_SPRG7R
820 mtcr r11
821 mfspr r13, SPRN_SPRG5R
822 mfspr r12, SPRN_SPRG4R
823 mfspr r11, SPRN_SPRG1
824 mfspr r10, SPRN_SPRG0
825 rfi /* Force context change */
826
827#ifdef CONFIG_SPE
828/* Note that the SPE support is closely modeled after the AltiVec
829 * support. Changes to one are likely to be applicable to the
830 * other! */
831load_up_spe:
832/*
833 * Disable SPE for the task which had SPE previously,
834 * and save its SPE registers in its thread_struct.
835 * Enables SPE for use in the kernel on return.
836 * On SMP we know the SPE units are free, since we give it up every
837 * switch. -- Kumar
838 */
839 mfmsr r5
840 oris r5,r5,MSR_SPE@h
841 mtmsr r5 /* enable use of SPE now */
842 isync
843/*
844 * For SMP, we don't do lazy SPE switching because it just gets too
845 * horrendously complex, especially when a task switches from one CPU
846 * to another. Instead we call giveup_spe in switch_to.
847 */
848#ifndef CONFIG_SMP
849 lis r3,last_task_used_spe@ha
850 lwz r4,last_task_used_spe@l(r3)
851 cmpi 0,r4,0
852 beq 1f
853 addi r4,r4,THREAD /* want THREAD of last_task_used_spe */
854 SAVE_32EVRS(0,r10,r4)
855 evxor evr10, evr10, evr10 /* clear out evr10 */
856 evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */
857 li r5,THREAD_ACC
858 evstddx evr10, r4, r5 /* save off accumulator */
859 lwz r5,PT_REGS(r4)
860 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
861 lis r10,MSR_SPE@h
862 andc r4,r4,r10 /* disable SPE for previous task */
863 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
8641:
865#endif /* CONFIG_SMP */
866 /* enable use of SPE after return */
867 oris r9,r9,MSR_SPE@h
868 mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
869 li r4,1
870 li r10,THREAD_ACC
871 stw r4,THREAD_USED_SPE(r5)
872 evlddx evr4,r10,r5
873 evmra evr4,evr4
874 REST_32EVRS(0,r10,r5)
875#ifndef CONFIG_SMP
876 subi r4,r5,THREAD
877 stw r4,last_task_used_spe@l(r3)
878#endif /* CONFIG_SMP */
879 /* restore registers and return */
8802: REST_4GPRS(3, r11)
881 lwz r10,_CCR(r11)
882 REST_GPR(1, r11)
883 mtcr r10
884 lwz r10,_LINK(r11)
885 mtlr r10
886 REST_GPR(10, r11)
887 mtspr SPRN_SRR1,r9
888 mtspr SPRN_SRR0,r12
889 REST_GPR(9, r11)
890 REST_GPR(12, r11)
891 lwz r11,GPR11(r11)
892 SYNC
893 rfi
894
895/*
896 * SPE unavailable trap from kernel - print a message, but let
897 * the task use SPE in the kernel until it returns to user mode.
898 */
899KernelSPE:
900 lwz r3,_MSR(r1)
901 oris r3,r3,MSR_SPE@h
902 stw r3,_MSR(r1) /* enable use of SPE after return */
903 lis r3,87f@h
904 ori r3,r3,87f@l
905 mr r4,r2 /* current */
906 lwz r5,_NIP(r1)
907 bl printk
908 b ret_from_except
90987: .string "SPE used in kernel (task=%p, pc=%x) \n"
910 .align 4,0
911
912#endif /* CONFIG_SPE */
913
914/*
915 * Global functions
916 */
917
918/*
919 * extern void loadcam_entry(unsigned int index)
920 *
921 * Load TLBCAM[index] entry in to the L2 CAM MMU
922 */
923_GLOBAL(loadcam_entry)
924 lis r4,TLBCAM@ha
925 addi r4,r4,TLBCAM@l
926 mulli r5,r3,20
927 add r3,r5,r4
928 lwz r4,0(r3)
929 mtspr SPRN_MAS0,r4
930 lwz r4,4(r3)
931 mtspr SPRN_MAS1,r4
932 lwz r4,8(r3)
933 mtspr SPRN_MAS2,r4
934 lwz r4,12(r3)
935 mtspr SPRN_MAS3,r4
936 tlbwe
937 isync
938 blr
939
940/*
941 * extern void giveup_altivec(struct task_struct *prev)
942 *
943 * The e500 core does not have an AltiVec unit.
944 */
945_GLOBAL(giveup_altivec)
946 blr
947
948#ifdef CONFIG_SPE
949/*
950 * extern void giveup_spe(struct task_struct *prev)
951 *
952 */
953_GLOBAL(giveup_spe)
954 mfmsr r5
955 oris r5,r5,MSR_SPE@h
956 SYNC
957 mtmsr r5 /* enable use of SPE now */
958 isync
959 cmpi 0,r3,0
960 beqlr- /* if no previous owner, done */
961 addi r3,r3,THREAD /* want THREAD of task */
962 lwz r5,PT_REGS(r3)
963 cmpi 0,r5,0
964 SAVE_32EVRS(0, r4, r3)
965 evxor evr6, evr6, evr6 /* clear out evr6 */
966 evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
967 li r4,THREAD_ACC
968 evstddx evr6, r4, r3 /* save off accumulator */
969 mfspr r6,SPRN_SPEFSCR
970 stw r6,THREAD_SPEFSCR(r3) /* save spefscr register value */
971 beq 1f
972 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
973 lis r3,MSR_SPE@h
974 andc r4,r4,r3 /* disable SPE for previous task */
975 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
9761:
977#ifndef CONFIG_SMP
978 li r5,0
979 lis r4,last_task_used_spe@ha
980 stw r5,last_task_used_spe@l(r4)
981#endif /* CONFIG_SMP */
982 blr
983#endif /* CONFIG_SPE */
984
985/*
986 * extern void giveup_fpu(struct task_struct *prev)
987 *
988 * Not all FSL Book-E cores have an FPU
989 */
990#ifndef CONFIG_PPC_FPU
991_GLOBAL(giveup_fpu)
992 blr
993#endif
994
995/*
996 * extern void abort(void)
997 *
998 * At present, this routine just applies a system reset.
999 */
1000_GLOBAL(abort)
1001 li r13,0
1002 mtspr SPRN_DBCR0,r13 /* disable all debug events */
a7cb0337 1003 isync
14cf11af
PM		 1004 mfmsr r13
1005 ori r13,r13,MSR_DE@l /* Enable Debug Events */
1006 mtmsr r13
a7cb0337 1007 isync
14cf11af
PM		 1008 mfspr r13,SPRN_DBCR0
1009 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
1010 mtspr SPRN_DBCR0,r13
a7cb0337 1011 isync
14cf11af
PM		 1012
1013_GLOBAL(set_context)
1014
1015#ifdef CONFIG_BDI_SWITCH
1016 /* Context switch the PTE pointer for the Abatron BDI2000.
1017 * The PGDIR is the second parameter.
1018 */
1019 lis r5, abatron_pteptrs@h
1020 ori r5, r5, abatron_pteptrs@l
1021 stw r4, 0x4(r5)
1022#endif
1023 mtspr SPRN_PID,r3
1024 isync /* Force context change */
1025 blr
1026
1027/*
1028 * We put a few things here that have to be page-aligned. This stuff
1029 * goes at the beginning of the data segment, which is page-aligned.
1030 */
1031 .data
ea703ce2
KG		 1032 .align 12
1033 .globl sdata
1034sdata:
1035 .globl empty_zero_page
1036empty_zero_page:
14cf11af 1037 .space 4096
ea703ce2
KG		 1038 .globl swapper_pg_dir
1039swapper_pg_dir:
14cf11af
PM		 1040 .space 4096
1041
1042/* Reserved 4k for the critical exception stack & 4k for the machine
1043 * check stack per CPU for kernel mode exceptions */
1044 .section .bss
1045 .align 12
1046exception_stack_bottom:
1047 .space BOOKE_EXCEPTION_STACK_SIZE * NR_CPUS
ea703ce2
KG		 1048 .globl exception_stack_top
1049exception_stack_top:
14cf11af
PM		 1050
1051/*
1052 * This space gets a copy of optional info passed to us by the bootstrap
1053 * which is used to pass parameters into the kernel like root=/dev/sda1, etc.
1054 */
ea703ce2
KG		 1055 .globl cmd_line
1056cmd_line:
14cf11af
PM		 1057 .space 512
1058
1059/*
1060 * Room for two PTE pointers, usually the kernel and current user pointers
1061 * to their respective root page table.
1062 */
1063abatron_pteptrs:
1064 .space 8
Linux kernel - Deliverables
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