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9994a338 PM |
1 | /* |
2 | * This file contains miscellaneous low-level functions. | |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * | |
5 | * Largely rewritten by Cort Dougan (cort@cs.nmt.edu) | |
6 | * and Paul Mackerras. | |
7 | * | |
3d1229d6 ME |
8 | * kexec bits: |
9 | * Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com> | |
10 | * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz | |
11 | * | |
9994a338 PM |
12 | * This program is free software; you can redistribute it and/or |
13 | * modify it under the terms of the GNU General Public License | |
14 | * as published by the Free Software Foundation; either version | |
15 | * 2 of the License, or (at your option) any later version. | |
16 | * | |
17 | */ | |
18 | ||
9994a338 PM |
19 | #include <linux/sys.h> |
20 | #include <asm/unistd.h> | |
21 | #include <asm/errno.h> | |
22 | #include <asm/reg.h> | |
23 | #include <asm/page.h> | |
24 | #include <asm/cache.h> | |
25 | #include <asm/cputable.h> | |
26 | #include <asm/mmu.h> | |
27 | #include <asm/ppc_asm.h> | |
28 | #include <asm/thread_info.h> | |
29 | #include <asm/asm-offsets.h> | |
3d1229d6 ME |
30 | #include <asm/processor.h> |
31 | #include <asm/kexec.h> | |
9994a338 PM |
32 | |
33 | .text | |
34 | ||
85218827 KG |
35 | #ifdef CONFIG_IRQSTACKS |
36 | _GLOBAL(call_do_softirq) | |
37 | mflr r0 | |
38 | stw r0,4(r1) | |
39 | stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3) | |
40 | mr r1,r3 | |
41 | bl __do_softirq | |
42 | lwz r1,0(r1) | |
43 | lwz r0,4(r1) | |
44 | mtlr r0 | |
45 | blr | |
46 | ||
47 | _GLOBAL(call_handle_irq) | |
48 | mflr r0 | |
49 | stw r0,4(r1) | |
50 | mtctr r6 | |
51 | stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r5) | |
52 | mr r1,r5 | |
53 | bctrl | |
54 | lwz r1,0(r1) | |
55 | lwz r0,4(r1) | |
56 | mtlr r0 | |
57 | blr | |
58 | #endif /* CONFIG_IRQSTACKS */ | |
59 | ||
f2783c15 PM |
60 | /* |
61 | * This returns the high 64 bits of the product of two 64-bit numbers. | |
62 | */ | |
63 | _GLOBAL(mulhdu) | |
64 | cmpwi r6,0 | |
65 | cmpwi cr1,r3,0 | |
66 | mr r10,r4 | |
67 | mulhwu r4,r4,r5 | |
68 | beq 1f | |
69 | mulhwu r0,r10,r6 | |
70 | mullw r7,r10,r5 | |
71 | addc r7,r0,r7 | |
72 | addze r4,r4 | |
73 | 1: beqlr cr1 /* all done if high part of A is 0 */ | |
74 | mr r10,r3 | |
75 | mullw r9,r3,r5 | |
76 | mulhwu r3,r3,r5 | |
77 | beq 2f | |
78 | mullw r0,r10,r6 | |
79 | mulhwu r8,r10,r6 | |
80 | addc r7,r0,r7 | |
81 | adde r4,r4,r8 | |
82 | addze r3,r3 | |
83 | 2: addc r4,r4,r9 | |
84 | addze r3,r3 | |
85 | blr | |
86 | ||
9994a338 PM |
87 | /* |
88 | * sub_reloc_offset(x) returns x - reloc_offset(). | |
89 | */ | |
90 | _GLOBAL(sub_reloc_offset) | |
91 | mflr r0 | |
92 | bl 1f | |
93 | 1: mflr r5 | |
94 | lis r4,1b@ha | |
95 | addi r4,r4,1b@l | |
96 | subf r5,r4,r5 | |
97 | subf r3,r5,r3 | |
98 | mtlr r0 | |
99 | blr | |
100 | ||
101 | /* | |
102 | * reloc_got2 runs through the .got2 section adding an offset | |
103 | * to each entry. | |
104 | */ | |
105 | _GLOBAL(reloc_got2) | |
106 | mflr r11 | |
107 | lis r7,__got2_start@ha | |
108 | addi r7,r7,__got2_start@l | |
109 | lis r8,__got2_end@ha | |
110 | addi r8,r8,__got2_end@l | |
111 | subf r8,r7,r8 | |
112 | srwi. r8,r8,2 | |
113 | beqlr | |
114 | mtctr r8 | |
115 | bl 1f | |
116 | 1: mflr r0 | |
117 | lis r4,1b@ha | |
118 | addi r4,r4,1b@l | |
119 | subf r0,r4,r0 | |
120 | add r7,r0,r7 | |
121 | 2: lwz r0,0(r7) | |
122 | add r0,r0,r3 | |
123 | stw r0,0(r7) | |
124 | addi r7,r7,4 | |
125 | bdnz 2b | |
126 | mtlr r11 | |
127 | blr | |
128 | ||
9994a338 PM |
129 | /* |
130 | * call_setup_cpu - call the setup_cpu function for this cpu | |
131 | * r3 = data offset, r24 = cpu number | |
132 | * | |
133 | * Setup function is called with: | |
134 | * r3 = data offset | |
135 | * r4 = ptr to CPU spec (relocated) | |
136 | */ | |
137 | _GLOBAL(call_setup_cpu) | |
138 | addis r4,r3,cur_cpu_spec@ha | |
139 | addi r4,r4,cur_cpu_spec@l | |
140 | lwz r4,0(r4) | |
141 | add r4,r4,r3 | |
142 | lwz r5,CPU_SPEC_SETUP(r4) | |
b26f100d | 143 | cmpwi 0,r5,0 |
9994a338 PM |
144 | add r5,r5,r3 |
145 | beqlr | |
146 | mtctr r5 | |
147 | bctr | |
148 | ||
149 | #if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx) | |
150 | ||
151 | /* This gets called by via-pmu.c to switch the PLL selection | |
152 | * on 750fx CPU. This function should really be moved to some | |
153 | * other place (as most of the cpufreq code in via-pmu | |
154 | */ | |
155 | _GLOBAL(low_choose_750fx_pll) | |
156 | /* Clear MSR:EE */ | |
157 | mfmsr r7 | |
158 | rlwinm r0,r7,0,17,15 | |
159 | mtmsr r0 | |
160 | ||
161 | /* If switching to PLL1, disable HID0:BTIC */ | |
162 | cmplwi cr0,r3,0 | |
163 | beq 1f | |
164 | mfspr r5,SPRN_HID0 | |
165 | rlwinm r5,r5,0,27,25 | |
166 | sync | |
167 | mtspr SPRN_HID0,r5 | |
168 | isync | |
169 | sync | |
170 | ||
171 | 1: | |
172 | /* Calc new HID1 value */ | |
173 | mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */ | |
174 | rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */ | |
175 | rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */ | |
176 | or r4,r4,r5 | |
177 | mtspr SPRN_HID1,r4 | |
178 | ||
179 | /* Store new HID1 image */ | |
f608600e | 180 | rlwinm r6,r1,0,0,(31-THREAD_SHIFT) |
9994a338 PM |
181 | lwz r6,TI_CPU(r6) |
182 | slwi r6,r6,2 | |
183 | addis r6,r6,nap_save_hid1@ha | |
184 | stw r4,nap_save_hid1@l(r6) | |
185 | ||
186 | /* If switching to PLL0, enable HID0:BTIC */ | |
187 | cmplwi cr0,r3,0 | |
188 | bne 1f | |
189 | mfspr r5,SPRN_HID0 | |
190 | ori r5,r5,HID0_BTIC | |
191 | sync | |
192 | mtspr SPRN_HID0,r5 | |
193 | isync | |
194 | sync | |
195 | ||
196 | 1: | |
197 | /* Return */ | |
198 | mtmsr r7 | |
199 | blr | |
200 | ||
201 | _GLOBAL(low_choose_7447a_dfs) | |
202 | /* Clear MSR:EE */ | |
203 | mfmsr r7 | |
204 | rlwinm r0,r7,0,17,15 | |
205 | mtmsr r0 | |
206 | ||
207 | /* Calc new HID1 value */ | |
208 | mfspr r4,SPRN_HID1 | |
209 | insrwi r4,r3,1,9 /* insert parameter into bit 9 */ | |
210 | sync | |
211 | mtspr SPRN_HID1,r4 | |
212 | sync | |
213 | isync | |
214 | ||
215 | /* Return */ | |
216 | mtmsr r7 | |
217 | blr | |
218 | ||
219 | #endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */ | |
220 | ||
221 | /* | |
222 | * complement mask on the msr then "or" some values on. | |
223 | * _nmask_and_or_msr(nmask, value_to_or) | |
224 | */ | |
225 | _GLOBAL(_nmask_and_or_msr) | |
226 | mfmsr r0 /* Get current msr */ | |
227 | andc r0,r0,r3 /* And off the bits set in r3 (first parm) */ | |
228 | or r0,r0,r4 /* Or on the bits in r4 (second parm) */ | |
229 | SYNC /* Some chip revs have problems here... */ | |
230 | mtmsr r0 /* Update machine state */ | |
231 | isync | |
232 | blr /* Done */ | |
233 | ||
9dae8afd BH |
234 | #ifdef CONFIG_40x |
235 | ||
236 | /* | |
237 | * Do an IO access in real mode | |
238 | */ | |
239 | _GLOBAL(real_readb) | |
240 | mfmsr r7 | |
241 | ori r0,r7,MSR_DR | |
242 | xori r0,r0,MSR_DR | |
243 | sync | |
244 | mtmsr r0 | |
245 | sync | |
246 | isync | |
247 | lbz r3,0(r3) | |
248 | sync | |
249 | mtmsr r7 | |
250 | sync | |
251 | isync | |
252 | blr | |
253 | ||
254 | /* | |
255 | * Do an IO access in real mode | |
256 | */ | |
257 | _GLOBAL(real_writeb) | |
258 | mfmsr r7 | |
259 | ori r0,r7,MSR_DR | |
260 | xori r0,r0,MSR_DR | |
261 | sync | |
262 | mtmsr r0 | |
263 | sync | |
264 | isync | |
265 | stb r3,0(r4) | |
266 | sync | |
267 | mtmsr r7 | |
268 | sync | |
269 | isync | |
270 | blr | |
271 | ||
272 | #endif /* CONFIG_40x */ | |
9994a338 PM |
273 | |
274 | /* | |
275 | * Flush MMU TLB | |
276 | */ | |
0ba3418b KG |
277 | #ifndef CONFIG_FSL_BOOKE |
278 | _GLOBAL(_tlbil_all) | |
279 | _GLOBAL(_tlbil_pid) | |
280 | #endif | |
9994a338 PM |
281 | _GLOBAL(_tlbia) |
282 | #if defined(CONFIG_40x) | |
283 | sync /* Flush to memory before changing mapping */ | |
284 | tlbia | |
285 | isync /* Flush shadow TLB */ | |
286 | #elif defined(CONFIG_44x) | |
287 | li r3,0 | |
288 | sync | |
289 | ||
290 | /* Load high watermark */ | |
291 | lis r4,tlb_44x_hwater@ha | |
292 | lwz r5,tlb_44x_hwater@l(r4) | |
293 | ||
294 | 1: tlbwe r3,r3,PPC44x_TLB_PAGEID | |
295 | addi r3,r3,1 | |
296 | cmpw 0,r3,r5 | |
297 | ble 1b | |
298 | ||
299 | isync | |
300 | #elif defined(CONFIG_FSL_BOOKE) | |
301 | /* Invalidate all entries in TLB0 */ | |
302 | li r3, 0x04 | |
303 | tlbivax 0,3 | |
304 | /* Invalidate all entries in TLB1 */ | |
305 | li r3, 0x0c | |
306 | tlbivax 0,3 | |
9994a338 PM |
307 | msync |
308 | #ifdef CONFIG_SMP | |
309 | tlbsync | |
310 | #endif /* CONFIG_SMP */ | |
311 | #else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */ | |
312 | #if defined(CONFIG_SMP) | |
f608600e | 313 | rlwinm r8,r1,0,0,(31-THREAD_SHIFT) |
9994a338 PM |
314 | lwz r8,TI_CPU(r8) |
315 | oris r8,r8,10 | |
316 | mfmsr r10 | |
317 | SYNC | |
318 | rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ | |
319 | rlwinm r0,r0,0,28,26 /* clear DR */ | |
320 | mtmsr r0 | |
321 | SYNC_601 | |
322 | isync | |
323 | lis r9,mmu_hash_lock@h | |
324 | ori r9,r9,mmu_hash_lock@l | |
325 | tophys(r9,r9) | |
326 | 10: lwarx r7,0,r9 | |
327 | cmpwi 0,r7,0 | |
328 | bne- 10b | |
329 | stwcx. r8,0,r9 | |
330 | bne- 10b | |
331 | sync | |
332 | tlbia | |
333 | sync | |
334 | TLBSYNC | |
335 | li r0,0 | |
336 | stw r0,0(r9) /* clear mmu_hash_lock */ | |
337 | mtmsr r10 | |
338 | SYNC_601 | |
339 | isync | |
340 | #else /* CONFIG_SMP */ | |
341 | sync | |
342 | tlbia | |
343 | sync | |
344 | #endif /* CONFIG_SMP */ | |
345 | #endif /* ! defined(CONFIG_40x) */ | |
346 | blr | |
347 | ||
348 | /* | |
349 | * Flush MMU TLB for a particular address | |
350 | */ | |
0ba3418b KG |
351 | #ifndef CONFIG_FSL_BOOKE |
352 | _GLOBAL(_tlbil_va) | |
353 | #endif | |
9994a338 PM |
354 | _GLOBAL(_tlbie) |
355 | #if defined(CONFIG_40x) | |
e701d269 BH |
356 | /* We run the search with interrupts disabled because we have to change |
357 | * the PID and I don't want to preempt when that happens. | |
358 | */ | |
359 | mfmsr r5 | |
360 | mfspr r6,SPRN_PID | |
361 | wrteei 0 | |
362 | mtspr SPRN_PID,r4 | |
9994a338 | 363 | tlbsx. r3, 0, r3 |
e701d269 BH |
364 | mtspr SPRN_PID,r6 |
365 | wrtee r5 | |
9994a338 PM |
366 | bne 10f |
367 | sync | |
368 | /* There are only 64 TLB entries, so r3 < 64, which means bit 25 is clear. | |
369 | * Since 25 is the V bit in the TLB_TAG, loading this value will invalidate | |
370 | * the TLB entry. */ | |
371 | tlbwe r3, r3, TLB_TAG | |
372 | isync | |
373 | 10: | |
e701d269 | 374 | |
9994a338 | 375 | #elif defined(CONFIG_44x) |
e701d269 BH |
376 | mfspr r5,SPRN_MMUCR |
377 | rlwimi r5,r4,0,24,31 /* Set TID */ | |
9994a338 | 378 | |
aa1cf632 DG |
379 | /* We have to run the search with interrupts disabled, even critical |
380 | * and debug interrupts (in fact the only critical exceptions we have | |
381 | * are debug and machine check). Otherwise an interrupt which causes | |
382 | * a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */ | |
e701d269 | 383 | mfmsr r4 |
aa1cf632 DG |
384 | lis r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha |
385 | addi r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l | |
e701d269 | 386 | andc r6,r4,r6 |
aa1cf632 | 387 | mtmsr r6 |
e701d269 | 388 | mtspr SPRN_MMUCR,r5 |
9994a338 | 389 | tlbsx. r3, 0, r3 |
e701d269 | 390 | mtmsr r4 |
9994a338 PM |
391 | bne 10f |
392 | sync | |
393 | /* There are only 64 TLB entries, so r3 < 64, | |
394 | * which means bit 22, is clear. Since 22 is | |
395 | * the V bit in the TLB_PAGEID, loading this | |
396 | * value will invalidate the TLB entry. | |
397 | */ | |
398 | tlbwe r3, r3, PPC44x_TLB_PAGEID | |
399 | isync | |
400 | 10: | |
401 | #elif defined(CONFIG_FSL_BOOKE) | |
402 | rlwinm r4, r3, 0, 0, 19 | |
403 | ori r5, r4, 0x08 /* TLBSEL = 1 */ | |
9994a338 PM |
404 | tlbivax 0, r4 |
405 | tlbivax 0, r5 | |
9994a338 PM |
406 | msync |
407 | #if defined(CONFIG_SMP) | |
408 | tlbsync | |
409 | #endif /* CONFIG_SMP */ | |
410 | #else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */ | |
411 | #if defined(CONFIG_SMP) | |
f608600e | 412 | rlwinm r8,r1,0,0,(31-THREAD_SHIFT) |
9994a338 PM |
413 | lwz r8,TI_CPU(r8) |
414 | oris r8,r8,11 | |
415 | mfmsr r10 | |
416 | SYNC | |
417 | rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ | |
418 | rlwinm r0,r0,0,28,26 /* clear DR */ | |
419 | mtmsr r0 | |
420 | SYNC_601 | |
421 | isync | |
422 | lis r9,mmu_hash_lock@h | |
423 | ori r9,r9,mmu_hash_lock@l | |
424 | tophys(r9,r9) | |
425 | 10: lwarx r7,0,r9 | |
426 | cmpwi 0,r7,0 | |
427 | bne- 10b | |
428 | stwcx. r8,0,r9 | |
429 | bne- 10b | |
430 | eieio | |
431 | tlbie r3 | |
432 | sync | |
433 | TLBSYNC | |
434 | li r0,0 | |
435 | stw r0,0(r9) /* clear mmu_hash_lock */ | |
436 | mtmsr r10 | |
437 | SYNC_601 | |
438 | isync | |
439 | #else /* CONFIG_SMP */ | |
440 | tlbie r3 | |
441 | sync | |
442 | #endif /* CONFIG_SMP */ | |
443 | #endif /* ! CONFIG_40x */ | |
444 | blr | |
445 | ||
0ba3418b KG |
446 | #if defined(CONFIG_FSL_BOOKE) |
447 | /* | |
448 | * Flush MMU TLB, but only on the local processor (no broadcast) | |
449 | */ | |
450 | _GLOBAL(_tlbil_all) | |
451 | #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \ | |
452 | MMUCSR0_TLB2FI | MMUCSR0_TLB3FI) | |
453 | li r3,(MMUCSR0_TLBFI)@l | |
454 | mtspr SPRN_MMUCSR0, r3 | |
455 | 1: | |
456 | mfspr r3,SPRN_MMUCSR0 | |
457 | andi. r3,r3,MMUCSR0_TLBFI@l | |
458 | bne 1b | |
459 | blr | |
460 | ||
461 | /* | |
462 | * Flush MMU TLB for a particular process id, but only on the local processor | |
463 | * (no broadcast) | |
464 | */ | |
465 | _GLOBAL(_tlbil_pid) | |
466 | /* we currently do an invalidate all since we don't have per pid invalidate */ | |
467 | li r3,(MMUCSR0_TLBFI)@l | |
468 | mtspr SPRN_MMUCSR0, r3 | |
469 | 1: | |
470 | mfspr r3,SPRN_MMUCSR0 | |
471 | andi. r3,r3,MMUCSR0_TLBFI@l | |
472 | bne 1b | |
473 | blr | |
474 | ||
475 | /* | |
476 | * Flush MMU TLB for a particular address, but only on the local processor | |
477 | * (no broadcast) | |
478 | */ | |
479 | _GLOBAL(_tlbil_va) | |
480 | slwi r4,r4,16 | |
481 | mtspr SPRN_MAS6,r4 /* assume AS=0 for now */ | |
482 | tlbsx 0,r3 | |
483 | mfspr r4,SPRN_MAS1 /* check valid */ | |
484 | andis. r3,r4,MAS1_VALID@h | |
485 | beqlr | |
486 | rlwinm r4,r4,0,1,31 | |
487 | mtspr SPRN_MAS1,r4 | |
488 | tlbwe | |
489 | blr | |
490 | #endif /* CONFIG_FSL_BOOKE */ | |
491 | ||
492 | ||
9994a338 PM |
493 | /* |
494 | * Flush instruction cache. | |
495 | * This is a no-op on the 601. | |
496 | */ | |
497 | _GLOBAL(flush_instruction_cache) | |
498 | #if defined(CONFIG_8xx) | |
499 | isync | |
500 | lis r5, IDC_INVALL@h | |
501 | mtspr SPRN_IC_CST, r5 | |
502 | #elif defined(CONFIG_4xx) | |
503 | #ifdef CONFIG_403GCX | |
504 | li r3, 512 | |
505 | mtctr r3 | |
506 | lis r4, KERNELBASE@h | |
507 | 1: iccci 0, r4 | |
508 | addi r4, r4, 16 | |
509 | bdnz 1b | |
510 | #else | |
511 | lis r3, KERNELBASE@h | |
512 | iccci 0,r3 | |
513 | #endif | |
514 | #elif CONFIG_FSL_BOOKE | |
515 | BEGIN_FTR_SECTION | |
516 | mfspr r3,SPRN_L1CSR0 | |
517 | ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC | |
518 | /* msync; isync recommended here */ | |
519 | mtspr SPRN_L1CSR0,r3 | |
520 | isync | |
521 | blr | |
4508dc21 | 522 | END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE) |
9994a338 PM |
523 | mfspr r3,SPRN_L1CSR1 |
524 | ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR | |
525 | mtspr SPRN_L1CSR1,r3 | |
526 | #else | |
527 | mfspr r3,SPRN_PVR | |
528 | rlwinm r3,r3,16,16,31 | |
529 | cmpwi 0,r3,1 | |
530 | beqlr /* for 601, do nothing */ | |
531 | /* 603/604 processor - use invalidate-all bit in HID0 */ | |
532 | mfspr r3,SPRN_HID0 | |
533 | ori r3,r3,HID0_ICFI | |
534 | mtspr SPRN_HID0,r3 | |
535 | #endif /* CONFIG_8xx/4xx */ | |
536 | isync | |
537 | blr | |
538 | ||
539 | /* | |
540 | * Write any modified data cache blocks out to memory | |
541 | * and invalidate the corresponding instruction cache blocks. | |
542 | * This is a no-op on the 601. | |
543 | * | |
544 | * flush_icache_range(unsigned long start, unsigned long stop) | |
545 | */ | |
b76e59d1 | 546 | _KPROBE(__flush_icache_range) |
9994a338 PM |
547 | BEGIN_FTR_SECTION |
548 | blr /* for 601, do nothing */ | |
4508dc21 | 549 | END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) |
7dffb720 | 550 | li r5,L1_CACHE_BYTES-1 |
9994a338 PM |
551 | andc r3,r3,r5 |
552 | subf r4,r3,r4 | |
553 | add r4,r4,r5 | |
7dffb720 | 554 | srwi. r4,r4,L1_CACHE_SHIFT |
9994a338 PM |
555 | beqlr |
556 | mtctr r4 | |
557 | mr r6,r3 | |
558 | 1: dcbst 0,r3 | |
7dffb720 | 559 | addi r3,r3,L1_CACHE_BYTES |
9994a338 PM |
560 | bdnz 1b |
561 | sync /* wait for dcbst's to get to ram */ | |
562 | mtctr r4 | |
563 | 2: icbi 0,r6 | |
7dffb720 | 564 | addi r6,r6,L1_CACHE_BYTES |
9994a338 PM |
565 | bdnz 2b |
566 | sync /* additional sync needed on g4 */ | |
567 | isync | |
568 | blr | |
569 | /* | |
570 | * Write any modified data cache blocks out to memory. | |
571 | * Does not invalidate the corresponding cache lines (especially for | |
572 | * any corresponding instruction cache). | |
573 | * | |
574 | * clean_dcache_range(unsigned long start, unsigned long stop) | |
575 | */ | |
576 | _GLOBAL(clean_dcache_range) | |
7dffb720 | 577 | li r5,L1_CACHE_BYTES-1 |
9994a338 PM |
578 | andc r3,r3,r5 |
579 | subf r4,r3,r4 | |
580 | add r4,r4,r5 | |
7dffb720 | 581 | srwi. r4,r4,L1_CACHE_SHIFT |
9994a338 PM |
582 | beqlr |
583 | mtctr r4 | |
584 | ||
585 | 1: dcbst 0,r3 | |
7dffb720 | 586 | addi r3,r3,L1_CACHE_BYTES |
9994a338 PM |
587 | bdnz 1b |
588 | sync /* wait for dcbst's to get to ram */ | |
589 | blr | |
590 | ||
591 | /* | |
592 | * Write any modified data cache blocks out to memory and invalidate them. | |
593 | * Does not invalidate the corresponding instruction cache blocks. | |
594 | * | |
595 | * flush_dcache_range(unsigned long start, unsigned long stop) | |
596 | */ | |
597 | _GLOBAL(flush_dcache_range) | |
7dffb720 | 598 | li r5,L1_CACHE_BYTES-1 |
9994a338 PM |
599 | andc r3,r3,r5 |
600 | subf r4,r3,r4 | |
601 | add r4,r4,r5 | |
7dffb720 | 602 | srwi. r4,r4,L1_CACHE_SHIFT |
9994a338 PM |
603 | beqlr |
604 | mtctr r4 | |
605 | ||
606 | 1: dcbf 0,r3 | |
7dffb720 | 607 | addi r3,r3,L1_CACHE_BYTES |
9994a338 PM |
608 | bdnz 1b |
609 | sync /* wait for dcbst's to get to ram */ | |
610 | blr | |
611 | ||
612 | /* | |
613 | * Like above, but invalidate the D-cache. This is used by the 8xx | |
614 | * to invalidate the cache so the PPC core doesn't get stale data | |
615 | * from the CPM (no cache snooping here :-). | |
616 | * | |
617 | * invalidate_dcache_range(unsigned long start, unsigned long stop) | |
618 | */ | |
619 | _GLOBAL(invalidate_dcache_range) | |
7dffb720 | 620 | li r5,L1_CACHE_BYTES-1 |
9994a338 PM |
621 | andc r3,r3,r5 |
622 | subf r4,r3,r4 | |
623 | add r4,r4,r5 | |
7dffb720 | 624 | srwi. r4,r4,L1_CACHE_SHIFT |
9994a338 PM |
625 | beqlr |
626 | mtctr r4 | |
627 | ||
628 | 1: dcbi 0,r3 | |
7dffb720 | 629 | addi r3,r3,L1_CACHE_BYTES |
9994a338 PM |
630 | bdnz 1b |
631 | sync /* wait for dcbi's to get to ram */ | |
632 | blr | |
633 | ||
9994a338 PM |
634 | /* |
635 | * Flush a particular page from the data cache to RAM. | |
636 | * Note: this is necessary because the instruction cache does *not* | |
637 | * snoop from the data cache. | |
638 | * This is a no-op on the 601 which has a unified cache. | |
639 | * | |
640 | * void __flush_dcache_icache(void *page) | |
641 | */ | |
642 | _GLOBAL(__flush_dcache_icache) | |
643 | BEGIN_FTR_SECTION | |
4508dc21 DG |
644 | blr |
645 | END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) | |
9994a338 | 646 | rlwinm r3,r3,0,0,19 /* Get page base address */ |
7dffb720 | 647 | li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */ |
9994a338 PM |
648 | mtctr r4 |
649 | mr r6,r3 | |
650 | 0: dcbst 0,r3 /* Write line to ram */ | |
7dffb720 | 651 | addi r3,r3,L1_CACHE_BYTES |
9994a338 PM |
652 | bdnz 0b |
653 | sync | |
b98ac05d BH |
654 | #ifndef CONFIG_44x |
655 | /* We don't flush the icache on 44x. Those have a virtual icache | |
656 | * and we don't have access to the virtual address here (it's | |
657 | * not the page vaddr but where it's mapped in user space). The | |
658 | * flushing of the icache on these is handled elsewhere, when | |
659 | * a change in the address space occurs, before returning to | |
660 | * user space | |
661 | */ | |
9994a338 PM |
662 | mtctr r4 |
663 | 1: icbi 0,r6 | |
7dffb720 | 664 | addi r6,r6,L1_CACHE_BYTES |
9994a338 PM |
665 | bdnz 1b |
666 | sync | |
667 | isync | |
b98ac05d | 668 | #endif /* CONFIG_44x */ |
9994a338 PM |
669 | blr |
670 | ||
671 | /* | |
672 | * Flush a particular page from the data cache to RAM, identified | |
673 | * by its physical address. We turn off the MMU so we can just use | |
674 | * the physical address (this may be a highmem page without a kernel | |
675 | * mapping). | |
676 | * | |
677 | * void __flush_dcache_icache_phys(unsigned long physaddr) | |
678 | */ | |
679 | _GLOBAL(__flush_dcache_icache_phys) | |
680 | BEGIN_FTR_SECTION | |
681 | blr /* for 601, do nothing */ | |
4508dc21 | 682 | END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) |
9994a338 PM |
683 | mfmsr r10 |
684 | rlwinm r0,r10,0,28,26 /* clear DR */ | |
685 | mtmsr r0 | |
686 | isync | |
687 | rlwinm r3,r3,0,0,19 /* Get page base address */ | |
7dffb720 | 688 | li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */ |
9994a338 PM |
689 | mtctr r4 |
690 | mr r6,r3 | |
691 | 0: dcbst 0,r3 /* Write line to ram */ | |
7dffb720 | 692 | addi r3,r3,L1_CACHE_BYTES |
9994a338 PM |
693 | bdnz 0b |
694 | sync | |
695 | mtctr r4 | |
696 | 1: icbi 0,r6 | |
7dffb720 | 697 | addi r6,r6,L1_CACHE_BYTES |
9994a338 PM |
698 | bdnz 1b |
699 | sync | |
700 | mtmsr r10 /* restore DR */ | |
701 | isync | |
702 | blr | |
703 | ||
704 | /* | |
705 | * Clear pages using the dcbz instruction, which doesn't cause any | |
706 | * memory traffic (except to write out any cache lines which get | |
707 | * displaced). This only works on cacheable memory. | |
708 | * | |
709 | * void clear_pages(void *page, int order) ; | |
710 | */ | |
711 | _GLOBAL(clear_pages) | |
7dffb720 | 712 | li r0,4096/L1_CACHE_BYTES |
9994a338 PM |
713 | slw r0,r0,r4 |
714 | mtctr r0 | |
715 | #ifdef CONFIG_8xx | |
716 | li r4, 0 | |
717 | 1: stw r4, 0(r3) | |
718 | stw r4, 4(r3) | |
719 | stw r4, 8(r3) | |
720 | stw r4, 12(r3) | |
721 | #else | |
722 | 1: dcbz 0,r3 | |
723 | #endif | |
7dffb720 | 724 | addi r3,r3,L1_CACHE_BYTES |
9994a338 PM |
725 | bdnz 1b |
726 | blr | |
727 | ||
728 | /* | |
729 | * Copy a whole page. We use the dcbz instruction on the destination | |
730 | * to reduce memory traffic (it eliminates the unnecessary reads of | |
731 | * the destination into cache). This requires that the destination | |
732 | * is cacheable. | |
733 | */ | |
734 | #define COPY_16_BYTES \ | |
735 | lwz r6,4(r4); \ | |
736 | lwz r7,8(r4); \ | |
737 | lwz r8,12(r4); \ | |
738 | lwzu r9,16(r4); \ | |
739 | stw r6,4(r3); \ | |
740 | stw r7,8(r3); \ | |
741 | stw r8,12(r3); \ | |
742 | stwu r9,16(r3) | |
743 | ||
744 | _GLOBAL(copy_page) | |
745 | addi r3,r3,-4 | |
746 | addi r4,r4,-4 | |
747 | ||
748 | #ifdef CONFIG_8xx | |
749 | /* don't use prefetch on 8xx */ | |
7dffb720 | 750 | li r0,4096/L1_CACHE_BYTES |
9994a338 PM |
751 | mtctr r0 |
752 | 1: COPY_16_BYTES | |
753 | bdnz 1b | |
754 | blr | |
755 | ||
756 | #else /* not 8xx, we can prefetch */ | |
757 | li r5,4 | |
758 | ||
759 | #if MAX_COPY_PREFETCH > 1 | |
760 | li r0,MAX_COPY_PREFETCH | |
761 | li r11,4 | |
762 | mtctr r0 | |
763 | 11: dcbt r11,r4 | |
7dffb720 | 764 | addi r11,r11,L1_CACHE_BYTES |
9994a338 PM |
765 | bdnz 11b |
766 | #else /* MAX_COPY_PREFETCH == 1 */ | |
767 | dcbt r5,r4 | |
7dffb720 | 768 | li r11,L1_CACHE_BYTES+4 |
9994a338 | 769 | #endif /* MAX_COPY_PREFETCH */ |
7dffb720 | 770 | li r0,4096/L1_CACHE_BYTES - MAX_COPY_PREFETCH |
9994a338 PM |
771 | crclr 4*cr0+eq |
772 | 2: | |
773 | mtctr r0 | |
774 | 1: | |
775 | dcbt r11,r4 | |
776 | dcbz r5,r3 | |
777 | COPY_16_BYTES | |
7dffb720 | 778 | #if L1_CACHE_BYTES >= 32 |
9994a338 | 779 | COPY_16_BYTES |
7dffb720 | 780 | #if L1_CACHE_BYTES >= 64 |
9994a338 PM |
781 | COPY_16_BYTES |
782 | COPY_16_BYTES | |
7dffb720 | 783 | #if L1_CACHE_BYTES >= 128 |
9994a338 PM |
784 | COPY_16_BYTES |
785 | COPY_16_BYTES | |
786 | COPY_16_BYTES | |
787 | COPY_16_BYTES | |
788 | #endif | |
789 | #endif | |
790 | #endif | |
791 | bdnz 1b | |
792 | beqlr | |
793 | crnot 4*cr0+eq,4*cr0+eq | |
794 | li r0,MAX_COPY_PREFETCH | |
795 | li r11,4 | |
796 | b 2b | |
797 | #endif /* CONFIG_8xx */ | |
798 | ||
799 | /* | |
800 | * void atomic_clear_mask(atomic_t mask, atomic_t *addr) | |
801 | * void atomic_set_mask(atomic_t mask, atomic_t *addr); | |
802 | */ | |
803 | _GLOBAL(atomic_clear_mask) | |
804 | 10: lwarx r5,0,r4 | |
805 | andc r5,r5,r3 | |
806 | PPC405_ERR77(0,r4) | |
807 | stwcx. r5,0,r4 | |
808 | bne- 10b | |
809 | blr | |
810 | _GLOBAL(atomic_set_mask) | |
811 | 10: lwarx r5,0,r4 | |
812 | or r5,r5,r3 | |
813 | PPC405_ERR77(0,r4) | |
814 | stwcx. r5,0,r4 | |
815 | bne- 10b | |
816 | blr | |
817 | ||
9994a338 PM |
818 | /* |
819 | * Extended precision shifts. | |
820 | * | |
821 | * Updated to be valid for shift counts from 0 to 63 inclusive. | |
822 | * -- Gabriel | |
823 | * | |
824 | * R3/R4 has 64 bit value | |
825 | * R5 has shift count | |
826 | * result in R3/R4 | |
827 | * | |
828 | * ashrdi3: arithmetic right shift (sign propagation) | |
829 | * lshrdi3: logical right shift | |
830 | * ashldi3: left shift | |
831 | */ | |
832 | _GLOBAL(__ashrdi3) | |
833 | subfic r6,r5,32 | |
834 | srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count | |
835 | addi r7,r5,32 # could be xori, or addi with -32 | |
836 | slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count) | |
837 | rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0 | |
838 | sraw r7,r3,r7 # t2 = MSW >> (count-32) | |
839 | or r4,r4,r6 # LSW |= t1 | |
840 | slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2 | |
841 | sraw r3,r3,r5 # MSW = MSW >> count | |
842 | or r4,r4,r7 # LSW |= t2 | |
843 | blr | |
844 | ||
845 | _GLOBAL(__ashldi3) | |
846 | subfic r6,r5,32 | |
847 | slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count | |
848 | addi r7,r5,32 # could be xori, or addi with -32 | |
849 | srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count) | |
850 | slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32) | |
851 | or r3,r3,r6 # MSW |= t1 | |
852 | slw r4,r4,r5 # LSW = LSW << count | |
853 | or r3,r3,r7 # MSW |= t2 | |
854 | blr | |
855 | ||
856 | _GLOBAL(__lshrdi3) | |
857 | subfic r6,r5,32 | |
858 | srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count | |
859 | addi r7,r5,32 # could be xori, or addi with -32 | |
860 | slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count) | |
861 | srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32) | |
862 | or r4,r4,r6 # LSW |= t1 | |
863 | srw r3,r3,r5 # MSW = MSW >> count | |
864 | or r4,r4,r7 # LSW |= t2 | |
865 | blr | |
866 | ||
95ff54f5 PM |
867 | /* |
868 | * 64-bit comparison: __ucmpdi2(u64 a, u64 b) | |
869 | * Returns 0 if a < b, 1 if a == b, 2 if a > b. | |
870 | */ | |
871 | _GLOBAL(__ucmpdi2) | |
872 | cmplw r3,r5 | |
873 | li r3,1 | |
874 | bne 1f | |
875 | cmplw r4,r6 | |
876 | beqlr | |
877 | 1: li r3,0 | |
878 | bltlr | |
879 | li r3,2 | |
880 | blr | |
881 | ||
9994a338 PM |
882 | _GLOBAL(abs) |
883 | srawi r4,r3,31 | |
884 | xor r3,r3,r4 | |
885 | sub r3,r3,r4 | |
886 | blr | |
887 | ||
9994a338 PM |
888 | /* |
889 | * Create a kernel thread | |
890 | * kernel_thread(fn, arg, flags) | |
891 | */ | |
892 | _GLOBAL(kernel_thread) | |
893 | stwu r1,-16(r1) | |
894 | stw r30,8(r1) | |
895 | stw r31,12(r1) | |
896 | mr r30,r3 /* function */ | |
897 | mr r31,r4 /* argument */ | |
898 | ori r3,r5,CLONE_VM /* flags */ | |
899 | oris r3,r3,CLONE_UNTRACED>>16 | |
900 | li r4,0 /* new sp (unused) */ | |
901 | li r0,__NR_clone | |
902 | sc | |
41c2e949 JP |
903 | bns+ 1f /* did system call indicate error? */ |
904 | neg r3,r3 /* if so, make return code negative */ | |
905 | 1: cmpwi 0,r3,0 /* parent or child? */ | |
906 | bne 2f /* return if parent */ | |
9994a338 PM |
907 | li r0,0 /* make top-level stack frame */ |
908 | stwu r0,-16(r1) | |
909 | mtlr r30 /* fn addr in lr */ | |
910 | mr r3,r31 /* load arg and call fn */ | |
911 | PPC440EP_ERR42 | |
912 | blrl | |
913 | li r0,__NR_exit /* exit if function returns */ | |
914 | li r3,0 | |
915 | sc | |
41c2e949 | 916 | 2: lwz r30,8(r1) |
9994a338 PM |
917 | lwz r31,12(r1) |
918 | addi r1,r1,16 | |
919 | blr | |
920 | ||
9994a338 PM |
921 | /* |
922 | * This routine is just here to keep GCC happy - sigh... | |
923 | */ | |
924 | _GLOBAL(__main) | |
925 | blr | |
3d1229d6 ME |
926 | |
927 | #ifdef CONFIG_KEXEC | |
928 | /* | |
929 | * Must be relocatable PIC code callable as a C function. | |
930 | */ | |
931 | .globl relocate_new_kernel | |
932 | relocate_new_kernel: | |
933 | /* r3 = page_list */ | |
934 | /* r4 = reboot_code_buffer */ | |
935 | /* r5 = start_address */ | |
936 | ||
937 | li r0, 0 | |
938 | ||
939 | /* | |
940 | * Set Machine Status Register to a known status, | |
941 | * switch the MMU off and jump to 1: in a single step. | |
942 | */ | |
943 | ||
944 | mr r8, r0 | |
945 | ori r8, r8, MSR_RI|MSR_ME | |
946 | mtspr SPRN_SRR1, r8 | |
947 | addi r8, r4, 1f - relocate_new_kernel | |
948 | mtspr SPRN_SRR0, r8 | |
949 | sync | |
950 | rfi | |
951 | ||
952 | 1: | |
953 | /* from this point address translation is turned off */ | |
954 | /* and interrupts are disabled */ | |
955 | ||
956 | /* set a new stack at the bottom of our page... */ | |
957 | /* (not really needed now) */ | |
d9178f4c | 958 | addi r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */ |
3d1229d6 ME |
959 | stw r0, 0(r1) |
960 | ||
961 | /* Do the copies */ | |
962 | li r6, 0 /* checksum */ | |
963 | mr r0, r3 | |
964 | b 1f | |
965 | ||
966 | 0: /* top, read another word for the indirection page */ | |
967 | lwzu r0, 4(r3) | |
968 | ||
969 | 1: | |
970 | /* is it a destination page? (r8) */ | |
971 | rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */ | |
972 | beq 2f | |
973 | ||
974 | rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */ | |
975 | b 0b | |
976 | ||
977 | 2: /* is it an indirection page? (r3) */ | |
978 | rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */ | |
979 | beq 2f | |
980 | ||
981 | rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */ | |
982 | subi r3, r3, 4 | |
983 | b 0b | |
984 | ||
985 | 2: /* are we done? */ | |
986 | rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */ | |
987 | beq 2f | |
988 | b 3f | |
989 | ||
990 | 2: /* is it a source page? (r9) */ | |
991 | rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */ | |
992 | beq 0b | |
993 | ||
994 | rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */ | |
995 | ||
996 | li r7, PAGE_SIZE / 4 | |
997 | mtctr r7 | |
998 | subi r9, r9, 4 | |
999 | subi r8, r8, 4 | |
1000 | 9: | |
1001 | lwzu r0, 4(r9) /* do the copy */ | |
1002 | xor r6, r6, r0 | |
1003 | stwu r0, 4(r8) | |
1004 | dcbst 0, r8 | |
1005 | sync | |
1006 | icbi 0, r8 | |
1007 | bdnz 9b | |
1008 | ||
1009 | addi r9, r9, 4 | |
1010 | addi r8, r8, 4 | |
1011 | b 0b | |
1012 | ||
1013 | 3: | |
1014 | ||
1015 | /* To be certain of avoiding problems with self-modifying code | |
1016 | * execute a serializing instruction here. | |
1017 | */ | |
1018 | isync | |
1019 | sync | |
1020 | ||
1021 | /* jump to the entry point, usually the setup routine */ | |
1022 | mtlr r5 | |
1023 | blrl | |
1024 | ||
1025 | 1: b 1b | |
1026 | ||
1027 | relocate_new_kernel_end: | |
1028 | ||
1029 | .globl relocate_new_kernel_size | |
1030 | relocate_new_kernel_size: | |
1031 | .long relocate_new_kernel_end - relocate_new_kernel | |
1032 | #endif |